CN101996863B - Method for producing polished semiconductor wafer - Google Patents
Method for producing polished semiconductor wafer Download PDFInfo
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- CN101996863B CN101996863B CN2010102262072A CN201010226207A CN101996863B CN 101996863 B CN101996863 B CN 101996863B CN 2010102262072 A CN2010102262072 A CN 2010102262072A CN 201010226207 A CN201010226207 A CN 201010226207A CN 101996863 B CN101996863 B CN 101996863B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 200
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 238000005498 polishing Methods 0.000 claims abstract description 71
- 239000000463 material Substances 0.000 claims abstract description 26
- 238000012545 processing Methods 0.000 claims abstract description 17
- 235000012431 wafers Nutrition 0.000 claims description 197
- 238000000034 method Methods 0.000 claims description 55
- 238000000227 grinding Methods 0.000 claims description 45
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- 239000007788 liquid Substances 0.000 claims description 5
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- 238000007517 polishing process Methods 0.000 description 10
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02021—Edge treatment, chamfering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
- H01L21/67063—Apparatus for fluid treatment for etching
- H01L21/67075—Apparatus for fluid treatment for etching for wet etching
- H01L21/6708—Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
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- Engineering & Computer Science (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
Abstract
The invention relates to a method for producing a polished semiconductor wafer, comprising the following steps in the stated order: - slicing a semiconductor wafer from a rod composed of semiconductor material, - material-removing processing of at least one side of the semiconductor wafer, and - polishing of at least one side of the semiconductor wafer, wherein the semiconductor wafer has after the material-removing processing and before the polishing on at least one side to be polished, along its edge, a ring-shaped local elevation having a maximum height of at least 0.1 [mu]m, wherein the local elevation reaches its maximum height within a 10 mm wide ring lying at the edge of the semiconductor wafer.
Description
Technical field
The present invention relates to a kind of method of the semiconductor wafer for the manufacture of polishing, described method comprises a plurality of steps of following order:
-the rod that is made of semi-conducting material cuts out semiconductor wafer,
-at least one side of semiconductor wafer is carried out material removal process, and
Described at least one side of-polishing of semiconductor wafers.
Background technology
Semiconductor wafer has the front side of polishing usually, and device inserts in the described front side.Exigence relates to the flatness of front side day by day.In order to make the most probable number MPN destination device at semiconductor wafer, until essential flatness must be strictly guaranteed at the edge of front side as much as possible.
Be used for improving generally speaking the flatness of side surface of semiconductor wafer and the step that the effort of the overwhelming majority that improves specifically the flatness of front side concentrates on the material removal process of the semiconductor wafer that affects flatness all the time.They particularly comprise the step of grinding, grinding and polishing such as one or two side surface.In fact always carry out at least a polishing process that is implemented as the single or double polishing.Yet, as described in DE10302611A1, also can affect the flatness in the limit section zone of flatness, particularly side surface such as the treatment step on etched side surface.Semiconductor wafer is usually etched before first time polishing process, for example processes because the damage that grinding or grinding (or combination of these methods) effects on surface of semiconductor wafer caused to eliminate by the shaping of front.The Patent Application Publication of quoting a kind of engraving method, wherein, the liquid etchant that semiconductor wafer is exposed in etching process on the edge that is directed into semiconductor wafer flows down.For semiconductor wafer is obtained until the smooth side surface of most probable of the limit section of outermost, the etchant that the limit section of semiconductor wafer avoids flowing by means of special shielding part conductively-closed in etching process.Before polishing until the side surface of the smooth as far as possible semiconductor wafer of the limit section of outermost is considered to make the semiconductor wafer of polishing also to have the precondition of extraordinary geometry in limit section zone.Yet, have been found that the geometry in the limit section zone still has improved needs, even when having adopted the instruction of DE10302611A1.
Summary of the invention
Therefore, the objective of the invention is further to improve the geometry of semiconductor wafer in limit section zone of polishing.
Above-mentioned purpose is by a kind of method realization of the semiconductor wafer for the manufacture of polishing, and described method comprises a plurality of steps of following order:
-the rod that is made of semi-conducting material cuts out semiconductor wafer,
-at least one side of semiconductor wafer is carried out material removal process, and
Described at least one side of-polishing of semiconductor wafers,
Wherein, before after described material removal process, to polished described at least one side, polishing, semiconductor wafer has annular local eminence section along its limit section, described local eminence section has the maximum height of at least 0.1 μ m, and local eminence section reaches its maximum height in the wide ring of the 10mm at the limit of semiconductor wafer section place.
Different from the instruction of DE10302611A1, the inventor has been found that at smooth as far as possible semiconductor wafer before the polishing be not the precondition that obtains the best of good geometry after polishing at wafer limit section place.On the contrary, according to the present invention, be provided with slight local eminence section in the limit section zone of at least one side of polished semiconductor wafer, described protrusion is removed in polishing process.Polishing this moment can produce a kind of like this semiconductor wafer, itself until the limit section of outermost all have good flatness and do not have the limit of significantly collapsing.Preferably, protrusion is formed on the Bian Buchu of each side that stands to polish of semiconductor wafer, that is, in the situation that single-sided polishing is only in the situation that a side, form protrusion in twin polishing in both sides.
The processing parameter of the maximum height of protrusion and highly peaked position basis polishing step is subsequently selected.These processing parameters mainly comprise the velocity of rotation of composition, polishing plate and bearing part of contact, polishing pad quality (hardness), polishing slurries and the height that the main polishing that will reach is removed.On each side that stands to polish of semiconductor wafer, the material removal amount that produces by polishing is generally 3-30 μ m.The polishing removal amount is higher, just must be larger according to the height of protrusion of the present invention, in order to obtain desirable result.
According to the present invention, the maximum of local eminence section is arranged in along the annular region of the 10mm that extends internally from the edge of Waffer edge.Preferably, the height maximum of local eminence section is positioned on 5 millimeters of outermost of semiconductor wafer, namely be positioned at extend internally the surface of ring of 5mm from Waffer edge on.
According to the present invention, the height of local eminence section is at least 0.1 μ m.When the height of 0.1 μ m is following, even the result that in polishing process subsequently, in the situation of very little material removal amount, also no longer can obtain to expect.Preferably, be not higher than 10 μ m according to protrusion of the present invention, this is because otherwise can need very high polishing removal amount could obtain not have by means of polishing the smooth wafer limit section of limit section protrusion.Owing to these reasons, the height of the protrusion before polishing particularly preferably is positioned at the scope of 0.5-5 μ m.
Description of drawings
Below, referring to accompanying drawing the present invention and preferred embodiment are described in more detail, accompanying drawing comprises:
Fig. 1 shows the parameter according to protrusion of the present invention for the limit section place of describing semiconductor wafer;
Fig. 2 a, 2b and 2c schematically show by the situation of cup-shaped grinding disc process semiconductor wafers generation according to protrusion of the present invention;
Fig. 3 schematically shows etching by the shielding part that uses shield wafer limit section and produces situation according to protrusion of the present invention;
Fig. 4 schematically shows a kind of arrangement, and described arrangement comprises semiconductor wafer and shielding part, and described shielding part can be used in the engraving method, in order to produce the protrusion in the limit section zone that is positioned at semiconductor wafer at front side and the rear side of semiconductor wafer;
Fig. 5 schematically shows a kind of arrangement, and described arrangement comprises semiconductor wafer and shielding part, and described shielding part can be used in the engraving method, in order to only produce the protrusion in the limit section zone that is positioned at semiconductor wafer in a side; And
Fig. 6 shows the various limit section geometry by using different shielding parts and not having that the engraving method of shielding part produces.
Embodiment
As further describing basis of the present invention, at first use the example of circular semiconductor wafers to introduce geometric parameter (also please referring to Fig. 1-5).Yet the present invention also can be applicable to non-circular semiconductor wafer in principle.The physical boundary R of semiconductor wafer 1 is the distance of radius r apart from the center of semiconductor wafer 1, and forms the periphery of semiconductor wafer.Edge 4 parts of semiconductor wafer 1 are provided with type exterior feature section, and described type exterior feature section mechanically produces by forming tool, for example type exterior feature section grinding disc in so-called rounded at the edge step.The inner at the edge of the moulding of semiconductor wafer, namely the intermediate location from the faceted pebble of the peripheral type exterior feature section of semiconductor wafer to the surface of general planar represents with E, and represents with distance ρ apart from physical boundary R.The edge 4 of semiconductor wafer can be symmetrically or fillet asymmetricly.According to the limit section zone of the semiconductor wafer of the special care of the present invention distance apart from the 0-10mm of the physical boundary R of semiconductor wafer 1 on the front side 2 of semiconductor wafer 1 and rear side 3.The thickness d of semiconductor wafer 1 is corresponding with the distance between the front side of semiconductor wafer 2 and the rear side 3.
The height h of local eminence section
RAnd highly peaked position can be described by the limit of collapsing (ERO).ERO can be for example definite from the graduate device of Kobelco LER-310 by means of the measurement mechanism that can obtain in market, and described device operates according to oblique ray phase shift interference measuring principle.This measures the radial profile h (x) of the appearance structure that produces semiconductor wafer.In this case, the front side of semiconductor wafer or rear side or both sides simultaneously can be measured.
In order to determine important for purposes of the invention variable (maximum height of local eminence section and peaked position), the algorithm (referring to Fig. 1) of describing among the Application standard SEMI M69.With the parameters R OA that only in the standard that predetermined radial position place is determined, describes (" (ROA) measured on three rank fitting of a polynomials and the limit of collapsing after falling at position x place "; The size on the limit of collapsing at the x place, position after three rank fitting of a polynomials and subtraction thereof) difference uses continuous height profile to describe the present invention, and the below will describe determining of described height profile.In this case, x represents radial position as the distance that represents with mm of the physical boundary R of distance semiconductor wafer 1.
Basis that be used for to describe local eminence section is, defines a reference curve RL (x) by according to SEMI M69 the radial profile h (x) of the measurement of the appearance structure of semiconductor wafer being carried out three rank fitting of a polynomials.For the purposes of the present invention, the radial profile h (x) that reference curve RL (x) measures in radial zone 11 matches, described radial zone extends to the distance of x=30mm from the distance of the x=11mm of distance wafer physical boundary.Three different radial profile h (x) are shown among Fig. 1, and represent with P1, P2 and P3.
Three rank multinomial RL (x) that obtain are pushed out to the physical boundary (position x=0mm) of semiconductor wafer 1 subsequently, and the height tolerance h of the curve RL (x) of the radial profile h (x) that measures in the limit of 0-10mm section zone and extrapolation
R(x) determine by following difference formula: h
R(x)=h (x)-RL (x).This subtraction has been eliminated the global geometric shape (recessed, protrusion) of semiconductor wafer, so that h
R(x) in fact only reflect partial deviations with respect to global geometric shape, these partial deviations are vital for purposes of the invention.The size of the described deviation that changes with radial position in this manual, is called " height of protrusion " h
R(x), and the maximum positive deviation between actual radial profile and the extrapolated curve be called " maximum height of protrusion " h
R, maxProtrusion is reached below the radial position of its maximum height referred to as " peaked position " x
MaxUnder any circumstance, the present invention needs positive deviation at least in the regional area of the outermost 10mm of semiconductor wafer; Its maximum height h
R, maxBe at least 0.1 μ m.
Can all specify h for front side 2 and the rear side 3 of semiconductor wafer 1
R(x), be protrusion on the occasion of total expression.
Peaked position (the x of protrusion
Max) can just in time be positioned at the transition point E from the flat surfaces of semiconductor wafer 1 to the faceted pebble of rounded at the edge section, but also can further be offset towards the direction at the center of semiconductor wafer 1.Platform also is fine.Three kinds of different forms exemplarily are shown among Fig. 1, and wherein, outline line P1 is not according to outline line of the present invention.Outline line P2 and P3 are the possible variation patterns according to local eminence of the present invention section in the limit section zone.Have been found that in the limit section zone protrusion in addition at h
R(x) when the edge has descended again, also can improve the polishing after the local geometric shape.In this case, h
R(max) also can bear.Form (gradient of peaked height and position and rising) can be by means of the different formation specification of variables of the annular local eminence section that is used for limit section zone, thereby can optimally adapt to polishing step subsequently.Yet zone 12 interior enforcements that under any circumstance should be shown in Figure 1 are namely in outermost 10 millimeters enforcements of semiconductor wafer.
At should not obscuring mutually with overall spill geometry commonly known in the art according to local eminence of the present invention section of the limit section place of the outermost of semiconductor wafer, this overall spill geometry is for the flatness after the polishing process that improves subsequently equally.This overall spill geometry as the original geometric form that is used for twin polishing processing subsequently exemplarily is described in EP0750967A2.In contrast to this, according to the present invention, before polishing, local eminence section is arranged on and connects antermarginal zone.Have been found that this can irrespectively make with the global geometric shape of semiconductor wafer the polishing step limit of collapsing afterwards subsequently minimize.This verified the polishing after improved geometric shape parameters, SFQR for example, SFQD, SBIR (according to SEMI M1 appendix 1 and SEMI MF1530-0707), PSFQR (SEMIM70-1108), ESFQR, ESFQD, ESBIR, ESBID (SEMI M67-1108) and ZDD (SEMIM68-1108).Semiconductor wafer prepared in accordance with the present invention in addition to the polishing after global parameter for example GBIR (SEMI M1 appendix 1 and SEMI MF1530-0707) also have positive impact.In the limit of semiconductor wafer section zone according to protrusion of the present invention can-according to the requirement of subsequently polishing step namely according to the variation of the wafer geometry that is caused by described polishing step-make up with the basic configuration of overall recessed, smooth or optional protrusion.Therefore, can produce the semiconductor wafer that concerning polishing step subsequently, is optimised.
Parent material for generation of the protrusion in the limit section zone for example is the semiconductor wafer that cuts from the semiconductor rods that is generally monocrystal by means of multi-wire saw.Described semiconductor wafer stands material removal process subsequently, and described material removal process generally includes a plurality of steps.Exemplarily, described wafer is mechanically processed in both sides, and for example grinding or grinding is to remove the sawing groove.Produce in an appropriate steps of material removal process according to local eminence of the present invention section.This for example can be undertaken by grinding or etching.
In the first embodiment of the present invention, protrusion produces by grinding, schematically shown in Figure 2.
Protrusion can produce or produce in the both sides of semiconductor wafer 1 by double-side grinding order or the while in a side of semiconductor wafer 1 by the single face grinding.Under any circumstance, described processing is preferably implemented by means of cup-shaped grinding disc 21, and described cup-shaped grinding disc 21 rotates around the axis 22 with the Surface Vertical of semiconductor wafer 1.In the situation of single face grinding and double-side grinding sequentially, semiconductor wafer 1 is fixed on the chuck 23 by a side in processing procedure, and the opposite side of semiconductor wafer 1 is processed by means of cup-shaped grinding disc 21.This in the situation that the single face grinding only carry out in a side; In the situation of double-side grinding of order, semiconductor wafer is reversed after processing the first side, and namely processed the first side is clamped on the chuck, and also untreated the second side is ground.In the situation of double-side grinding of order, the protrusion that produces in the first side of semiconductor wafer in first step is not resisted against in second step on the chuck 23, and namely chuck 23 must have the diameter less than semiconductor wafer 1 in this case.On the contrary, at the same time in the situation of double-side grinding, semiconductor wafer is not firmly fixed, but between two hydrostatic support spares, be directed (not shown) in substantially non-binding mode, and simultaneously processed on both sides by means of two relative cup-shaped grinding discs 21, described cup-shaped grinding disc rotates around the pivot center 22 of collinear setting.This technology also is called " double plate grinding ", DDG.
In order to produce according to protrusion of the present invention, in the situation that the single or double grinding must be noted that to guarantee at the limit of semiconductor wafer section place: the whole surface of processing the semiconductor wafer except the limit section zone of outermost.This can be by selecting to have corresponding little external diameter r
ACup-shaped grinding disc 21 and correspondingly locate semiconductor wafer 1 with respect to cup-shaped grinding disc 21 and realize, as shown in Figure 2.In this case, cup-shaped grinding disc carries out grinding at the center of semiconductor wafer all the time, namely puts into practice differently from usually traditional, can grinding surpass the limit section of semiconductor wafer, namely so that limit section zone is not processed.The desired width w of the radius r of semiconductor wafer 1 and the limit section protrusion that will produce
RAccurate dimension to cup-shaped grinding disc (covers the external diameter r of the annular region of abrasive material
AWith width d
s) most important.The material area amount depends on the finishing method subsequently of expectation-namely required-protrusion height h of Bian section
R
Grinding is particularly suitable for producing the local eminence section of flat condition.
The step of the sudden change between the flat surfaces of semiconductor wafer and the limit section protrusion may have problems in polishing subsequently.Therefore, employed grinding disc can be in the outer radius chamfering, to prevent from occurring the step of sudden change between processed zone and not processed zone.The level and smooth of transition portion between flat surfaces and the limit section protrusion also can be realized by removal etching subsequently.
According to the second embodiment, also can produce by means of engraving method according to protrusion of the present invention in the limit of semiconductor wafer section zone for example produces in the mode of describing among the DE10302611A1.Different from DE10302611A1, shielding part with and be constructed such that with respect to the arrangement of semiconductor wafer: it is so good that limit section zone conductively-closed in etching process of semiconductor wafer gets, thus because the further reduction that local material is removed and protrusion occurs in limit section zone.Suitable arrangement is shown among Fig. 3 with general view, is illustrated in greater detail in the Figure 4 and 5.
In etching process (referring to Fig. 3), the preferred semiconductor wafer 1 of mainly being made by silicon is exposed to liquid etchant and flows down, and described liquid etchant flows to the edge 4 of semiconductor wafer 1 with the specific flow rates parallel with side surface (front side 2 and rear side 3).The flow direction of etchant represents with arrow 7 in Fig. 3.Suitable etchant comprises alkalescence and acid solution.Yet, preferred acidic solution, this is because they are obviously lower with the danger that metal pollutant imports in the semi-conducting material.Particularly preferred etchant comprises aqueous hydrofluoric acid solution, at least a oxidizing acid, particularly preferably nitric acid, and other additives in the suitable situation.Also particularly preferably, little bubble is dispersed in the etchant, removes to obtain uniform etching.This can for example implement according to US5451267.In order to obtain as far as possible uniformly material removal, semiconductor wafer rotates in etching process.The rotation of semiconductor wafer represents with arrow 9 in Fig. 3.Semiconductor wafer for example rotates by the driving shaft 8 of at least one rotation.In Fig. 3, exemplarily show three driving shafts 8.Shielding part 5 is positioned at the upstream at the edge 4 of semiconductor wafer 1 when streamwise 7 is watched, described shielding part prevents that the part at edge 4 from suffering etchant.
The second embodiment of the present invention so that the edge 4 of the semiconductor wafer 1 that etchant flows in the above with at least part of conductively-closed of the mode shown in the Figure 4 and 5.This means, be positioned at least a portion at the edge 4 of the semiconductor wafer on the flow direction 7 of etchant, comprise the outermost regions of the flat surfaces of semiconductor wafer, conductively-closed.Yet, shielded fully if be positioned at the circumference of the semiconductor wafer on the flow direction of etchant, be maximum to the shielding action of the geometry in the limit section zone of the side surface of semiconductor wafer.Therefore, this also is particularly preferred.
In order to realize this point, shielding part 5 is when the upstream that is arranged on the edge 4 of semiconductor wafer 1 when the flow direction 7 of etchant is watched, with DE10302611A1 in the similar mode of mode described arrange.Yet different from the prior art, shielding part and be constructed such that with respect to the arrangement of semiconductor wafer: protrusion according to the present invention appears in etching process in the limit section zone of semiconductor wafer.
Especially, this is possible in the arrangement shown in the Figure 4 and 5.Shielding part 5 have from the edge of semiconductor wafer farthest lower boundary H and from the edge of semiconductor wafer immediate coboundary G.The size of shielding part, particularly length 1 and height h are mainly determined by the size of semiconductor wafer.The length 1 at least diameter than semiconductor wafer is slightly large.Be the semiconductor wafer of 300mm for diameter, height h, namely the distance between coboundary G and the lower boundary H is preferably 5-200mm, is particularly preferably 30-180mm.According to shown in respect to the cutaway view of the side surface 2 of semiconductor wafer 1,3 vertical directions, what lower boundary H can be for straight or circle.And according to described cutaway view, the body of shielding part 5 can have the constant rectangle perimeter of thickness t, or can implement (not shown) towards the mode that shrink on one or two border.When a plurality of semiconductor wafer of while etching, the thickness t of shielding part is limited by the clearance distance between each semiconductor wafer.Distance between two adjacent shielding parts should be chosen to make etching media to flow through between shielding part with enough amounts.Distance beta between the physical boundary R of semiconductor wafer 1 and the coboundary G of shielding part 5 should be at least 0.1mm, but also can be obviously large.
For optimally shield near the wafer surface (front side 2 and/or rear side 3) the edge 4 the zone and for by means of etching process at limit section region generating protrusion, shielding part 5 preferably has at least one projection (protuberance 10), described projection with the surperficial parallel plane of semiconductor wafer on protrude towards the direction at the center of semiconductor wafer 1.Figure 4 and 5 show in the both sides of semiconductor wafer 1 respectively has a protuberance 10; Yet, also can contemplate, save the protuberance 10 of a side fully.
In Figure 4 and 5, the mark 2 that is used for all variablees relates to front side 2 or the corresponding protuberance 10 of semiconductor wafer, and label 3 relates to rear side or the corresponding protuberance 10 of semiconductor wafer.Exemplarily, γ
2Height (that is, the end S of protuberance of the protuberance 10 of the front side of expression shielding semiconductor wafer
2And the length of the distance between the coboundary G of shielding part 5), γ
3Height (that is, the end S of protuberance of the protuberance 10 of the rear side of expression shielding semiconductor wafer
3And the length of the distance between the coboundary G of shielding part 5).Compare, sequence number i relates to two protuberances, i.e. γ
iExpression γ
2Or γ
3
The thickness W of protuberance 10
iBe significantly less than the thickness t of shielding part, so that when watching perpendicular to the surface of semiconductor wafer 1, between semiconductor wafer 1 (having thickness d) and protuberance 10, still remain with apart from a
iWall thickness W
iShould be between 0.1-1mm.The side 2 of semiconductor wafer and 3 and protuberance 10 between apart from a
iShould be between 0.1-1mm.Protuberance 10 is evenly stopping away from a side of semiconductor wafer 1 and the surface of shielding part 5.Protuberance has height γ
iIf have two protuberances 10, then forming the degree of depth between protuberance 10 is γ
i, width is the breach 6 of n, semiconductor wafer radially extend into length Δ in the described breach
iEspecially, Δ
i＞ρ
i, that is to say, the flat surfaces of semiconductor wafer is also shielded by at least one protuberance at Bian Buchu.The width n of breach should be chosen to make the zone of the conductively-closed of semiconductor wafer not contact with protuberance and semiconductor wafer can hang down in the breach reliably.
The length Δ
iHeight γ with protuberance 10
iDifference Δ with distance beta
i=γ
i-β is consistent.On the side of expectation generation according to protrusion of the present invention of semiconductor wafer, the length Δ
iPreferably in the scope of 1-10mm, in the scope particularly preferably in 1-5mm.
If the both sides that for example were desirably in semiconductor wafer 1 before twin polishing is processed produce the protrusion of same type, then shielding part 5 is constructed symmetrically with respect to the symmetrical plane of semiconductor wafer, as shown in Figure 4.Especially, the height γ of the protuberance 10 of both sides
iIdentical, i.e. γ
2=γ
3This also means Δ naturally
2=Δ
3Thereby,, the both sides 2 of semiconductor wafer and 3 are in the in an identical manner conductively-closed of zone of limit section.
Compare, if only produce in a side of semiconductor wafer 1 according to the protrusion expectation of limit of the present invention section, for example only 2 produce to prepare the single-sided polishings of front side in the front side, then preferably make shielding part 5 have asymmetrical execution mode, make especially protuberance 10 have asymmetrical execution mode, as shown in Figure 5.If the height γ of the protuberance 10 of the front side of shielding semiconductor wafer
2Height γ with the protuberance 10 of the rear side of shielding semiconductor wafer
3Difference, then can be on a side of semiconductor wafer (in the situation that Fig. 5, on front side 2) than producing larger protrusion at opposite side.Especially, the geometry of shielding part can be selected to protrusion according to the present invention is created on the side of semiconductor wafer by means of engraving method, and the opposite side of semiconductor wafer almost keeps fully smooth according to the instruction of DE10302611A1.
All shielding part parameters that provide can affect position and the yardstick of protrusion according to the present invention in the limit of semiconductor wafer section zone, and must adapt to polishing step subsequently.The wall thickness W of protuberance
iWith height γ
iAnd between the inboard of semiconductor wafer 1 and protuberance 10 apart from a
iAlso can asymmetricly implement.The other important parameter arranged side by side with the physical dimension of shielding part is the flow rate of the etching media in the etching process and the velocity of rotation of semiconductor wafer.These parameters should be selected by means of simple preliminary experiment in suitable mode, in order to obtain according to effect of the present invention.
Also can produce by means of additive method according to protrusion of the present invention.Exemplarily, protrusion can produce by penetrate etchant at least one side spray of semiconductor wafer, and wherein, that limit section zone that the expectation of semiconductor wafer produces protrusion is capped.In this way, it is lower that limit section zone is not exposed to the etching erosion, thereby at limit section region generating protrusion.
The cleaning of implementing in advance and afterwards in polishing subsequently and the suitable situation should be carried out according to prior art.At least at least one of the front side of semiconductor wafer is performed all over polishing.Polishing can be used as single-sided polishing or is performed as twin polishing.In the situation of the single-sided polishing of front side, semiconductor wafer for example bonds on the supporting bracket by rear side is fixing.In the situation that twin polishing, semiconductor wafer is arranged in the breach of bearing part in the mode that can move freely.
In polishing process subsequently, the geometrical defect that deliberately produces in etching process is removed and is accurately compensated by this of wafer limit section zone can cause collapsing material that the part on limit increases, thereby, produced a kind of until the extremely smooth semiconductor wafer at edge.
If front side polishing multipass, advantageously, the first pass polishing process is configured to stock removal polishing, last polishing process is configured to contact polishing (touch polishing), obviously different aspect the material removal amount that they reach in polishing process, in the situation that the contact polishing, material removal amount is generally 2 μ m or less, and in the situation that stock removal polishing, material removal amount is generally 3 μ m or more.Except last polishing process, semiconductor wafer also can be coated, for example by in the front side deposit epitaxial layers and/or by utilizing the polycrystalline material layer and/or utilizing oxide layer sealing rear side.On the every side that has had in limit section zone before according to local eminence of the present invention section, the material removal amount that is produced by polishing is preferably in the scope of 3-30 μ m.
A kind of particularly preferred processing procedure for the manufacture of the claimed semiconductor wafer of the present invention comprises: cut out semiconductor wafer by the sawing monocrystal; The edge of round and smooth semiconductor wafer, if suitable, the grinded semiconductor wafer, described grinding can be used as single face grinding or order or double-side grinding simultaneously and implements, and/or grinding, wet chemical etching, if suitablely carry out the seamed edge polishing, and polishing of semiconductor wafers, described polishing is carried out once at least, carries out cleaning between these are processed, and carries out the one or many coating processing after the last polishing of side surface.Can preferably produce in grinding or etched situation according to local eminence of the present invention section in limit section zone perhaps also can expect being used in combination these two kinds of processes.Exemplarily, the limit of semiconductor wafer section place according to the passing through the protrusion that grinding produces and can be formed again in addition of the first embodiment of the present invention, and suitable can replenishing by means of etching step according to a second embodiment of the present invention how.
Example and comparative example
The semiconductor wafer that is made of silicon is that the cylindrical monocrystalline silicon cutting of 300mm forms by multi-wire saw by diameter.All semiconductor wafers are processed in an identical manner by simultaneous double-side grinding subsequently.Then semiconductor wafer stands etching process.Hydrogen fluoride/the salpeter solution that has the little bubble of dispersion by use, 25 μ m (summation of the etching removal amount of forward and backward side) are etched altogether.The velocity of rotation of semiconductor wafer is to be 3.0rpm in the situation of 165l/min at the rate of influx that etching media enters etching bath in etching process.
In the etching process of semiconductor wafer, various limit section geometry produces by the limit section zone of shielding semiconductor wafer differently.At this, use following the setting:
Comparative example 1: do not have shielding part
Comparative example 2: have shielding part (the t=2.5mm/ γ according to Fig. 4
2=γ
3=0.4mm/ Δ
i=0.25mm)
Example: have shielding part (the t=2.5mm/ γ according to Fig. 4
2=γ
3=2.0mm/ Δ
i=1.85mm)
The width n of breach 6 is 2mm in all examples He in the comparative example.
Semiconductor wafer is measured by means of the limit measurement mechanism Kobelco LER 310 that collapses after etching.
Fig. 6 shows near the corresponding radial profile h (x) of the appearance structure of the semiconductor wafer the edge, and wherein, the left side ordinate represents the outline line h of front side
2(x) (upper three curves), the right side ordinate represents the outline line h of the rear side of semiconductor wafer
3(x) (lower three curves).In the situation that comparative example 1 (does not have shielding part; Short stroke of dotted line among Fig. 6), in forward and backward side the limit of significantly collapsing has appearred all.In the situation that comparative example 2 (have shielding part, and semiconductor wafer 1 inserts the insertion depth Δ of breach 6
i=0.25mm; Pecked line among Fig. 6) also can additionally find to have the limit of collapsing, compare with comparative example 1, this limit of collapsing reduces.According to example, only at obvious larger insertion depth Δ
iJust produce at wafer limit section place in the situation of=1.85mm according to local eminence of the present invention section, this local eminence section has the maximum height h of approximate 1.2 μ m
R, max(solid line among Fig. 6).Maximum height is approximately 1.7mm apart from the distance of Waffer edge.
After measuring, distribute to equably altogether eight polishing passages according to the semiconductor wafer of all examples and comparative example, and be that the Twp-sided polishing machine of AC 2000 polishes in the model from Peter Wolters AG.The polishing removal amount is 20 μ m (summation of the polishing removal amount of forward and backward side) altogether.Semiconductor wafer is cleaned after polishing, then is their flatness (PSFQR) of measurement mechanism measurement of Wafersight by means of the model from KLA-Tencor company.The average that obtains and the further result of statistical estimate are provided in the following table.
| Comparative example 1 | Comparative example 2 | Example | |
| Wafer number n | 18 | 33 | 36 |
| Average PSFQR[nm] | 49.1 | 34.7 | 29.1 |
| Standard deviation [nm] | 3.1 | 2.6 | 2.8 |
| 10% value [nm] | 45.7 | 31.2 | 25.5 |
| 50% value [nm] | 49.5 | 34.0 | 29.5 |
| 90% value [nm] | 53.0 | 38.0 | 32.5 |
| 95% value [nm] | 53.3 | 38.0 | 33.0 |
| 99.7% value [nm] | 54.9 | 38.9 | 33.0 |
The boundary condition that PSFQR measures is:
Edge exclusion zone EE=2mm
Measurement field size=20mm * 20mm
Side-play amount=the 10mm of the grid on the x direction
Side-play amount=the 10mm of the grid on the y direction
Be clear that, under identical burnishing parameters, the semiconductor wafer that has in limit section zone according to protrusion of the present invention (example) reaches best PSFQR after polishing
AvgValue.
The present invention is applicable to all semiconductor wafers that stand at last the single or double polishing.These semiconductor wafers particularly are provided for the monocrystalline semiconductor wafer of making electronic device.These semiconductor wafers preferably mainly are made of silicon.
Claims (8)
1. method of semiconductor wafer for the manufacture of polishing, described method comprises a plurality of steps of following order:
-the rod that is made of semi-conducting material cuts out semiconductor wafer,
-at least one side of semiconductor wafer is carried out material removal process, and
Described at least one side of-polishing of semiconductor wafers,
Wherein, before after described material removal process, to polished described at least one side, polishing, semiconductor wafer has annular local eminence section along its limit section, described local eminence section has the maximum height of at least 0.1 μ m, and local eminence section reaches its maximum height in the wide ring of the 10mm at the limit of semiconductor wafer section place.
2. the method for claim 1 is characterized in that, local eminence section reaches its maximum height in the wide ring of the 5mm at the limit of semiconductor wafer section place.
3. such as arbitrary described method among the claim 1-2, it is characterized in that, the maximum height of described local eminence section is 0.1-10 μ m.
4. such as arbitrary described method among the claim 1-2, it is characterized in that, the maximum height of described local eminence section is 0.5-5 μ m.
5. such as arbitrary described method among the claim 1-2, it is characterized in that, on each side that stands to polish of semiconductor wafer, the material removal amount that produces by polishing is 3-30 μ m.
6. such as arbitrary described method among the claim 1-2, it is characterized in that, described material removal process comprises: at least a liquid etchant that utilizes is to the processing of semiconductor wafer, wherein, etchant in processing procedure with the surperficial almost parallel of semiconductor wafer flow on the edge of semiconductor wafer, local eminence section directly gives birth at described ring upper reaches movable property to prevent etchant by the ring at the limit section place of shadow shield semiconductor wafer at least.
7. such as arbitrary described method among the claim 1-2, it is characterized in that, described material removal process comprises: at least a liquid etchant that utilizes is to the processing of semiconductor wafer, wherein, etchant is ejected at least one side of semiconductor wafer, and the described ring at the limit section of semiconductor wafer place is at least part of covered.
8. such as arbitrary described method among the claim 1-2, it is characterized in that, described material removal process comprises: at least a by means of the grinding processing of at least one cup-shaped grinding disc at least one side of semiconductor wafer, wherein, described at least one cup-shaped grinding disc is positioned to make the described ring at limit section place of semiconductor wafer not processed with respect to semiconductor wafer in the grinding processing procedure, thereby the surface at described ring in the grinding processing procedure produces local eminence section.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE102009037281.4 | 2009-08-12 | ||
| DE102009037281A DE102009037281B4 (en) | 2009-08-12 | 2009-08-12 | Process for producing a polished semiconductor wafer |
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| Publication Number | Publication Date |
|---|---|
| CN101996863A CN101996863A (en) | 2011-03-30 |
| CN101996863B true CN101996863B (en) | 2013-04-10 |
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| US (1) | US8409992B2 (en) |
| JP (1) | JP5323016B2 (en) |
| KR (1) | KR101432863B1 (en) |
| CN (1) | CN101996863B (en) |
| DE (1) | DE102009037281B4 (en) |
| SG (2) | SG169267A1 (en) |
| TW (1) | TWI420581B (en) |
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| US8952496B2 (en) * | 2009-12-24 | 2015-02-10 | Sumco Corporation | Semiconductor wafer and method of producing same |
| US9242333B2 (en) | 2012-05-02 | 2016-01-26 | Memc Singapore Pte. Ltd. | Systems and methods for ingot grinding |
| DE102013204830B4 (en) * | 2013-03-19 | 2014-10-09 | Siltronic Ag | Method and apparatus for treating a semiconductor wafer with an etching medium |
| DE102015224933A1 (en) * | 2015-12-11 | 2017-06-14 | Siltronic Ag | Monocrystalline semiconductor wafer and method for producing a semiconductor wafer |
| US10600634B2 (en) * | 2015-12-21 | 2020-03-24 | Globalwafers Co., Ltd. | Semiconductor substrate polishing methods with dynamic control |
| CN108807138A (en) * | 2017-04-28 | 2018-11-13 | 胜高股份有限公司 | Silicon Wafer and its manufacturing method |
| DE102017210423A1 (en) * | 2017-06-21 | 2018-12-27 | Siltronic Ag | Method, control system and plant for processing a semiconductor wafer and semiconductor wafer |
| JP6451825B1 (en) * | 2017-12-25 | 2019-01-16 | 株式会社Sumco | Wafer double-side polishing method |
| KR102483923B1 (en) * | 2017-12-27 | 2023-01-02 | 삼성전자 주식회사 | semiconductor wafer having bevel portion |
| DE102018200415A1 (en) * | 2018-01-11 | 2019-07-11 | Siltronic Ag | Semiconductor wafer with epitaxial layer |
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Also Published As
| Publication number | Publication date |
|---|---|
| SG187487A1 (en) | 2013-02-28 |
| TW201106422A (en) | 2011-02-16 |
| DE102009037281B4 (en) | 2013-05-08 |
| DE102009037281A1 (en) | 2011-02-17 |
| SG169267A1 (en) | 2011-03-30 |
| CN101996863A (en) | 2011-03-30 |
| KR20110016822A (en) | 2011-02-18 |
| JP2011040753A (en) | 2011-02-24 |
| US20110039411A1 (en) | 2011-02-17 |
| JP5323016B2 (en) | 2013-10-23 |
| KR101432863B1 (en) | 2014-08-26 |
| US8409992B2 (en) | 2013-04-02 |
| TWI420581B (en) | 2013-12-21 |
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