CN102034709B - Method for amplifying process window of PMOS (P-channel metal oxide semiconductor) core device - Google Patents
Method for amplifying process window of PMOS (P-channel metal oxide semiconductor) core device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 127
- 230000008569 process Effects 0.000 title claims abstract description 73
- 239000004065 semiconductor Substances 0.000 title abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 4
- 150000004706 metal oxides Chemical class 0.000 title abstract description 4
- 238000002347 injection Methods 0.000 claims abstract description 40
- 239000007924 injection Substances 0.000 claims abstract description 40
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 35
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 11
- 150000004767 nitrides Chemical class 0.000 claims abstract description 9
- 150000002500 ions Chemical class 0.000 claims description 88
- 238000005516 engineering process Methods 0.000 claims description 62
- 238000005468 ion implantation Methods 0.000 claims description 36
- 229920005591 polysilicon Polymers 0.000 claims description 32
- 229910052796 boron Inorganic materials 0.000 claims description 25
- -1 boron ion Chemical class 0.000 claims description 12
- 229910015900 BF3 Inorganic materials 0.000 claims description 11
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 10
- WTEOIRVLGSZEPR-UHFFFAOYSA-N boron trifluoride Chemical compound FB(F)F WTEOIRVLGSZEPR-UHFFFAOYSA-N 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 9
- 238000005224 laser annealing Methods 0.000 claims description 6
- 238000000151 deposition Methods 0.000 abstract description 9
- 239000002184 metal Substances 0.000 abstract description 3
- 229910052751 metal Inorganic materials 0.000 abstract description 3
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 238000000137 annealing Methods 0.000 description 8
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000004151 rapid thermal annealing Methods 0.000 description 6
- 101000599782 Homo sapiens Insulin-like growth factor 2 mRNA-binding protein 3 Proteins 0.000 description 4
- 101000960626 Homo sapiens Mitochondrial inner membrane protease subunit 2 Proteins 0.000 description 4
- 101000702394 Homo sapiens Signal peptide peptidase-like 2A Proteins 0.000 description 4
- 101000828788 Homo sapiens Signal peptide peptidase-like 3 Proteins 0.000 description 4
- 101000960621 Homo sapiens U3 small nucleolar ribonucleoprotein protein IMP3 Proteins 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 102100030403 Signal peptide peptidase-like 2A Human genes 0.000 description 4
- 102100023501 Signal peptide peptidase-like 3 Human genes 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 230000001771 impaired effect Effects 0.000 description 4
- 230000035755 proliferation Effects 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 101000599778 Homo sapiens Insulin-like growth factor 2 mRNA-binding protein 1 Proteins 0.000 description 3
- 101000988591 Homo sapiens Minor histocompatibility antigen H13 Proteins 0.000 description 3
- 102100029083 Minor histocompatibility antigen H13 Human genes 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910004219 SiNi Inorganic materials 0.000 description 2
- 150000001638 boron Chemical class 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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Abstract
The invention discloses a method for amplifying the process window of a PMOS (P-channel metal oxide semiconductor) core device, which comprises: carrying out a first ion injection course on the formed polycrystalline silicon layer after a gate oxide layer and a polycrystalline silicon layer are successively formed on a substrate; etching the gate oxide layer and the polycrystalline silicon layer to form a grid and form first side walls on both sides of the grid; carrying out a shallow ion injection process to form a shallow doped drain region and form a second side wall on the external side of the first side wall; carrying out a deep source/drain region ion injection process, wherein the deep source/drain region ion injection process comprises a first source/drain region ion injection course and a second source/drain region ion injection course; depositing a high-stress nitride layer respectively on a grid region, a source region and a drain region; and carrying out an ohmic contact process and a top metal wiring process. The method provided by the invention is used for amplifying the process window of the PMOS core device, enhancing the yield of the product and saving the process cost.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, be specifically related to a kind of method of process window (Process Window) of the PMOS of increase core devices.
Background technology
At present; Be accompanied by the develop rapidly of semiconductor fabrication; Semiconductor device is in order to reach arithmetic speed faster, bigger memory data output and more function; Wafer develops towards higher component density, high integration direction, and the manufacturing technology of semiconductor device has got into 65nm and even 45nm process node, and the minimum feature size of grid width has reached 45nm or littler.
And in the manufacturing process of complementary metal oxide semiconductors (CMOS) (CMOS) device; Some technological processes will be to the performance of metal oxide semiconductor field effect tube (MOSFET); Particularly the performance of p NMOS N-channel MOS N (PMOS) core parts causes bigger influence, thereby makes the performance of formed semiconductor components and devices also decrease.
Fig. 1 is the flow chart that forms the method for PMOS in the prior art, and Fig. 2 A～2G is the sketch map that forms the method for PMOS in the prior art.In the prior art, the method for formation PMOS comprises the step that is described below:
Step 101 forms gate oxide and polysilicon layer successively on substrate.
Shown in Fig. 2 A, in this step, will at first on substrate 1, form gate oxide 2, and then on gate oxide 2, deposit a polysilicon layer 3.
Step 102 is carried out etching to said gate oxide and polysilicon layer, forms grid.
Shown in Fig. 2 B, in this step, will make public, technology such as etching, thereby form grid 301 above-mentioned polysilicon layer 3 and gate oxide 2.
Step 103 forms first side wall (Offset Spacer) in the both sides of said grid.
Shown in Fig. 2 C, in this step, will form first side wall 4 in the both sides of grid 301, said first side wall 4 is generally formed by silica/silicon nitride medium film combinations.The purpose of this first side wall 4 that forms is to reserve certain distance into the shallow ion injection region horizontal proliferation in follow-up rapid thermal annealing (RTA) technology; Thereby the raceway groove of guaranteeing grid 301 belows has certain width; With the short-channel effect of avoiding follow-up shallow ion injection technology to be brought, cause channel width to narrow down and the situation of (punch through) phenomenon and leakage current occurs puncturing.
Step 104 is carried out the shallow ion injection technology, to form shallow doped drain (LDD, Lightly DopedDrain) district.
Shown in Fig. 2 D, in this step, will be mask with first side wall 4 and grid 301, carry out the shallow ion injection technology, thereby on substrate 1, form shallow doped drain (LDD, Lightly Doped Drain) district 5.
After carrying out above-mentioned shallow ion injection technology, also can carry out follow-up rapid thermal anneal process (for example, laser annealing technique etc.), make the horizontal proliferation of shallow ion injection region, help the formation of shallow doped drain 5; In addition, above-mentioned rapid thermal anneal process can also be repaired lattice impaired when carrying out the shallow ion injection technology, and can make the ion distribution of being injected more even.
Step 105 forms second side wall in the outside of above-mentioned first side wall.
Shown in Fig. 2 E, in this step, will form second side wall 6 in the outside of first side wall 4 through series of process flow processs such as deposition, photoetching, corrosion.
Step 106 is carried out the deep/source drain extensions ion implantation technology.
Shown in Fig. 2 F, in this step, will be mask, and, carry out the deep/source drain extensions ion and inject, formation source on substrate 1/leakage (S/D) district 7 with second side wall, 6 defined windows with grid 301, first side wall 4 and second side wall 6.
In above-mentioned deep/source drain extensions ion implantation technology; Generally be divided into the completion of three steps; In order to distinguish this three secondary ions injection process; Can the source/drain region ion first time in this step be injected and be called IMP1, source/drain region ion injects and is called IMP2 for the second time, and source/drain region ion injects and is called IMP3 for the third time.Wherein, in IMP1 and IMP3, employed ion is boron (B, Boron) ion; And in IMP2, employed ion is boron fluoride (BF
2) ion.
After carrying out above-mentioned deep/source drain extensions ion implantation technology; Also can (for example carry out follow-up rapid thermal anneal process; Laser annealing technique etc.), thereby repair lattice impaired when carrying out the deep/source drain extensions ion implantation technology, and make the ion distribution of being injected more even.
Step 107, remove second side wall after, on formed grid, source and drain region the deposition heavily stressed nitride layer.
Shown in Fig. 2 G, in this step, will remove second side wall 6, then the heavily stressed nitride layer 8 of deposition on formed grid, source and drain region.Wherein, can utilize multiple deposition process of the prior art to form heavily stressed nitride layer 8.
Step 108 is carried out ohmic contact (CT) technology.
In this step, will carry out ohmic contact craft, to form ohmic contact layer (not shown among Fig. 2 G).Specifically; When need carry out ohmic contact craft; Can use PVD method deposit thickness earlier is the nickel metal layer of 100～150 dusts
; Carry out process annealing (annealing temperature is generally about 300 ℃) and high annealing (annealing temperature is generally about 450 ℃) then, the SiNi ohmic contact layer that has the low-resistivity phase with formation.Concrete technical process repeats no more at this.
Step 109 is carried out top-level metallic wiring (MT) technology.
In this step, will carry out the top-level metallic Wiring technique, to form top-level metallic wiring (not shown among Fig. 2 G).Concrete technical process repeats no more at this.
Through above-mentioned step 101～109, finally can form required PMOS core devices.
But ion implantation process in the manufacturing process of above-mentioned PMOS and employed RTA technology can reduce the performance of MOSFET usually.For example, when carrying out above-mentioned deep/source drain extensions ion implantation technology, owing to need carry out three secondary ion injection process continuously, the dosage that therefore makes source leakage ion inject easily is too high; Simultaneously; Because P type element (for example; The boron ion) fair all smaller, so the ions diffusion speed ratio is very fast, thereby make the density of the ion mixed when the follow-up RTA of carrying out technology, occur overdoping (over-run) phenomenon easily; Thereby make and to compare with P type MOSFET (PMOSFET) accordingly with corresponding N type MOSFET (NMOSFET); The saturation current (Idsat) through the formed PMOS core devices of above-mentioned technology and the value of cut-off leakage current (Ioff) will substantially exceed the domain of walker of standard, cause the process window (Process Window) of this PMOS core devices too little, thereby greatly reduce the performance of this PMOS core devices.
Therefore, the process window that how to increase the PMOS core devices is the problem that must pay close attention in the semiconductor fabrication process.
Summary of the invention
The invention provides a kind of method of process window of the PMOS of increase core devices, thereby increase the process window of PMOS core devices, improve the yield of product, save the technology cost.
For achieving the above object, the technical scheme among the present invention is achieved in that
A kind of method that increases the process window of PMOS core devices, this method comprises:
On substrate, form successively after gate oxide and the polysilicon layer, formed polysilicon layer is carried out the ion injection first time;
Said gate oxide and polysilicon layer are carried out etching, form grid, and form first side wall in the both sides of said grid;
Carry out the shallow ion injection technology, forming shallow doped drain, and form second side wall in the outside of above-mentioned first side wall;
Carry out the deep/source drain extensions ion implantation technology; Comprise that in said deep/source drain extensions ion implantation technology source/drain region ion injects and source/drain region ion injection for the second time for the first time;
The heavily stressed nitride layer of deposition on formed grid, source and drain region, and carry out ohmic contact craft and top-level metallic Wiring technique.
When formed polysilicon layer and gate oxide being carried out the first time, ion injected, employed ion is the boron ion;
Wherein, said boron energy of ions interval is: 4～8Kev, the dosage interval of said boron ion is: 10
13～10
14/ cm
2
The source first time in said deep/source drain extensions ion implantation technology/drain region ion injects, and employed ion is a boron fluoride BF2 ion;
Wherein, said boron fluoride energy of ions is: 4～10Kev, the dosage of said boron fluoride ion is: 5 * 10
14～5 * 10
15/ cm2.
The source second time in said deep/source drain extensions ion implantation technology/drain region ion injects, and employed ion is the boron ion;
Wherein, said boron energy of ions is: 1～3Kev, the dosage of said boron ion is: 10
14～2 * 10
15/ cm
2
This method also further comprises: after carrying out described deep/source drain extensions ion implantation technology, carry out rapid thermal anneal process.
This method also further comprises: after carrying out described shallow ion injection technology, carry out rapid thermal anneal process.
Said rapid thermal anneal process is a laser annealing technique.
To sum up can know, a kind of method of process window of the PMOS of increase core devices is provided among the present invention.In the method; Because said gate oxide and polysilicon layer are being carried out etching with before forming grid; Carry out the primary ions injection process earlier, and in follow-up deep/source drain extensions ion implantation technology, only carry out the twice ion injection process, thereby can increase the process window of PMOS core devices effectively; Improve the yield of product, save the technology cost.
Description of drawings
Fig. 1 is the flow chart that forms the method for PMOS in the prior art.
Fig. 2 A～2G is the sketch map that forms the method for PMOS in the prior art.
Fig. 3 is the flow chart of method of the process window of increase of the present invention PMOS core devices.
Fig. 4 A～4G is the sketch map of method of the process window of increase of the present invention PMOS core devices.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the present invention is elaborated.
The invention provides a kind of method of process window of the PMOS of increase core devices; This method deposits successively on substrate and forms after gate oxide and the polysilicon, and in that said gate oxide and polysilicon layer are carried out etching with before forming grid, carries out primary ions earlier and inject (IMP) process; And in follow-up deep/source drain extensions ion implantation technology, the dosage of this part ion that has injected is deducted; Only carry out the twice ion injection process, thereby reduce the dosage of the injection ion in the deep/source drain extensions ion implantation technology, reduce the overdoping phenomenon effectively; Improve the performance of PMOS core devices, improve the yield of product.
Fig. 3 is the flow chart of method of the process window of increase of the present invention PMOS core devices.Fig. 4 A～4G is the sketch map of method of the process window of increase of the present invention PMOS core devices.As shown in Figure 3, the method for the process window of increase PMOS core devices of the present invention may further comprise the steps:
Shown in Fig. 4 A, in this step, will at first on substrate 1, deposit and form gate oxide 2, and then on gate oxide 2, deposit a polysilicon layer 3.Wherein, gate oxide 2 generally is made up of silicon dioxide and a spot of nitrogen element.
In addition, can use deposition process commonly used in this area to carry out the deposition of above-mentioned gate oxide and polysilicon layer, the concrete deposition gate oxide and the method for polysilicon layer repeat no more at this.
Shown in Fig. 4 A, in this step, will carry out the preceding doping process of polysilicon, promptly above-mentioned formed polysilicon layer 3 is carried out the ion implantation process first time, thereby described polysilicon layer 3 is mixed.After (poly pre-doping) technology of before carrying out above-mentioned polysilicon, mixing; Can be under the prerequisite that does not reduce the polysilicon resistance rate; Reduce the dosage of the ion that is injected in the follow-up deep/source drain extensions ion implantation technology, thereby reduce the situation of (punchthrough) phenomenon and leakage current to occur puncturing owing to channel width that overdoping causes narrows down.
In order to be different from other ion implantation process in the subsequent step, can the ion implantation process first time in this step be called IMP1.
Wherein, carrying out the first time during ion implantation process, employed ion is boron (B) ion; This boron energy of ions interval is: 4～8Kev, the dosage interval is: 10
13～10
14Individual/square centimeter (is abbreviated as "/cm with unit " individual/square centimeter " usually
2", Hereinafter the same).Preferable, in practical application, can select: the boron energy of ions of being injected is respectively: 4Kev, 5Kev, 6Kev, 7Kev or 8Kev, the dosage of the boron ion that is injected is respectively: 2 * 10
13/ cm
2, 4 * 10
13/ cm
2, 6 * 10
13/ cm
2, 8 * 10
13/ cm
2Or 9 * 10
13/ cm
2
In this step, can use ion injection method commonly used in this area to carry out the preceding doping process of above-mentioned polysilicon, therefore, the concrete implementation of doping process repeats no more at this before the above-mentioned polysilicon.
Step 303 is carried out etching to said gate oxide and polysilicon layer, forms grid.
Shown in Fig. 4 B, in this step, will make public, technology such as etching, thereby form grid 301 polysilicon layer after the above-mentioned doping 3 and gate oxide 2.
In this step, can use technologies such as exposure commonly used in this area, etching to form required grid 301, therefore, the concrete implementation that forms grid repeats no more at this.
Step 304 forms first side wall in the both sides of said grid.
Shown in Fig. 4 C, in this step, will form first side wall 4 in the both sides of grid 301.The purpose of this first side wall 4 that forms is to reserve certain distance into the shallow ion injection region horizontal proliferation in follow-up rapid thermal annealing (RTA) technology; Thereby the raceway groove of guaranteeing grid 301 belows has certain width; With the short-channel effect of avoiding follow-up shallow ion injection technology to be brought, cause channel width to narrow down and the situation of punch-through and leakage current occurs.
In this step; Said first side wall 4 is generally formed by silica/silicon nitride medium film combinations; And that the thickness of said first side wall 4 is generally
is preferred, and the thickness of said first side wall 4 is
In addition, the method for concrete formation first side wall 4 can be used the method for formation side wall commonly used in this area, repeats no more at this.
Step 305 is carried out the shallow ion injection technology, to form shallow doped drain (LDD) district.
Shown in Fig. 4 D, in this step, will be mask with first side wall 4 and grid 301, carry out the shallow ion injection technology, thereby on substrate 1, form shallow doped drain 5.
After carrying out above-mentioned shallow ion injection technology, also can carry out follow-up rapid thermal anneal process (for example, laser annealing technique etc.), make the horizontal proliferation of shallow ion injection region, help the formation of shallow doped drain 5; In addition, above-mentioned rapid thermal anneal process can also be repaired lattice impaired when carrying out the shallow ion injection technology, and can make the ion distribution of being injected more even.
In addition, in this step, can use ion injection method commonly used in this area to carry out above-mentioned shallow ion injection technology, therefore, the concrete implementation of above-mentioned shallow ion injection technology repeats no more at this.
Step 306 forms second side wall 6 in the outside of above-mentioned first side wall.
Shown in Fig. 4 E, in this step, will form second side wall 6 in the outside of first side wall 4 through series of process flow processs such as deposition, photoetching, corrosion.
Wherein, said second side wall 6 is mainly formed by silica/silicon nitride medium film combinations; And that the thickness of said second side wall 6 is generally
is preferred, and the thickness of said second side wall 6 is
In addition, in this step, can use side wall formation method commonly used in this area to form the second above-mentioned side wall 6, therefore, concrete implementation repeats no more at this.
Step 307 is carried out the deep/source drain extensions ion implantation technology.
Shown in Fig. 4 F, in this step, will be mask, and, carry out the deep/source drain extensions ion and inject, formation source on substrate 1/leakage (S/D) district 7 with second side wall, 6 defined windows with grid 301, first side wall 4 and second side wall 6.
In the present invention, above-mentioned deep/source drain extensions ion implantation technology is divided into the completion of two steps, promptly after carrying out the source first time/drain region ion implantation process, carries out the source second time/drain region ion implantation process again.For the ease of difference, can the source/drain region ion implantation process first time in this step be called IMP2, source/drain region ion implantation process is called IMP3 for the second time.
Wherein, in IMP2, employed ion is boron fluoride (BF
2) ion; This boron fluoride energy of ions is: 4～10Kev, dosage is: 5 * 10
14～5 * 10
15/ cm
2Preferable, in practical application, can select: the boron fluoride energy of ions of being injected is respectively: 3Kev, 5Kev, 7Kev or 9Kev, the dosage of the boron fluoride ion that is injected is respectively: 6 * 10
14/ cm
2, 8 * 10
14/ cm
2, 1 * 10
15/ cm
2, 2 * 10
15/ cm
2Or 4 * 10
15/ cm
2
In IMP3, employed ion is boron (B) ion; This boron energy of ions is: 1～3Kev, dosage is: 10
14～2 * 10
15Individual/cm
2Preferable, in practical application, can select: the boron energy of ions of being injected is respectively: 1Kev, 2Kev or 3Kev, the dosage of the boron ion that is injected is respectively: 2 * 10
14/ cm
2, 4 * 10
14/ cm
2, 6 * 10
14/ cm
2, 8 * 10
14/ cm
2Or 10
15/ cm
2
After carrying out above-mentioned deep/source drain extensions ion implantation technology; Also can (for example carry out follow-up rapid thermal anneal process; Laser annealing technique etc.), thereby repair lattice impaired when carrying out the deep/source drain extensions ion implantation technology, and make the ion distribution of being injected more even.
In addition, in this step, can use ion injection method commonly used in this area to carry out above-mentioned deep/source drain extensions ion implantation technology, therefore, the concrete implementation of above-mentioned deep/source drain extensions ion implantation technology repeats no more at this.
Shown in Fig. 4 G, in this step, will on formed grid, source and drain region, deposit heavily stressed nitride layer 8.Wherein, can utilize multiple deposition process of the prior art to form heavily stressed nitride layer 8.
Step 309 is carried out ohmic contact (CT) technology.
In this step, will carry out ohmic contact craft, to form ohmic contact layer (not shown among Fig. 4 G).Specifically; When need carry out ohmic contact craft; Can use the nickel metal layer of PVD method deposit thickness earlier for
; Carry out process annealing (annealing temperature is generally about 300 ℃) and high annealing (annealing temperature is generally about 450 ℃) then, the SiNi ohmic contact layer that has the low-resistivity phase with formation.Concrete technical process repeats no more at this.
Step 310 is carried out top-level metallic wiring (MT) technology.
In this step, will carry out the top-level metallic Wiring technique, to form top-level metallic wiring (not shown among Fig. 4 G).Concrete technical process repeats no more at this.
Through above-mentioned step 301～310, finally can form required PMOS core devices.
Can know by the above-described method that increases the process window of PMOS core devices; In technical scheme provided by the present invention, form after gate oxide and the polysilicon owing on substrate, deposit successively, and said gate oxide and polysilicon layer are being carried out etching with before forming grid; Carry out primary ions earlier and inject (IMP) process; And in follow-up deep/source drain extensions ion implantation technology, the dosage of this part ion that has injected is deducted, only carry out the twice ion injection process, thereby under the prerequisite that does not reduce the polysilicon resistance rate; Reduce the dosage of the ion that is injected in the follow-up deep/source drain extensions ion implantation technology; Narrow down and the situation of (punchthrough) phenomenon and leakage current occurs puncturing thereby can reduce the channel width that causes owing to overdoping effectively, improve the yield of product, save the technology cost.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1. a method that increases the process window of PMOS core devices is characterized in that, this method comprises:
On substrate, form successively after gate oxide and the polysilicon layer, formed polysilicon layer is carried out the ion injection first time;
Said gate oxide and polysilicon layer are carried out etching, form grid, and form first side wall in the both sides of said grid;
Carry out the shallow ion injection technology, forming shallow doped drain, and form second side wall in the outside of above-mentioned first side wall;
Carry out the deep/source drain extensions ion implantation technology; Comprise that in said deep/source drain extensions ion implantation technology source/drain region ion injects and source/drain region ion injection for the second time for the first time;
The heavily stressed nitride layer of deposition on formed grid, source and drain region, and carry out ohmic contact craft and top-level metallic Wiring technique.
2. method according to claim 1 is characterized in that:
When formed polysilicon layer and gate oxide being carried out the first time, ion injected, employed ion is the boron ion;
Wherein, said boron energy of ions interval is: 4～8Kev, the dosage interval of said boron ion is: 10
13～10
14/ cm
2
3. method according to claim 1 is characterized in that:
The source first time in said deep/source drain extensions ion implantation technology/drain region ion injects, and employed ion is boron fluoride BF
2Ion;
Wherein, said boron fluoride energy of ions is: 4～10Kev, the dosage of said boron fluoride ion is: 5 * 10
14～5 * 10
15/ cm
2
4. method according to claim 1 is characterized in that:
The source second time in said deep/source drain extensions ion implantation technology/drain region ion injects, and employed ion is the boron ion;
Wherein, said boron energy of ions is: 1～3Kev, the dosage of said boron ion is: 10
14～2 * 10
15/ cm
2
5. method according to claim 1 is characterized in that, this method also further comprises:
After carrying out described deep/source drain extensions ion implantation technology, carry out rapid thermal anneal process.
6. method according to claim 1 is characterized in that, this method also further comprises:
After carrying out described shallow ion injection technology, carry out rapid thermal anneal process.
7. according to claim 5 or 6 described methods, it is characterized in that:
Said rapid thermal anneal process is a laser annealing technique.
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| CN104123962A (en) * | 2014-07-21 | 2014-10-29 | 中国人民解放军国防科学技术大学 | Single-grid nonvolatile storage cell with low polycrystal doping concentration |
| CN105590842B (en) * | 2014-11-17 | 2019-11-01 | 上海华力微电子有限公司 | Reduce the structures and methods of source electrode and drain electrode resistance |
| CN112735950A (en) * | 2020-12-28 | 2021-04-30 | 华虹半导体(无锡)有限公司 | NOR Flash process method |
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| CN101383286A (en) * | 2007-09-07 | 2009-03-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for PMOS tube with improved negative temperature instability |
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| CN101383286A (en) * | 2007-09-07 | 2009-03-11 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for PMOS tube with improved negative temperature instability |
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