CN102034865B - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

The present application discloses a semiconductor device and a method of manufacturing the same, the semiconductor device being formed on an SOI substrate including a buried insulating layer and a semiconductor layer formed on the buried insulating layer, a fin of a semiconductor material being formed in the semiconductor layer, the fin including two opposite side surfaces perpendicular to a surface of the SOI substrate, the semiconductor device including: the source region and the drain region are arranged at two ends of the fin; a channel region disposed in a middle portion of the fin; and a stack of a gate dielectric and a gate conductor disposed on one side of a fin, the gate conductor being isolated from the channel region by the gate dielectric, wherein the gate conductor extends away from the one side of the fin in a direction parallel to a surface of the SOI substrate. The semiconductor device reduces short channel effects and reduces parasitic capacitance and parasitic resistance, thereby facilitating transistor size reduction and transistor performance improvement.

Description

Semiconductor device and manufacturing method thereof

technical field

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to an improved FinFET formed on a semiconductor-on-insulator (SOI) substrate. the

Background technique

An important development direction of integrated circuit technology is to scale down the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) to improve integration and reduce manufacturing costs. However, it is well known that short-channel effects occur as the size of MOSFETs decreases. When the size of the MOSFET is scaled down, the effective length of the gate is reduced, so that the proportion of the depletion layer charge actually controlled by the gate voltage is reduced, so that the threshold voltage decreases with the decrease of the channel length. the

A conventional planar MOSFET includes a sandwich structure consisting of a gate electrode, a gate insulating layer, and a semiconductor layer. The semiconductor layer includes a channel region below the gate electrode and source/drain regions on both sides of the channel region. A silicide layer can be formed on the source/drain region, and the silicide layer is connected to the source/drain electrodes through holes, thereby reducing the parasitic resistance and parasitic capacitance of the device. Planar MOSFETs suffer from short-channel effects that cause the device's threshold voltage to fluctuate with channel length. the

In order to suppress the short channel effect, the FinFET formed on SOI is disclosed in US Pat. / drain area. The gate electrode surrounds the channel region on both sides of the channel region (ie, a double gate structure), so that an inversion layer is formed on each side of the channel. The thickness of the channel region in the fin is very thin, so that the entire channel region can be controlled by the gate, so it can play a role in suppressing the short channel effect. the

However, in a conventional FinFET, since there is a gate extending parallel to the source/drain region between the source/drain regions, and the distance between the source/drain region and the gate is very close, in the source/drain region There is a capacitive coupling between the gate and the gate, which leads to the problem of large parasitic resistance and parasitic capacitance. the

The capacitive coupling between the source/drain region and the gate limits the degree of freedom in device design. If it is desired to reduce the parasitic resistance, the thickness of the source/drain region needs to be increased. However, an increase in the thickness of the source/drain region will result in an increase in the coupling area between the source/drain region and the gate, resulting in an increase in parasitic capacitance, and vice versa. Therefore, those skilled in the art cannot utilize conventional FinFET structures to achieve simultaneous reduction of parasitic resistance and parasitic capacitance. the

As a result, in a conventional FinFET, the delay due to the large value of the time constant RC increases, which in turn reduces the switching speed of the device. the

Contents of the invention

An object of the present invention is to provide a semiconductor device capable of suppressing short channel effects and reducing parasitic resistance and parasitic capacitance. the

Another object of the present invention is to further provide a semiconductor device that utilizes stress to improve device performance. the

According to an aspect of the present invention, there is provided a semiconductor device formed on an SOI substrate, the SOI substrate includes a buried insulating layer and a semiconductor layer formed on the buried insulating layer, and a semiconductor material is formed in the semiconductor layer The fin includes two opposite sides perpendicular to the surface of the SOI substrate, and the semiconductor device includes: a source region and a drain region arranged at both ends of the fin; a channel region arranged at the middle part of the fin and a stack of a gate dielectric and a gate conductor disposed on one side of the fin, the gate conductor being isolated from the channel region by the gate dielectric, wherein the gate conductor is along extending away from the one side of the fin in a direction parallel to the surface of the SOI substrate. the

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the following steps: a) forming fins of semiconductor material in a semiconductor material layer of an SOI substrate by a self-alignment method, the fins including vertical on two opposite sides of the SOI substrate surface; b) forming a stack of gate dielectric and gate conductor on one side of the fin, the gate conductor facing away from the SOI substrate along a direction parallel to the SOI substrate surface extending the one side of the fin; c) implanting dopants into the semiconductor material at both ends of the fin to form a source region and a drain region; and d) forming a channel region in a middle portion of the fin. the

It should be noted that the semiconductor device of the present invention includes fins of semiconductor material, but its structure is different from that of conventional FinFETs in that its gates are arranged on only one side of the fins and extend away from the fins, while conventional FinFETs are arranged in double fins. gate structure and surrounds the channel region in the middle portion of the fin. Also, the source/drain regions are arranged at both ends of the fins, extending in a direction opposite to that of the gate. the

The semiconductor device of the present invention does not include a gate extending parallel to the source/drain regions between the source/drain regions, so there is no capacitive coupling between the source/drain regions and the gate, thereby reducing parasitic capacitance. At the same time, the semiconductor device of the present invention allows reduction of parasitic resistance by using thicker source/drain regions. the

An extension region can also be formed on the portion of the fin adjacent to the channel region to reduce the conduction path length of the carriers, thereby further reducing the parasitic effect related to the parasitic capacitance and the parasitic resistance. the

In addition, a stress layer can also be formed in the source/drain region to increase the stress of the channel region, thereby further increasing the switching speed of the device. the

In order to effectively control the short channel effect, the self-aligned channel region is very thin: about 5-40nm. And, in a preferred process, the thickness of the channel region is further reduced by using a super steep retreat well (SSRW) process. Even if the gate is only set on one side of the channel, the channel region can still be fully controlled by the gate, thereby reducing the influence of the short channel effect. the

Description of drawings

1A and 1B are three-dimensional perspective views and plan views schematically illustrating the structure of a semiconductor device according to the present invention, and lines A-A', 1-1' and 2-2' indicate intercept positions of the following cross-sectional views. the

2-9 are cross-sectional views along the line A-A' of the semiconductor structure formed in various steps of the method for manufacturing a semiconductor device according to the present invention, showing various steps of forming fin regions and gate regions. the

10-16 are cross-sectional views along line 1-1' of a semiconductor structure formed in subsequent steps of the method for manufacturing a semiconductor device according to the present invention, showing various steps of forming source/drain regions. the

17-21 are cross-sectional views along line A-A' of a semiconductor structure formed in subsequent steps of the method for manufacturing a semiconductor device according to the present invention, showing various steps of forming a channel region. the

22A, 22B, 23A, and 23B are cross-sectional views of the semiconductor structure formed in the subsequent steps of the method for manufacturing a semiconductor device according to the present invention along the A-A' line and the 2-2' line, wherein the source/drain region And the various steps of forming a silicide layer on the gate. the

Detailed ways

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. In the various figures, identical elements are indicated with similar reference numerals. For the sake of clarity, various parts in the drawings have not been drawn to scale. the

It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean being directly on another layer or another region, or Other layers or regions are also included between it and another layer or another region. And, if the device is turned over, the layer, one region, will be "below" or "beneath" the other layer, another region. the

If it is to describe the situation of being directly on another layer or another area, the expression "directly on" or "on and adjacent to" will be used herein. the

In the following, many specific details of the present invention are described, such as device structures, materials, dimensions, processing techniques and techniques, for a clearer understanding of the present invention. However, the invention may be practiced without these specific details, as will be understood by those skilled in the art. the

Unless otherwise specified below, various parts in the semiconductor device may be composed of materials known to those skilled in the art. SOI substrates as initial structures include, for example, silicon-on-insulator, silicon-germanium-on-insulator, and semiconductor material stacks on insulator. The semiconductor material stack includes, for example, III-V semiconductors, such as GaAs, InP, GaN, SiC. The gate conductor may be a metal layer, a doped polysilicon layer, or a stacked gate conductor comprising a metal layer and a doped polysilicon layer. The material of the metal layer is TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, HfRu , RuOx and the combination of various metal materials. The gate dielectric can be made of _SiO2 or a material with a dielectric constant greater than _SiO2 , such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, where oxides include _SiO2 , for example , HfO ₂ , ZrO ₂ , Al ₂ O ₃ , TiO ₂ , La ₂ O ₃ , nitrides such as Si ₃ N ₄ , silicates such as HfSiOx, aluminates such as LaAlO ₃ , titanates such as SrTiO _3. Oxynitrides include SiON, for example. Also, the gate dielectric may not only be formed of materials known to those skilled in the art, but also materials for gate dielectrics developed in the future may be used.

1A and 1B are three-dimensional perspective and plan views schematically illustrating the structure of a semiconductor device according to the present invention. Lines A-A', 1-1', 2-2' in Figure 1B represent the interception positions of the cross-sectional view, where line A-A' is perpendicular to the channel length direction and passes through the gate, and line 1-1' is along the channel The line 2-2' goes along the length direction of the channel and passes through the channel region, and passes through the insulating material filling between the source/drain regions. the

As shown in Figures 1A and 1B, a semiconductor device 100 is formed in the semiconductor layer of the SOI substrate, including a channel region 11 located in the middle part of the fin of the semiconductor material, a source region 12 and a drain region 13 located at both ends thereof, A stack of gate dielectric 14 and gate 15 is provided adjacent to one side of the fin, and a fill of insulating material 18 for filling the opening in the other side of the fin. the

The thickness of the channel region located in the middle part of the fin is very thin, for example in the range of about 5-40 nm. This thickness is similar to that of the channel region in a conventional FinFET and can be formed using a similar self-aligned process. the

The inventors found that although the double gate structure is not used, if the thickness of the channel region is within the above range, the gate located on one side of the fin can still act on the entire channel region, thereby suppressing the short channel effect. the

Preferably, the semiconductor device further includes stressors 16 and 17 for applying stress to the source region 12 and the drain region 13 . The stress layers 16 and 17 are adjacent to the source region 12 and the drain region 13 respectively, and the contact area is as large as possible, so that the contact resistance between the stress layers 16 and 17 and the source region 12 and the drain region 13 is minimum. As shown in Figures 1A and 1B, a step portion has been formed in the source region 12 and the drain region 13, and the stress layers 16 and 17 are located in the step portion, so that one side and the bottom of the stress layer 16 and 17 are in contact with the source region 12 and the drain region 13 contacts. the

The material of the stress layers 16 and 17 should be able to generate stress in the channel region that is beneficial to improve the performance of the transistor. When the formed device is an n-type MOSFET, the stress layers 16 and 17 should apply tensile stress along the source/drain direction to the channel region, so as to increase the mobility of electrons as carriers. On the contrary, when the transistor is a p-type MOSFET, the stress layers 16 and 17 should apply compressive stress in the source/drain direction to the channel region to increase the mobility of holes as carriers. the

It should be noted that in the example of the semiconductor device structure shown in FIGS. 1A and 1B , the stress layers 16 and 17 are respectively located at the source region 12 and the source contact (not shown), and the drain region 13 and the drain contact (not shown). Therefore, the stress layers 16, 17 should also be conductive. For p-type MOSFETs, B-doped SiGe materials can be used, while for n-type MOSFETs, Si:C materials doped with As or P can be used. the

Additional layers and portions above the source region 12, the drain region 13 and the gate 15 are not shown in FIGS. Pole contacts, interlayer insulating layers, via holes formed in interlayer insulating layers, and passivation layers, etc. the

In describing the steps of manufacturing the semiconductor device below, some additional layers and parts closely related to the semiconductor device will be described, but those additional layers and parts known in the art (such as source contacts, drain contacts and gate contacts) will be omitted. pole contact) for a detailed description. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure. the

Referring to FIG. 2 , the method of manufacturing a semiconductor device of the present invention starts with an SOI wafer, which is a stack including a bottom substrate 21 , a buried insulating layer (BOX) 22 and a top semiconductor layer 23 . the

By known deposition processes, such as PVD, CVD, atomic layer deposition, sputtering, etc., the SiGe layer 24 with a Ge content of about 5-15% and a thickness of about 3-20 nm and a thickness of about Si layer 25 of 30-100 nm. The Si layer 25 can be formed in a separate deposition step, or can be formed in situ after the epitaxial growth of the SiGe layer 24 by using a Si target or precursor. the

Then, an HfO ₂ layer 26 with a thickness of about 3-10 nm is formed on the Si layer 25 by atomic layer deposition or magnetron sputtering.

Referring to FIG. 3 , a stripe-shaped photoresist pattern 27 is formed on the HfO ₂ layer 26 through a conventional photolithography process including exposure and development steps.

Referring to FIG. 4, using the photoresist pattern 27 as a mask, a part of the _HfO2 layer 26, the Si layer 25, and the SiGe layer 24 are removed by dry etching, such as ion milling etching, plasma etching, reactive ion etching, and laser ablation. , forming a patterned stacked structure of the HfO ₂ layer 26 , the Si layer 25 , and the SiGe layer 24 .

If reactive ion etching is used, it can be divided into two steps. In a first step, the gas composition of the etching atmosphere is chosen such that the HfO ₂ layer 26 and part of the Si layer 25 are removed, stopping on top of the SiGe layer 24 . In the second step, by changing the gas composition of the etching atmosphere, a part of the SiGe layer 24 is removed and stops on the top semiconductor layer 23 of the SOI substrate. Those skilled in the art know that in reactive ion etching, the selective removal of one of the SiGe layer and the Si layer can be controlled by changing the gas composition of the etching atmosphere.

Then, the photoresist pattern 27 is removed by dissolving in a solvent or ashing. the

A conformal oxide layer 28 with a thickness of approximately 2-5 nm is formed on the patterned stack and exposed portions of the top semiconductor layer 23 of the SOI substrate. the

The thin oxide layer can be formed by known deposition processes such as PVD, CVD, atomic layer deposition, sputtering, and the like. the

Then, a conformal nitride layer is first formed, and then a part of the layer is removed, thereby forming a nitride spacer with a thickness of about 5-50 nm on both sides of the stack structure including the _HfO layer 26, the Si layer 25, and the SiGe layer 24. Wall 29.

Referring to FIG. 5, a photoresist layer pattern 30 is formed on the structure shown in FIG. 4 by a conventional photolithography process including exposure and development steps, so as to shield the spacer sidewall on the left side and the left side of the patterned stack structure. part. the

Referring to FIG. 6 , using the resist pattern 30 as a mask, the spacer sidewall on the right side is removed by isotropic etching, for example, conventional wet etching using an etchant solution. the

Alternatively, the right septal sidewall can be removed in three steps. In the first step, using the resist pattern 30 as a mask, Ge is implanted in the spacer sidewall on the right side by oblique angle ion implantation to cause damage. In the second step, the photoresist pattern 30 is removed by dissolving in a solvent or ashing. In the third step, the spacer sidewall on the right side is selectively removed with respect to the spacer sidewall on the left side by wet etching or dry etching. the

After removal of the spacer sidewall on the right, the gas composition of the etching atmosphere is selected, for example by reactive ion etching to selectively remove the exposed portions of the oxide layer 28 on the surface of the semiconductor structure. Then, using the remaining part of the oxide layer 28, the sidewall spacer sidewall 29, and the stacked structure comprising the HfO2 layer 26, the Si layer 25, and the SiGe layer 24 as a hard mask, the gas composition of the etching atmosphere is changed, for example, by reacting Ion etching selectively removes exposed portions of the top semiconductor layer of the SOI substrate, forming fins 23' of semiconductor material in a self-aligned manner. the

7, for example, by CVD or ALD, on the surface of the semiconductor structure shown in _FIG . A 3-10 nm conformal metal (eg TiN, cermet) layer 31 acts as the metal layer of the stacked gate conductor and an overlying polysilicon layer 32 acts as the polysilicon layer in the stacked gate conductor.

Preferably, in-situ doping can be performed on the polysilicon layer 32 to improve conductivity. the

A polysilicon layer 32 covers the entire top of the semiconductor structure. Then, planarization processing (CMP) is performed on the polysilicon layer 32 . The planarization process stops on top of the metal layer of the stacked gate conductor, resulting in a flat surface of the semiconductor structure. the

Referring to FIG. 8 , a part of the polysilicon layer 32 is selectively removed relative to the metal layer 31 by wet etching or dry etching, and the polysilicon layer 32 is etched back. A capping oxide layer 33 is then formed over the entire surface of the semiconductor structure, for example by CVD. the

The oxide layer 33 is planarized, which stops on top of the metal layer of the stacked gate conductor, resulting in a flat surface of the semiconductor structure. As a result, the oxide layer 33 fills the portion of the polysilicon layer 32 that was removed by the etch back. the

A nitride layer 34 is then formed on the surface of the semiconductor structure, for example by CVD. the

Referring to FIG. 9 , a stripe-shaped photoresist pattern 35 is formed to define the gate area of the device through a conventional photolithography process including exposure and development steps, and the stacked gate conductor includes a metal layer 31 and a polysilicon layer 32 . the

Then, using the photoresist pattern 35 as a mask, through dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, sequentially remove the nitride layer 34, oxide layer 33, polysilicon layer 32, The metal layer 31 , a portion of the thin oxide layer 26' on either side of the fin 23', the etch stops on top of the buried insulating layer (BOX) 22 of the SOI wafer. the

Corresponding to the cross-sectional view of the semiconductor structure along line A-A' shown in FIG. 9 , a cross-sectional view of the semiconductor structure along line 1-1' is shown in FIG. 10 . An etching step using the photoresist pattern 35 as a mask results in a stack of nitride layer 34, oxide layer 33, polysilicon layer 32, metal layer 31, oxide thin layer 26' over the Si layer 25. the

By an additional mask forming step and etching step before or after the above etching step, part of the fin 23', SiGe layer 24 and Si layer 25 may be removed to define the length of the fin. The dimensions of the fins 23 ′ thus defined in the horizontal direction are shown in FIG. 10 . the

11, still using the photoresist pattern 35 as a mask, by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, sequentially remove a part of Si layer 25 and SiGe layer 24, the Etching stops at the top of fin 23'. As a result, a multilayer stack 101 comprising nitride layer 34, oxide layer 33, polysilicon layer 32, metal layer 31, oxide thin layer 26', Si layer 25, SiGe layer 24 is formed over fin 23'. the

Referring to FIG. 12, the photoresist pattern 35 is removed by dissolving in a solvent or ashing. the

Then, for example by CVD, a conformal oxide layer 35 with a thickness of approximately 2-5 nm and a conformal nitride layer 37 with a thickness of approximately 10-20 nm are sequentially formed on the entire surface of the semiconductor structure. the

A portion of the nitride layer 37 is removed by dry etching, such as ion milling etch, plasma etch, reactive ion etching, laser ablation, which etch stops at the surface of the oxide layer 36, thereby creating a gap between the fins 23' and the multilayer stack. Nitride spacer sidewalls 37 are respectively formed on both sides of 101 . the

Referring to FIG. 13, the oxide layer 36 is removed by dry etching, such as ion milling etching, plasma etching, reactive ion etching, or laser ablation, using the multilayer stack 101 and the nitride spacer sidewalls 37 on both sides as a hard mask. The exposed surface of the fin 23 ′ and a part of the semiconductor material, thereby forming openings 38 at both ends of the fin 23 along the length direction (ie, the horizontal direction in the figure). A thin layer of semiconductor material with a thickness of about 10 nm remains at the bottom of the opening 38 . the

This etching step is self-aligned, wherein the dimensions of the opening 38 are substantially determined by the oxide layer 36 and the nitride spacer sidewalls 37 . the

FIG. 14 illustrates an optional step in some embodiments of halo implantation from opening 38 to the middle portion of fin 23' using angled ion implantation. For n-type MOSFETs, B or BF2 is used as a dopant. For p-type MOSFETs, As or P is used as a dopant. the

FIG. 15 illustrates an optional step in some embodiments of performing an extension implantation into the middle portion of the fin 23' using angled ion implantation. For n-type MOSFETs, As or P is used as a dopant. For p-type MOSFETs, B or BF2 is used as a dopant. the

Compared with the halo implant, the extension implant uses a smaller tilt angle and higher energy, so that in the extension implant, most of the implanted ions pass through the thin layer of semiconductor material at the bottom of the opening 38, so that the thin layer of semiconductor material is free of amorphous change. the

Since the opening 38 provides a window for ion implantation, and the nitride layer 34, oxide layer 36, and nitride spacer sidewalls 37 on the surface of the semiconductor structure provide a hard mask, the above-mentioned extension implantation, halo implantation, and source /Drain implants can be performed in-situ, reducing the number of masks and simplifying the process. the

Referring to FIG. 16 , the formed semiconductor structure is annealed, such as spike anneal. The annealing step is used to activate the dopants implanted by the previous implantation step and to remove the damage caused by the implantation. the

After the annealing treatment, the dopant distribution in the semiconductor fin 23' is shown in the figure, and the source region 12 and the drain region 13 are respectively formed at the bottom of the opening 38, adjacent to the source region 12 and the drain region 13 The source extension region 12' and the drain extension region 13' are respectively formed at the positions of the fins 23', and the source halos are respectively formed at the positions adjacent to the source extension region 12' and the drain extension region 13' and extending toward the middle part of the fin 23'. Circle area 12" and drain halo area 13". the

Then, the stress layer 39 and the epitaxial silicon layer 40 thereon are epitaxially grown sequentially in the opening 38 by known deposition processes, such as PVD, CVD, atomic layer deposition, sputtering, and the like. Due to the epitaxial growth, the stress layer 39 is only formed on the thin layer of semiconductor material at the bottom of the opening 38 . For the p-type MOSFET, the material of the stress layer 39 is SiGe with a Ge content of about 20-50% and doped with B in situ. After epitaxial growth, compressive stress is generated in the direction of source and drain in the channel region, which can enhance the performance of the p-type MOSFET. performance. For n-type MOSFETs, the material of the stress layer 39 is Si:C with a C content of about 0.5-2% and doped with As or P in situ. After epitaxial growth, tensile stress is generated in the direction of source and drain in the channel region, which can enhance Performance of n-type MOSFETs. the

Then, the formed semiconductor structure is oxidized, and the top of the epitaxial silicon layer 40 is oxidized to form a thin oxide layer 36' with a thickness of about 3-10 nm. An epitaxial silicon layer 40 formed on top of the stressor layer 39 is used to obtain good quality _SiO2 .

Referring to FIG. 17, using the oxide layer 33 formed in the step shown in FIG. 8 as a hard mask, the metal layer 31 is sequentially removed by dry etching, such as ion milling etching, plasma etching, reactive ion etching, and laser ablation. , thin nitride layer 26', Si layer 25, SiGe layer 24, part of the fin 23', the etch stops at the top of the buried insulating layer 22 of the SOI substrate, thereby forming the opening 41 in a self-aligned manner. As a result, the thickness of the fin 23' is reduced to a value approximately equal to the sum of the thicknesses of the oxide layer 28 and the nitride spacer sidewall 29. As described below, the fins are used to form a channel region in which stress is further increased due to material removed by etching, which can further enhance device performance. the

On the right side of the opening 41 remains a stack of materials comprising a thin nitride layer 26', a metal layer 31, a polysilicon layer 32, and a part of an oxide layer 33. When manufacturing an integrated circuit containing multiple MOSFETs of the same structure, the stacked material on the right side of the opening 41 can serve as the gate region of an adjacent MOSFET (not shown), and the filling material in the opening 41 can serve as a shallow gate region. The role of ditch isolation. the

In addition, as shown in FIG. 17, the nitride spacer sidewalls 37 formed in the step shown in FIG. 12 also exist on the sides of the gate stack. the

Referring to FIG. 18, by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, relative to the oxide layer 33, the thin oxide layer 26' and the metal layer 31 remaining inside the opening are selectively removed. (right side wall part in Fig. 18). the

Then, preferably, ions are implanted into the fin 23 ′ of the semiconductor material by using inclined angle ion implantation, and then annealing (for example, laser annealing) is performed to activate the implanted dopant, thereby forming a SSRW42. Opening 41 provides a window for ion implantation. For the formation process of SSRW, please refer to the following documents:

1) G.G.Shahidi, D.A.Antoniadis and H.I.Smith, IEEE TED Vol.36, p.2605, 1989

2) C.Fiegna, H.Iwai, T.Wada, M.Saito, E.Sangiorgi and B.Riccò, IEEE TED Vol.41, p.941, 1994.

3) J.B.Jacobs and D.A.Antoniadis, IEEE TED Vol.42, p.870, 1995. 

4) S.E.Thompson, P.A.Packan and M.T.Bohr, VLSI Tech Symp., p.154, 1996.

Referring to FIGS. 19 and 20 , the partition side wall 37 on the left side is removed in three steps. In the first step, using the oxide layer 33 as a mask, the angled ion implantation is used to implant Ge into the left spacer sidewall to cause damage, as shown in FIG. 19 . In the second step, the photoresist pattern 30 is removed by dissolving in a solvent or ashing. In the third step, the left partition sidewall is selectively removed with respect to the right partition sidewall by wet etching or dry etching, as shown in FIG. 20 . the

Referring to Figure 21, a thin conformal oxide layer 33' having a thickness of about 2-5 nm is formed over the entire surface of the semiconductor structure, for example by CVD. Nitride is then deposited, for example by CVD, to a thickness at least capable of filling opening 41 . The nitride is etched back selectively with respect to the oxide layer 33' such that the nitride layer around the opening is completely removed, leaving only the nitride fill material 43 in the opening. the

Referring to Figures 22A and 22B, by dry etching, such as ion milling etching, plasma etching, reactive ion etching, laser ablation, the oxide is selectively removed relative to the nitride filling material 43,

The etch completely removes the exposed portion of the oxide layer 33' on the surface of the semiconductor structure, leaving only the portion of the oxide layer 33' at the sidewalls and bottom of the filled opening, thereby exposing the polysilicon layer in the gate stack 32, and the upper surface of the epitaxial silicon layer 40 in the source and drain regions. the

This etch also removes a portion of the buried oxide layer 22 of the SOI substrate. the

Referring to FIGS. 23A and 23B , using a conventional silicidation process, a part of the upper surface and the left side surface of the polysilicon layer 32 in the gate stack, and at least a part of the epitaxial silicon layer 40 in the source region and the drain region, are transformed into It is a silicide layer to reduce the contact resistance between the gate, source/drain and corresponding metal contacts. the

For example, first deposit a Ni layer with a thickness of about 5-12nm, then heat-treat at a temperature of 300-500° C. for 1-10 seconds, so that at least a part of the polysilicon layer 32 and the epitaxial silicon layer 40 forms NiSi, and finally use wet etching Remove unreacted Ni. the

After the steps shown in FIGS. 2-23 are completed, an interlayer insulating layer, via holes located in the interlayer insulating layer, and holes located on the upper surface of the interlayer insulating layer are formed on the obtained semiconductor structure according to methods known in the art. Wiring or electrodes to complete the rest of the semiconductor device. the

The above description is only for illustration and description of the present invention, not intended to be exhaustive and limitative of the present invention. Accordingly, the invention is not limited to the described embodiments. Variations or changes that are obvious to those skilled in the art are within the protection scope of the present invention. the

Claims (21)

1. A semiconductor device formed on an SOI substrate, the SOI substrate comprising a buried insulating layer and a semiconductor layer formed on the buried insulating layer, fins of semiconductor material are formed in the semiconductor layer, the fins The sheet includes two opposite sides perpendicular to the surface of the SOI substrate, the semiconductor device includes: A source region (12) and a drain region (13) arranged at both ends of the fin; a channel region (11) disposed in the middle portion of the fin; and a stack of a gate dielectric (14) and a gate conductor disposed on one side of the fin, said gate conductor being isolated from said channel region (11) by said gate dielectric (14), wherein the gate conductor extends away from the one side of the fin along a direction parallel to the surface of the SOI substrate, and the source region (12) and drain region (13) include The direction of the surface of the SOI substrate is away from the portion extending from the other side of the fin. 2. The semiconductor device according to claim 1, further comprising an ultra-steep receding well (42), the ultra-steep receding well (42) being arranged in the other fin adjacent to the channel region and close to the fin A side position. 3. The semiconductor device according to claim 1 or 2, wherein the channel region (11) has a thickness in the range of 5-40 nm. 4. The semiconductor device according to claim 1 or 2, wherein the gate conductor is a metal layer, a doped polysilicon layer, or a stacked gate conductor comprising a metal layer and a doped polysilicon layer. 5. The semiconductor device according to claim 4, wherein the metal layer is selected from TaC, TiN, TaTbN, TaErN, TaYbN, TaSiN, HfSiN, MoSiN, RuTax, NiTax, MoNx, TiSiN, TiCN, TaAlC, TiAlN, Formed from one material in the group consisting of TaN, PtSix, Ni3Si, Pt, Ru, Ir, Mo, HfRu, RuOx and combinations thereof. 6. The semiconductor device according to claim 1 or 2, wherein the gate dielectric (14) is selected from the group consisting of SiO ₂ , Si ₃ N ₄ , HfSiOx, HfO ₂ , ZrO ₂ , Al ₂ O ₃ , TiO ₂ , Formed from one material in the group consisting of La ₂ O ₃ , SrTiO ₃ , LaAlO ₃ , and combinations thereof. 7. The semiconductor device according to claim 1 or 2, further comprising a stress layer (16, 17), the stress layer (16, 17) being arranged on the source region (12) and the drain region (13), And it is used for applying stress to the source region (12) and the drain region (13). 8. The semiconductor device according to claim 7, wherein said source region (12) and drain region (13) comprise a recessed step portion, said stress layer (16, 17) being arranged in said step portion. 9. The semiconductor device according to claim 7, wherein the stressor layer (16, 17) is formed of SiGe or Si:C. 10. The semiconductor device according to claim 1 or 2, further comprising a fin adjacent to the source region (12) and drain region (13) and extending towards the channel region (11) source extension (12') and drain extension (13'). 11. The semiconductor device according to claim 10, further comprising adjoining the source extension region (12') and the drain extension region (13') in the fin and facing the channel region (11 ) extended source halo region (12") and drain halo region (13"). 12. A method of manufacturing a semiconductor device, comprising the steps of: a) Forming fins (23') of semiconductor material in the semiconductor material layer (23) of the SOI substrate by a self-alignment method, said fins (23') comprising two opposite sides perpendicular to the surface of the SOI substrate ; b) forming a stack of gate dielectric (14) and gate conductor on one side of the fin (23'), the gate conductor facing away from the fin in a direction parallel to the surface of the SOI substrate said one side extension of (23'); c) Implanting dopants into the semiconductor material at both ends of the fin (23') to form a source region (12) and a drain region (13), wherein the source region (12) and the drain region (13) include a portion extending away from the other side of the fin in the direction of the SOI substrate surface; and d) Forming the channel region (11) in the middle part of the fin (23'). 13. A method according to claim 12, wherein step a) of forming fins (23') of semiconductor material comprises the steps of: forming a patterned stack structure (24, 25, 26) on the semiconductor material layer (23); forming a conformal oxide layer (28) and a conformal nitride layer on said stack (24, 25, 26) and on the entire exposed surface of said semiconductor material layer (23); selectively removing a portion of said conformal oxide layer (28) and said conformal nitride layer to leave said conformal oxide layer on one sidewall of the stack (24, 25, 26) A portion of (28) and the nitride spacer sidewall (29); and Selectively removing the A layer of semiconductor material (23), leaving a first thickness of semiconductor material in the middle portion of the fin (23'). 14. The method according to claim 13, wherein the step d) of forming the channel region comprises the steps of: Using the part of the conformal oxide layer (28) and the nitride spacer sidewall (29) as a hard mask, selectively remove the stacked structure (24, 25, 26) and semiconductor material A part of the fin (23'), leaving a second thickness of semiconductor material in the middle part of the fin (23') as the channel region (11). 15. The method according to claim 12, after the step d) of forming the channel region, further comprising the following steps: In the middle part of the fin, an ultra-steep receding well (42) adjacent to the channel region (11) is formed at a position close to the other side of the fin. 16. The method of claim 12, wherein the gate conductor is a metal layer, a doped polysilicon layer, or a stacked gate conductor comprising a metal layer and a doped polysilicon layer 17. The method according to claim 12, between the step c) of forming the source region and the drain region and the step d) of forming the channel region, further comprising forming the source region (12) and the drain region (13) Stress layers (16, 17) are formed thereon for applying stress to the source region (12) and the drain region (13). 18. The method of claim 17, wherein the step of forming a stress layer comprises the steps of: Recessed openings (38) are formed in said source region (12) and drain region (13), respectively; and The material of the stress layer (16, 17) is filled in the opening (38). 19. The method of claim 18, further comprising the steps of: An extension implant is performed from the opening (38) to the middle portion of the fin (23') to form the extension region (12', 13') using dip angle ion implantation. 20. The method of claim 19, prior to the step of extending the implant, further comprising the step of: Using oblique ion implantation, halo implantation is performed from the opening (38) to the middle portion of the fin (23') to form halo regions (12", 13"). 21. The method of claim 20, wherein the implant tilt angle used in the extension implant step is smaller than the halo implant step, and the implant energy used in the extension implant step is greater than the halo implant step.

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