CN102033370B - Liquid crystal display substrate and manufacturing method thereof - Google Patents

Abstract

The invention relates to a liquid crystal display substrate and a manufacturing method thereof. The liquid crystal display substrate includes a base substrate, on which a variety of patterns of conductive structures are formed, and the conductive structures are spaced apart from each other or kept insulated by an insulating layer, wherein grooves are formed on the insulating layer formed with the conductive structures, and the conductive structures A pattern is at least partially formed in the trench. The invention adopts the technical means of forming the conductive structure in the groove of the insulating layer, which reduces the height difference of the conductive structure on the lower surface of the insulating layer, thereby reducing the limitation on the thickness of the conductive structure.

Description

Liquid crystal display substrate and manufacturing method thereof

technical field

Embodiments of the present invention relate to liquid crystal display technology, and in particular to a liquid crystal display substrate and a manufacturing method thereof.

Background technique

Thin Film Transistor-Liquid Crystal Display (Thin Film Transistor-Liquid Crystal Display; hereinafter referred to as: TFT-LCD) has the characteristics of small size, low power consumption, and no radiation, and occupies a dominant position in the current flat panel display market.

TFT-LCD usually includes two liquid crystal display substrates arranged in a cell, generally an array substrate and a color filter substrate in a cell, and liquid crystal is filled between them. The array substrate generally includes a base substrate on which data lines and gate scanning lines intersecting horizontally and vertically are formed, surrounding a plurality of pixel units forming a matrix. Each pixel unit is provided with a TFT switch, and the TFT switch includes a gate electrode, an active layer, a source electrode and a drain electrode. The gate electrode is connected to the gate scanning line, and is generally formed at the same time with the same material as the gate scanning line; the source electrode is connected to the data line, and the drain electrode is connected to the pixel electrode. Usually, the source electrode and the drain electrode are formed at the same time with the same material as the data line. The active layer is located between the gate electrode and the source and drain electrodes. When the gate electrode is connected to a high level, the source electrode and the drain electrode are conducted through the active layer, and the voltage of the data line is passed to the pixel electrode.

In the structure of the existing array substrate, there are overlapping areas among the patterns of the conductive structures such as gate scanning lines, gate electrodes, data lines, source electrodes, and drain electrodes, and overlapping capacitors C are easily formed between these overlapping areas. , so that the action time of the TFT switch forms a certain delay. The delay time is also related to the resistance R of the respective conductive structure. The larger the product between the resistor R and the capacitor C, the more pronounced the delay.

Increasing the cross-sectional area of conductive structures is one way to reduce resistance. However, increasing the width of patterns such as data lines and gate scanning lines will reduce the area of the light-transmitting region of the pixel unit, that is, reduce the aperture ratio. If the thickness of patterns such as data lines and gate scanning lines is increased, the height difference between the conductive structure pattern on the array substrate and the insulating layer plane below it will be too large, and it is easy to break when another layer of conductive structure pattern is formed. The phenomenon that causes defects, or is prone to breakage and non-uniformity problems during rubbing, so the prior art usually has a relatively large limit on the thickness of the conductive structure pattern.

Contents of the invention

The object of the present invention is to provide a liquid crystal display substrate and its manufacturing method, so as to reduce the restriction on the thickness of the conductive structure pattern.

In order to achieve the above object, the present invention provides a liquid crystal display substrate, including a base substrate, on which a plurality of patterns of conductive structures are formed, and each of the conductive structures is spaced from each other or kept insulated by an insulating layer, wherein:

A groove is formed on the insulating layer formed with the conductive structure, and the pattern of the conductive structure is at least partially formed in the groove.

In order to achieve the above object, the present invention provides a method for manufacturing a liquid crystal display substrate, comprising the step of forming a pattern of conductive structures spaced apart from each other or kept insulated by an insulating layer on the base substrate, wherein the conductive structure is formed on the insulating layer Previously, also included:

A trench is formed on the insulating layer, and the pattern of the conductive structure is at least partially formed in the trench.

It can be known from the above technical solutions that the present invention adopts the technical means of forming the conductive structure in the groove of the insulating layer, which reduces the height difference of the conductive structure on the lower surface of the insulating layer, thereby reducing the limitation on the thickness of the conductive structure. Appropriately increasing the thickness of different conductive structures can bring many beneficial effects.

Description of drawings

FIG. 1 is a partial top view structural schematic diagram of a liquid crystal display substrate provided by Embodiment 1 of the present invention;

Fig. 2 is a schematic diagram of the cross-sectional structure of A-A in Fig. 1;

Fig. 3 is a schematic diagram of a cross-sectional structure along B-B in Fig. 1;

4 is a schematic diagram of a partial cross-sectional structure of a liquid crystal display substrate provided by Embodiment 2 of the present invention;

FIG. 5 is a partial top view structural diagram of the substrate insulating layer in the liquid crystal display substrate provided by Embodiment 2 of the present invention;

6 is a schematic diagram of a partial cross-sectional structure of a liquid crystal display substrate provided by Embodiment 3 of the present invention;

FIG. 7 is a partial top view structural diagram of a gate insulating layer in a liquid crystal display substrate provided by Embodiment 3 of the present invention;

8 is a flowchart of a method for manufacturing a liquid crystal display substrate provided by Embodiment 4 of the present invention;

FIG. 9 is a flow chart of preparing a substrate insulating layer in the method for manufacturing a liquid crystal display substrate provided in Embodiment 5 of the present invention;

FIG. 10 is a flow chart of a method for manufacturing a liquid crystal display substrate provided by Embodiment 6 of the present invention.

Detailed ways

The present invention will be described in further detail below through specific embodiments and in conjunction with the accompanying drawings.

An embodiment of the present invention provides a liquid crystal display substrate. The liquid crystal display substrate includes a base substrate on which patterns of various conductive structures are formed. Specifically, the conductive structure may include structures such as gate scanning lines, gate electrodes, common electrode lines, data lines, source electrodes, drain electrodes, and pixel electrodes. Each conductive structure is spaced from each other or kept insulated by an insulating layer. For example, the gate scanning line, gate electrode and common electrode line are formed on the base substrate, the data line, source electrode and drain electrode are formed on the gate insulating layer, and the pixel electrode is formed On the passivation layer, the layers are kept insulated from each other. Wherein, a groove is formed on the insulating layer formed with the conductive structure, and the pattern of the conductive structure is at least partially formed in the groove.

By adopting the technical solution of forming the conductive structure in the trench, the exposed height of the conductive structure relative to the surface of the insulating layer where the trench is located can be reduced, and even the conductive structure is flush with the insulating layer. When the photoresist is coated for patterning when other layers are further formed, the photoresist will not be unevenly coated and disconnected on the side of the conductive structure due to the excessive height of the lower conductive structure. The photoresist can maintain the accuracy of the pattern formed by the patterning process, and it is not easy to break the line. The reduction of the height difference of the conductive structure can also avoid the poor alignment rubbing (PI rubbing) formed when the alignment film is coated.

Specifically, for an array substrate in a TFT-LCD, the conductive structure formed in the groove may include at least one of a gate scanning line, a gate electrode, a common electrode line, a data line, a source electrode and a drain electrode. The base substrate is also made of insulating material, which is equivalent to an insulating layer. In order to enable the gate scanning lines, gate electrodes and common electrode lines to be formed in the grooves of the insulating layer, materials that are easy to etch can be used as the base substrate. Or form an insulating layer that is easy to etch on the base substrate.

Forming the above-mentioned conductive structure in the trench can not only avoid defects such as inaccurate patterning, but also reduce the restriction on the thickness of the conductive structure pattern, that is, the thickness of the conductive structure pattern can be appropriately increased. The advantage of increasing the thickness is that the resistance of the conductive structure can be reduced, and the resistance value of the gate scanning line, gate electrode, common electrode line, data line, source electrode and/or drain electrode is reduced, that is, the formed RC value can be reduced , thereby reducing the delay impact on the TFT switching action and optimizing the delay characteristic of the TFT switching action. Alternatively, the width of the conductive structure pattern is reduced while maintaining the resistance constant, thereby increasing the area of the light-permeable region.

Several preferred embodiments of the present invention are described below.

Embodiment one

FIG. 1 is a partial top view structure diagram of a liquid crystal display substrate provided by Embodiment 1 of the present invention, FIG. 2 is a schematic cross-sectional structure diagram along the A-A direction in FIG. 1 , and FIG. 3 is a schematic cross-sectional structure diagram along the B-B direction in FIG. 1 . The liquid crystal display substrate of this embodiment may specifically be an array substrate, including a base substrate 1 on which data lines 2 and gate scanning lines 3 crossing vertically and vertically are formed, surrounding a plurality of array substrates forming a matrix. pixel unit. Each pixel unit is provided with a TFT switch, and the TFT switch includes a gate electrode 4 , an active layer 5 , a source electrode 6 and a drain electrode 7 . The gate electrode 4 is connected to the gate scanning line 3, and is generally formed at the same time as the gate scanning line 3; the source electrode 6 is connected to the data line 2, and the drain electrode 7 is connected to the pixel electrode 16. Usually, the source electrode 6 and the drain electrode 7 are connected to the data line Line 2 is formed simultaneously using the same material. Active layer 5 is located between gate electrode 4 and source electrode 6 and drain electrode 7 . When the gate electrode 4 is connected to a high level, the source electrode 6 and the drain electrode 7 are conducted through the active layer 5 , and the voltage of the data line 2 is passed to the pixel electrode 16 . The common electrode lines 8 for transmitting the common voltage to the common electrodes are usually formed simultaneously with the same material as the gate scanning lines 3 . In order to maintain the insulation between the above-mentioned conductive structures, a gate insulating layer 10 is covered on the gate scanning line 3, the gate electrode 4 and the common electrode line 8, and a passivation layer is covered on the data line 2, the source electrode 6 and the drain electrode 7. layer 11 , the pixel electrode 16 is connected to the drain electrode 7 through the via hole 12 on the passivation layer 11 .

In this embodiment, a layer of insulating layer is also added, that is, the substrate insulating layer 9, which is directly formed on the substrate 1, and the gate scanning line 3, the gate electrode 4 and the common electrode line 8 are formed on the substrate insulating layer. 9 on. The grooves formed on the insulating substrate layer 9 include a first groove 13 , and the gate scanning line 3 , the gate electrode 4 and the common electrode line 8 are formed in the first groove 13 . In this embodiment, the thickness of the gate scanning line 3, the gate electrode 4 and the common electrode line 8 is equal to the depth of the first groove 13. In a specific application, the thickness of the gate scanning line 3, the gate electrode 4 and the common electrode line 8 The thickness may also be larger or smaller than the depth of the first trench 13 .

Adopting the technical scheme of this embodiment, since the gate scanning line 3, the gate electrode 4 and the common electrode line 8 are embedded in the first groove 13, there is no protruding gate scanning line on the surface of the substrate insulating layer 9. 3. The gate electrode 4 and the common electrode line 8, or the thickness of the protruding part is smaller than the thickness of the gate scanning line 3, the gate electrode 4 and the common electrode line 8 when directly formed on the base substrate 1, that is, the thickness of the gate electrode 4 and the common electrode line 8 is formed on the substrate insulating layer. No or small step patterns are formed on the surface of 9 .

Under normal process conditions, the thickness of the gate scan line, gate electrode and common electrode line formed by the gate metal film is generally 200-500 nanometers (nm). In the subsequent patterning process for preparing patterns such as data lines, the side of the step pattern is a weak position. If the height of the step pattern is large, it will cause uneven or disconnected photoresist coating, which will make the subsequent etching pattern Inaccurate. The technical solution of this embodiment reduces the height of the step pattern, can solve the above problems, and make the subsequent etched pattern more accurate, that is, can avoid the problem of disconnection of etched data lines.

In addition, since the side of the step pattern is a weak position, the prior art often needs to increase the thickness of the step pattern and also increase the thickness of the gate insulating layer, which leads to defects between the gate electrode and the active layer, source electrode and drain electrode. As the vertical distance between them increases, a higher voltage needs to be applied to the gate electrode to make the active layer conduct the source electrode and the drain electrode. Therefore, the technical solution of this embodiment also provides the possibility of reducing the thickness of the gate insulating layer, which can effectively reduce the turn-on threshold voltage of the TFT switch and reduce driving power consumption.

Furthermore, the technical solution of this embodiment reduces the restriction on the thickness of the gate scanning line, gate electrode and common electrode line, so the thickness can be increased to reduce the resistance of the conductive structure, thereby optimizing the delay characteristics of the TFT switch and improving the LCD. display quality.

Alternatively, due to the reduction of the thickness limitation, the width of the gate scanning line, gate electrode and common electrode line pattern can be reduced while increasing the thickness. Due to the increase in thickness, reducing the pattern width does not result in a significant increase in resistance. Reducing the width can increase the area of the light-transmitting region in the pixel unit, that is, increase the aperture ratio of the pixel unit.

The pattern of the first trench preferably corresponds to the positions of the gate scanning lines, the gate electrodes and the common electrode lines, and the gate scanning lines, the gate electrodes and the common electrode lines are all formed in the first trench. The pattern of the first groove can also correspond to the position of at least one or more patterns of the gate scanning line, gate electrode and common electrode line according to specific needs, and form part of the patterns of the gate scanning line, gate electrode and common electrode line in the first groove. For example, only forming the first trench at the intersection of the data line and the gate scanning line can avoid the problem of disconnection during the subsequent etching of the data line.

Embodiment two

4 is a schematic diagram of a partial cross-sectional structure of a liquid crystal display substrate provided by Embodiment 2 of the present invention. The difference from Embodiment 1 is that the groove formed on the substrate insulating layer 9 also includes a second groove 14, which is formed on the gate insulating layer 10. The above data line 2 , source electrode 6 and drain electrode 7 are formed in the second trench 14 . The top view structure of the liquid crystal display substrate of this embodiment can be seen in Figure 1, and Figure 4 can be a schematic diagram of cutting the liquid crystal display substrate of this embodiment along the B-B line in Figure 1, and Figure 5 is the second embodiment of the present invention. A partial top view structural schematic diagram of the substrate insulating layer 9 in the liquid crystal display substrate. The first groove 13 and the second groove 14 may be through grooves with equal depth.

Adopting the technical solution of this embodiment can similarly reduce the thickness restriction on the data line, source electrode and drain electrode, thereby reducing its resistance or reducing its width, and can optimize the delay characteristic of the TFT switch or provide the opening of the pixel unit Rate.

In a specific application, the depth of the first groove 13 and the second groove 14 can be equal, preferably the depth of the first groove 13 is greater than the depth of the second groove 14, that is, the second groove 14 for accommodating the data line 2 Slightly shallower than the first trench 13, at the intersection of the data line 2 and the gate scanning line 3, the height that the data line 2 needs to cross the gate scanning line 3 is reduced, which can further reduce the occurrence of data line 2 disconnection possible.

The pattern of the second groove preferably corresponds to the positions of the data line, the source electrode and the drain electrode, and the data line, the source electrode and the drain electrode are all formed in the second groove. The pattern of the second groove can also correspond to the position of at least one or more patterns of the data line, the source electrode and the drain electrode according to specific requirements.

Embodiment three

FIG. 6 is a schematic diagram of a partial cross-sectional structure of a liquid crystal display substrate provided by Embodiment 3 of the present invention, and FIG. 7 is a schematic diagram of a partial top view structure of a gate insulating layer 10 in a liquid crystal display substrate provided by Embodiment 3 of the present invention. In this embodiment, the insulating layer between the data line 2, the source electrode 6 and the drain electrode 7 and the gate scanning line 3, the gate electrode 4 and the common electrode line 8 is a gate insulating layer 10, and the insulating layer formed on the gate insulating layer 10 The trenches include a third trench 15 in which at least one or more of the data line 2 , the source electrode 6 and the drain electrode 7 are formed. The depth of the third trench 15 is smaller than the thickness of the gate insulating layer 10 , so as to avoid contact and conduction with the gate scanning line 3 under the gate insulating layer 10 .

In this embodiment, as shown in FIG. 6 , the substrate insulating layer 9 and the first trench 13 thereon may be included, or the substrate insulating layer 9 may not be provided.

Adopting the technical solution of this embodiment can similarly reduce the thickness restriction on the data line, source electrode and drain electrode, thereby reducing its resistance or reducing its width, and can optimize the delay characteristic of the TFT switch or increase the opening of the pixel unit Rate.

The liquid crystal display substrate provided by the embodiment of the present invention is not limited to the twisted nematic (Twisted Nematic; hereinafter referred to as: TN) type array substrate shown in the figure, and may also be an array substrate forming a horizontal electric field, such as a fringe field switching (Fringe Field Switching; hereinafter referred to as: FFS) type array substrate. Then, the common electrode of the whole pattern can be formed under the substrate insulating layer, and the common electrode of the block pattern at intervals can also be formed on the substrate insulating layer, and the pattern of the common electrode is also formed in the first groove, and the same The gate electrodes and the gate scan lines are spaced apart from each other.

The present invention also provides a method for manufacturing a liquid crystal display substrate, including the step of forming a pattern of conductive structures spaced apart from each other or kept insulated by an insulating layer on the base substrate. Before forming the conductive structure on the insulating layer, the insulating layer A trench is formed on the top, and a pattern of the conductive structure is at least partially formed in the trench. The manufacturing method of the present invention can be used to prepare the liquid crystal display substrate of the present invention, and there may be different manufacturing methods according to the design of the specific process flow, and the preferred embodiments are described below.

Embodiment four

FIG. 8 is a flow chart of a method for manufacturing a liquid crystal display substrate provided in Embodiment 4 of the present invention, including the following steps:

的衬底绝缘薄膜，衬底绝缘薄膜的材料可以选用氧化物、氮化物或者氧氮化合物，对应的化学反应气体为硅烷(SiH4)、氨气(NH3)、氮气(N2)或二氯二氢硅(SiH2Cl2)、氨气(NH3)、氮气(N2)；Step 801, forming a substrate insulating film on the base substrate, the substrate can be a transparent glass plate or a quartz plate, and can be deposited by chemical vapor deposition (PECVD) to a thickness of about 5000-20000 (angstrom).

The substrate insulating film, the material of the substrate insulating film can be oxide, nitride or oxynitride compound, and the corresponding chemical reaction gas is silane (SiH4), ammonia (NH3), nitrogen (N2) or dichlorodihydrogen Silicon (SiH2Cl2), ammonia (NH3), nitrogen (N2);

Step 802, performing a patterning process on the substrate insulating film to form a pattern of the substrate insulating layer including the first groove. The so-called patterning process includes operations such as exposure and development, etching and stripping;

的栅金属薄膜，栅金属薄膜可以选用Cr、W、Ti、Ta、Mo、Al或Cu等金属或合金，由多层金属组成的栅金属层也能满足需要；Step 803, depositing a gate metal thin film on the insulating layer of the substrate, which can be deposited by sputtering or thermal evaporation with a thickness of 5000~

The gate metal film can be selected from metals or alloys such as Cr, W, Ti, Ta, Mo, Al or Cu, and the gate metal layer composed of multi-layer metals can also meet the needs;

Step 804, patterning the gate metal film to form a pattern including gate electrodes, gate scanning lines and common electrode lines, and at least one of the gate electrodes, gate scanning lines and common electrode lines is formed in the first trench ;

的栅绝缘层、厚度为1000～

的半导体层、厚度为500～

欧姆接触层，半导体层和欧姆接触层共同构成有源层，栅绝缘层可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体可以为SiH4、NH3、N2或SiH2Cl2、NH3、N2，半导体层对应的反应气体可以是SiH4、H2或SiH2Cl2、氢气(H2)，欧姆接触层的反应气体可为SiH4、磷化氢(PH3)，H2或SiH2Cl2、PH3、H2，可以通过溅射或热蒸发方法来沉积厚度为2000～

的数据线金属薄膜，数据线金属薄膜可以选用(铬)Cr、(钨)W、(钛)Ti、(钽)Ta、(钼)Mo、(铝)Al或(铜)Cu等金属和合金，可以是单层也可以是多层；Step 805, form a gate insulating layer, an active layer film and a data line metal film on the base substrate on which the gate electrode, gate scanning line and common electrode line are formed, which can be sequentially deposited by PECVD with a thickness of about 3000~

The gate insulating layer with a thickness of 1000~

The semiconductor layer, the thickness is 500~

The ohmic contact layer, the semiconductor layer and the ohmic contact layer together constitute the active layer. The gate insulating layer can be made of oxide, nitride or oxynitride compound, and the corresponding reaction gas can be SiH4, NH3, N2 or SiH2Cl2, NH3, N2. The reaction gas corresponding to the layer can be SiH4, H2 or SiH2Cl2, hydrogen (H2), the reaction gas of the ohmic contact layer can be SiH4, phosphine (PH3), H2 or SiH2Cl2, PH3, H2, can be sputtered or thermally evaporated method to deposit a thickness of 2000~

The data line metal film, the data line metal film can be selected from (chromium) Cr, (tungsten) W, (titanium) Ti, (tantalum) Ta, (molybdenum) Mo, (aluminum) Al or (copper) Cu and other metals and alloys , can be single-layer or multi-layer;

Step 806, patterning the data line metal film and the active layer film to form a pattern including the data line, source electrode, drain electrode and active layer, the data line, The pattern of the source electrode and the drain electrode, and the pattern of the TFT channel on the active layer;

的钝化层薄膜，钝化层薄膜可以选用氧化物、氮化物或者氧氮化合物，对应的反应气体可以为SiH4、NH3、N2或SiH2Cl2、NH3、N2；Step 807, form a passivation layer film on the base substrate forming the data line, source electrode, drain electrode and active layer, which can be deposited by PECVD with a thickness of about 1500~

The passivation layer film can be oxide, nitride or oxynitride compound, and the corresponding reaction gas can be SiH4, NH3, N2 or SiH2Cl2, NH3, N2;

Step 808, performing a patterning process on the passivation layer film to form a pattern of the passivation layer of the via hole, where the via hole corresponds to the position of the drain electrode;

Step 809, depositing a thin film of the pixel electrode on the passivation layer, which can be deposited by sputtering or thermal evaporation with a thickness of 300~ The pixel electrode film can be made of indium tin oxide (Indium Tin Oxides; hereinafter referred to as: ITO) or indium zinc oxide (Indium Zinc Oxides; hereinafter referred to as: IZO), or other transparent metals and metal oxides. ;

Step 810, patterning the pixel electrode film to form a pattern including the pixel electrode.

The structure of the liquid crystal display substrate formed by the above steps can be referred to as shown in FIGS. 1-3 . The thickness restriction on the gate scanning line, gate electrode and common electrode line is reduced, the thickness can be increased to reduce resistance, the TFT delay characteristic can be optimized, and the width can also be reduced to increase the aperture ratio.

On the basis of this embodiment, it is not limited to prepare the TN-type array substrates shown in Fig. Before forming the substrate insulating film on the substrate, it also includes: depositing a whole common electrode on the substrate substrate, and then forming the substrate insulating film.

Alternatively, before depositing the gate metal thin film on the insulating substrate layer, it may also include: depositing a common electrode thin film on the insulating substrate layer, forming a pattern of spaced block common electrodes by patterning, and forming a pattern of the common electrode In part of the first trenches, the gate scanning lines and the gate electrodes formed in the first trenches are spaced apart from each other. The pattern of the first groove can be patterned according to the requirement of mutual interval.

Forming patterns of conductive structures spaced apart from each other or kept insulated by an insulating layer on the base substrate, and the step of forming a groove on the insulating layer may also specifically include:

performing a patterning process on the gate insulating layer covering the gate electrode and the gate scanning line to form a pattern of the gate insulating layer including a third trench, and the depth of the third trench is smaller than the thickness of the gate insulating layer;

Deposit active layer thin film and data line metal thin film on the gate insulating layer;

Patterning the data line metal film and the active layer film to form a pattern including a data line, a source electrode, a drain electrode and an active layer, at least one of the data line, source electrode and drain electrode is formed in the in three grooves.

The technique for forming the third trench can be implemented independently, or can be implemented in combination with the solution of Embodiment 4.

Embodiment five

The method for manufacturing a liquid crystal display substrate provided in Embodiment 5 of the present invention can be based on Embodiment 4, and step 802 can be specifically: performing a patterning process on the substrate insulating film, and simultaneously forming the first groove and the second groove The pattern of the substrate insulating layer, the position of the second groove corresponds to the position of at least one of the data line, the source electrode and the drain electrode.

The structure of the liquid crystal display substrate formed by this solution can be seen in FIGS. 4 and 5 . It is possible to further reduce the thickness limitation on the data lines, source electrodes and drain electrodes, increase their thickness to reduce resistance, optimize TFT delay characteristics, and reduce their width to increase aperture ratio.

Perform a patterning process on the substrate insulating film to form a pattern of the substrate insulating layer including the first groove and the second groove. Specifically, the first groove and the second groove with the same depth can be formed simultaneously through a patterning process. pattern.

Alternatively, performing a patterning process on the substrate insulating film to form the pattern of the substrate insulating layer including the first trench and the second trench may also be to form the first trench and the second trench with different depths, and the first trench The depth of the groove is greater than the depth of the second groove. The first groove and the second groove can be formed respectively through two patterning processes, or can be realized by the following steps, as shown in Figure 9:

Step 901, coating photoresist on the substrate insulating film;

Step 902, using a two-tone mask, that is, a gray-tone mask or a half-tone mask, to expose and develop the photoresist to form a completely reserved area, a partially reserved area, and a completely removed area;

Step 903, perform the first etching, etch to completely remove the substrate insulating film corresponding to the region, and form a pattern of the substrate insulating layer including the partial depth of the first groove;

Step 904, ashing and removing the photoresist according to the thickness of the photoresist in the partially reserved area, the photoresist in the partially reserved area is completely removed, and the photoresist in the completely reserved area still has a certain thickness;

Step 905, perform a second etching, etch the substrate insulating film corresponding to the partially reserved area and the completely removed area, and form a pattern of the substrate insulating layer including the first trench and the second trench. At this time, the first trench After the depth of the groove is equal to the depth of the two etchings, the depth of the first groove is greater than the depth of the second groove.

The above scheme can form the first groove and the second groove through one mask exposure and two etchings, the process is simple, and the production efficiency can be improved.

Embodiment six

FIG. 10 is a flowchart of a method for manufacturing a liquid crystal display substrate provided in Embodiment 6 of the present invention, including the following steps:

Step 1001, forming a substrate insulating film on the substrate;

Step 1002, coating photoresist on the substrate insulating film;

Step 1003, using a monotone mask to expose and develop the photoresist to form a completely removed area and a completely reserved area;

Step 1004, etching the substrate insulating film to form a pattern of the substrate insulating layer including the first trench;

Step 1005, depositing a gate metal film on the substrate insulating layer coated with photoresist, and depositing the gate metal film in the photoresist and the first trench;

Step 1006, the photoresist and the gate metal film on it can be stripped by laser or other methods to form a pattern including gate electrodes, gate scanning lines and common electrode lines, and the gate electrodes, gate scanning lines and common electrode lines remain on the in the first groove;

Step 1007, forming a gate insulating layer, an active layer thin film and a data line metal thin film on the substrate on which the gate electrodes, gate scanning lines and common electrode lines are formed;

Step 1008, patterning the data line metal film and the active layer film to form a pattern including the data line, source electrode, drain electrode and active layer;

Step 1009, forming a passivation layer film on the base substrate on which the data line, source electrode, drain electrode and active layer are formed;

Step 1010, patterning the passivation layer film to form a passivation layer pattern including via holes;

Step 1011, depositing a pixel electrode thin film on the passivation layer;

Step 1012 , patterning the pixel electrode film to form a pattern including the pixel electrode.

On the basis of the above technical solution, after forming the gate electrode, gate scanning line and common electrode line, patterning process can be carried out on the substrate insulating layer on which the gate electrode, gate scanning line and common electrode line are formed. The pattern of the second trench is formed on the substrate insulating layer, so that the subsequently formed gate insulating layer, active layer, data line, source electrode and drain electrode are formed on the substrate insulating layer with the second trench, and the second trench The groove corresponds to the position of at least one of the data line, the source electrode and the drain electrode, thereby reducing thickness restrictions on the data line, the source electrode and/or the drain electrode.

The manufacturing method of the liquid crystal display substrate provided by the present invention can be used to prepare the liquid crystal display substrate of the present invention, but the liquid crystal display substrate of the present invention is not limited to be prepared by the above manufacturing method, and can also be prepared by other methods. The technical solution of the present invention provides a technical solution capable of reducing the limitation on the thickness of the conductive structure. The thickness of each conductive structure can be appropriately increased, which can bring many advantages: the resistance of the conductive structure can be reduced by increasing the thickness, such as the resistance of the gate scanning line, gate electrode, data line, source electrode and drain electrode. , can reduce the RC value, thereby optimizing the delay characteristics of the TFT switch and improving the display quality; on the premise that the thickness can be increased, the width of the conductive structure pattern can be appropriately reduced, which can increase the area of the light-transmitting region and increase the aperture ratio; The lower conductive structure is embedded in the groove, so that when the pattern of the upper conductive structure is etched, the photoresist can be coated more uniformly, the pattern is etched more accurately, and the disconnection is not easy to occur; the gate scanning line and the gate electrode are embedded in the groove In this case, the thickness of the gate insulating layer can be appropriately reduced, the distance between the gate electrode and the source electrode and the drain electrode can be shortened, and the voltage value at which the gate electrode drives the TFT switch to turn on can be reduced, and the driving power consumption can be reduced.

The technical scheme of the invention is not only applicable to liquid crystal display substrates, but also applicable to various semiconductor integrated devices.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still be Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims (6)

1. A liquid crystal display substrate, comprising a base substrate, the pattern of multiple conductive structures is formed on the base substrate, each of the conductive structures is spaced from each other or kept insulated by an insulating layer, and formed on the insulating layer of the conductive structure There is a groove in which the pattern of the conductive structure is at least partially formed; The conductive structure formed in the trench includes at least one of a gate scan line, a gate electrode, a common electrode line, a data line, a source electrode and a drain electrode; The insulating layer between the gate scanning line, the gate electrode or the common electrode line and the base substrate is a substrate insulating layer, and the grooves formed on the substrate insulating layer include a first groove, and the gate At least one of a pole scan line, a gate electrode, and a common electrode line is formed in the first trench; It is characterized in that the insulating layer covering the gate scanning line, gate electrode or common electrode line is a gate insulating layer, and the data line, source electrode and drain electrode are formed on the gate insulating layer; The trench formed on the substrate insulating layer further includes a second trench, at least one of the data line, the source electrode and the drain electrode formed on the gate insulating layer is formed in the second trench middle. 2. The liquid crystal display substrate according to claim 1, wherein the depth of the first groove is greater than or equal to the depth of the second groove. 3. A method for manufacturing a liquid crystal display substrate, comprising the step of forming a pattern of mutually spaced or insulating conductive structures on the base substrate, before forming the conductive structures on the insulating layer, it also includes: forming a trench on the insulating layer, the pattern of the conductive structure being at least partially formed in the trench; Forming a pattern of conductive structures spaced apart from each other or kept insulated by an insulating layer on the base substrate, and forming a trench on the insulating layer includes: forming a substrate insulating film on the substrate substrate; performing a patterning process on the substrate insulating film to form a pattern of the substrate insulating layer including the first trench; Depositing a gate metal film on the insulating layer of the substrate; performing a patterning process on the gate metal thin film to form a pattern including gate electrodes, gate scan lines and common electrode lines, and at least one of the gate electrodes, gate scan lines and common electrode lines is formed on the first in the groove; It is characterized in that, while performing a patterning process on the substrate insulating film to form a pattern of the substrate insulating layer including the first groove, it also includes: A pattern of a second groove is formed on the substrate insulating layer, and the position of the second groove corresponds to the position of at least one of the data line, the source electrode and the drain electrode. 4. The method for manufacturing a liquid crystal display substrate according to claim 3, wherein a patterning process is performed on the insulating substrate film to form a pattern of the insulating substrate layer comprising a first groove and a second groove comprising : Coating photoresist on the substrate insulating film; Exposing and developing the photoresist by using a two-tone mask to form a completely reserved area, a partially reserved area and a completely removed area; Performing the first etching, etching the substrate insulating film corresponding to the completely removed region, forming a pattern of the substrate insulating layer including the first trench with a partial depth; Ashing and removing the photoresist according to the thickness of the photoresist in the partially reserved area; Carrying out the second etching, etching the substrate insulating film corresponding to the partially reserved region and the completely removed region, forming a pattern of the substrate insulating layer including the first groove and the second groove, and the first groove The depth of the groove is greater than the depth of the second groove. 5. The method for manufacturing a liquid crystal display substrate according to claim 3, wherein forming a pattern of conductive structures spaced from each other or kept insulated by an insulating layer on the base substrate, and forming a groove on the insulating layer comprises: forming a substrate insulating film on the substrate substrate; Coating photoresist on the substrate insulating film; Exposing and developing the photoresist by using a monotone mask to form a completely removed area and a completely reserved area; Etching the substrate insulating film to form a pattern of the substrate insulating layer including the first trench; depositing a gate metal thin film on the substrate insulating layer coated with photoresist; peeling off the photoresist and the gate metal film on it to form a pattern including gate electrodes, gate scanning lines and common electrode lines, and the gate electrodes, gate scanning lines and common electrode lines remain on the first in the trench. 6. The method for manufacturing a liquid crystal display substrate according to claim 5, further comprising: A patterning process is performed on the insulating substrate layer forming the gate electrode, the gate scanning line and the common electrode line, and a pattern of the second trench is formed on the insulating substrate layer.

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