CN102044203B

CN102044203B - Drive circuit

Info

Publication number: CN102044203B
Application number: CN 200910179785
Authority: CN
Inventors: 叶松铫; 吴文琦
Original assignee: ILI Techonology Corp
Current assignee: ILI Techonology Corp
Priority date: 2009-10-19
Filing date: 2009-10-19
Publication date: 2013-01-16
Anticipated expiration: 2029-10-19
Also published as: CN102044203A

Abstract

A driving circuit includes a first data logic unit, a latch unit and a determining unit. The first data logic unit is used for receiving at least one digital data signal and a first control signal, and selectively inverting the digital data signal according to the first control signal to generate a first digital output data signal; the bolt-lock unit is used for receiving the first digital output data signal and a second control signal and selectively setting whether an output second digital output data signal is in an inverse phase with the first digital output data signal or not according to the second control signal; the judging unit is used for receiving the digital data signal, judging the number of transition times of the digital data signal compared with the previous digital data signal, and outputting the first control signal and the second control signal according to the number of transition times.

Description

Driving circuit

Technical field

The invention relates to a kind of driving circuit, espespecially a kind of one source pole driving circuit (source driver) that is applied in the display panels, this source electrode drive circuit can reduce power consumption, thermal value and electromagnetic interference (EMI) (electromagnetic interference, EMI) effectively.

Background technology

What Fig. 1 illustrated is the simplification block schematic diagram that is applied to the one source pole driving circuit 100 in the display panels in the known technology.As shown in Figure 1, source electrode drive circuit 100 includes: a mathematical logic unit 102 and a bolt-lock (latch) unit 104.In known technology, because the RGB data-signal is constantly to be sent to bolt-lock unit 104 from mathematical logic unit 102, passage (channel) number that needs when source electrode drive circuit is more and more many, data-signal transmission path from mathematical logic unit 102 to bolt-lock unit 104 will be longer, and load also just becomes heavier thereupon; In addition, because high resolving power and the demand that reduces cost, the operating frequency that needs is also more and more high.These factors all can cause the rising of operating current, cause power consumption, thermal value and the electromagnetic interference (EMI) (electromagnetic interference, EMI) of source electrode drive circuit 100 to become larger, and the life-span become shorter.For instance, if the digital data signal that mathematical logic unit 102 receives is 6 RGB data-signal, and be that the RGB data-signal is separately judged, suppose that then this stroke numeral data-signal S is 111111, and last stroke numeral data-signal is 000000, total the transition number of times of the data-signal on the data-signal transmission path between the first mathematical logic unit 202 and the bolt-lock unit 204 is exactly 6 times so.Total transition number of times the more, it is larger that the power consumption of source electrode drive circuit 100, thermal value and electromagnetic interference (EMI) also can become.

Summary of the invention

In view of this, one of purpose of the present invention is to provide a kind of driving circuit that can effectively reduce power consumption, thermal value and electromagnetic interference (EMI) (electromagnetic interference, EMI), to solve the above problems.

According to one aspect of the present invention, it discloses a kind of driving circuit, and this driving circuit includes: one first mathematical logic unit, a bolt-lock (latch) unit and a judging unit.This first mathematical logic unit is used for receiving digital data signal and one first control signal of at least one N position, and comes the digital data signal of anti-phase this N position optionally to produce first a digital output data signal according to this first control signal; This bolt-lock unit is coupled to this first mathematical logic unit, be used for receiving this pen the first digital output data signal and one second control signal, and whether optionally set second a digital output data signal of exporting according to this second control signal anti-phase in this pen the first digital output data signal; And this judging unit is coupled to this first mathematical logic unit and this bolt-lock unit, be used for receiving the digital data signal of this N position and judge the digital data signal of this N position compared to a transition number of times of the digital data signal of last N position, and export this first control signal and this second control signal according to this transition number of times.

According to another aspect of the present invention, it discloses a kind of driving circuit, and this driving circuit includes: one first mathematical logic unit, one second mathematical logic unit, a bolt-lock (latch) unit, one first judging unit and one second judging unit.This first mathematical logic unit is used for receiving digital data signal and one first control signal of at least one N position, and comes the digital data signal of anti-phase this N position optionally to produce first a digital output data signal according to this first control signal; This second mathematical logic unit is used for receiving this pen the first digital output data signal and one second control signal, and comes optionally anti-phase this pen first digital output data signal to produce second a digital output data signal according to this second control signal; This bolt-lock unit is coupled to this second mathematical logic unit, and be used for receiving this pen the second digital output data signal and one the 3rd control signal, and whether optionally set one the 3rd digital output data signal of exporting according to the 3rd control signal anti-phase in this pen the second digital output data signal; This first judging unit is coupled to this first mathematical logic unit, and be used for receiving the digital data signal of this N position and judge the digital data signal of this N position compared to a transition number of times of the digital data signal of last N position, and export this first control signal and one the 4th control signal according to this transition number of times; And this second judging unit is coupled to this second mathematical logic unit, this first judging unit and this bolt-lock unit, and be used for receiving digital data signal and the 4th control signal of this N position, and come optionally the 4th control signal to be set as the 3rd control signal or judge that the digital data signal of this N position sets this second control signal and the 3rd control signal compared to this transition number of times of the digital data signal of last N position according to the 4th control signal.

In sum, the disclosed driving circuit of the present invention can be between mathematical logic unit and bolt-lock unit the data-signal transmission path reduce total transition number of times of data-signal, therefore, the disclosed driving circuit of the present invention can reduce power consumption, thermal value and electromagnetic interference (EMI) (electromagnetic interference, EMI) effectively.

Description of drawings

What Fig. 1 illustrated is the simplification block schematic diagram that is applied to the one source pole driving circuit in the display panels in the known technology.

The simplification block schematic diagram that is applied to the one source pole driving circuit in the display panels for foundation one first embodiment of the present invention that Fig. 2 illustrates.

The simplification block schematic diagram that is applied to the one source pole driving circuit in the display panels for foundation one second embodiment of the present invention that Fig. 3 illustrates.

The simplification block schematic diagram that is applied to the one source pole driving circuit in the display panels for foundation one the 3rd embodiment of the present invention that Fig. 4 illustrates.

[main element label declaration]

100: source electrode drive circuit 102: the mathematical logic unit

104: bolt-lock unit 200: source electrode drive circuit

202: the first mathematical logic unit 204: bolt-lock unit

206: judging unit 210: the source electrode drive circuit chip

300: 302: the first mathematical logic unit of source electrode drive circuit

304: bolt-lock unit 306: judging unit

308: the second mathematical logic unit 310: source electrode drive circuit chip

400: 402: the first mathematical logic unit of source electrode drive circuit

403: the second mathematical logic unit 404: bolt-lock unit

408: the second judging units of 406: the first judging units

410: the source electrode drive circuit chip

Embodiment

In the middle of this instructions and above-mentioned claim, used some vocabulary to censure specific element, and those skilled in the art should understand, hardware manufacturer may be called same element with different nouns, this instructions and above-mentioned claim are not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function, be an open term mentioned " including " in the middle of instructions and the above-mentioned request item in the whole text, therefore should be construed to " include but be not limited to ", in addition, " coupling " word is to include any means that indirectly are electrically connected that directly reach at this, therefore, be coupled to one second device if describe a first device in the literary composition, then represent this first device and can directly be electrically connected in this second device, or indirectly be electrically connected to this second device by other device or connection means.

Please refer to Fig. 2, the simplification block schematic diagram that is applied to the one source pole driving circuit 200 in the display panels for foundation one first embodiment of the present invention that Fig. 2 illustrates.As shown in Figure 2, source electrode drive circuit 200 includes: one first mathematical logic unit 202, a bolt-lock (latch) unit 204 and a judging unit 206.The first mathematical logic unit 202 is used for receiving digital data signal S and the one first control signal C1 of at least one N position, and comes the digital data signal of anti-phase this N position optionally to produce first a digital output data signal S1 according to the first control signal C1; Bolt-lock unit 204 is coupled to the first mathematical logic unit 202, be used for receiving this pen the first digital output data signal S1 and one second control signal C2, and whether optionally set second a digital output data signal S2 who exports according to the second control signal C2 anti-phase in this pen the first digital output data signal S1; And judging unit 206 is coupled to the first mathematical logic unit 202 and bolt-lock unit 204, be used for receiving the digital data signal of this N position and judge that the digital data signal S of this N position is compared to the transition number of times of the digital data signal of last N position, and export the first control signal C1 and the second control signal C2 according to the transition number of times, please note at this, the first control signal C1 and this second control signal C2 can be identical logical signal (for example 1), also can be not identical logical signal (for example 1 and 0).Wherein, when the first control signal C1 triggered the first mathematical logic unit 202, the first mathematical logic unit 202 can be anti-phase with as this pen the first digital output data signal S1 with the digital data signal of this N position; And when the second control signal C2 triggers bolt-lock unit 204, this pen the second digital output data signal S2 that bolt-lock unit 204 is exported is anti-phase with this pen the first digital output data signal S1, in other words, exactly the digital data signal S of this N position is used as this pen the second digital output data signal S2; And when transition number of times during greater than N/2, judging unit 206 will trigger the first control signal C1 and the second control signal C2.In addition, please note that the first mathematical logic unit 202, bolt-lock unit 204 and judging unit 206 are arranged in the one source pole drive circuit chip (source driver chip) 210.

For instance, if the digital data signal that the first mathematical logic unit 202 receives is 6 RGB data-signal, and be that the RGB data-signal is separately judged, suppose that then this stroke numeral data-signal S is 111100, and last stroke numeral data-signal is 110011, therefore, judging unit 206 can judge that this stroke numeral data-signal S equals 4 (namely greater than 3) compared to a transition number of times of last stroke numeral data-signal, and judging unit 206 will trigger the first control signal C1 and the second control signal C2, and when the first control signal C1 triggers the first mathematical logic unit 202, the first mathematical logic unit 202 can be anti-phase with as this pen the first digital output data signal S1 (000011) with this stroke numeral data-signal S (111100), thus, total transition number of times of the data-signal on the data-signal transmission path between the first mathematical logic unit 202 and the bolt-lock unit 204 just can be reduced to 2 times from 4 times; And when the second control signal C2 triggers bolt-lock unit 204, this pen the second digital output data signal S2 (111100) that bolt-lock unit 204 is exported is anti-phase with this pen the first digital output data signal S1 (000011), in other words, exactly this stroke numeral data-signal S (111100) is used as this pen the second digital output data signal S2 (111100), the signal that also is about to export bolt-lock unit 204 is reduced to this stroke numeral data-signal S (111100).In addition, if the RGB data-signal is judged together, then the digital data signal that receives of the first mathematical logic unit 202 will become 18 data-signal, in other words, when judging unit 206 judge this stroke numeral data-signal S compared to a transition number of times of last stroke numeral data-signal greater than 9 the time, judging unit 206 just can trigger the first control signal C1 and the second control signal C2.

Thus, data-signal transmission path that just can be between the first mathematical logic unit 202 and bolt-lock unit 204 reduces total transition number of times of data-signal, therefore the disclosed driving circuit 200 of the present invention can reduce power consumption, thermal value and electromagnetic interference (EMI) (electromagneticinterference, EMI) effectively.In addition, if the digital data signal that the first mathematical logic unit 202 receives is the RGB data-signal of 6,2 buses (that is 2 pixels), and be that the RGB data-signal is separately judged, then drive circuit chip 210 has that 36 signal line are used for transmitting the RGB data-signal and 6 signal line are used for transmitting the first control signal C1 and the second control signal C2; If the RGB data-signal judges together, then drive circuit chip 210 has that 36 signal line are used for transmitting the RGB data-signal and 1 signal line is used for transmitting the first control signal C1 and the second control signal C2.Note that at this above embodiments only illustrate as of the present invention, rather than restrictive condition of the present invention, for instance, the figure place of above-mentioned RGB data-signal and bus number all can change according to various design requirement.

Please refer to Fig. 3, the simplification block schematic diagram that is applied to the one source pole driving circuit 300 in the display panels for foundation one second embodiment of the present invention that Fig. 3 illustrates.As shown in Figure 3, source electrode drive circuit 300 includes: one first mathematical logic unit 302, a bolt-lock (latch) unit 304, a judging unit 306 and one second mathematical logic unit 308.The first mathematical logic unit 302 is used for receiving digital data signal S and the one first control signal C1 of at least one N position, and comes the digital data signal of anti-phase this N position optionally to produce first a digital output data signal S1 according to the first control signal C1; Bolt-lock unit 304 is coupled to the first mathematical logic unit 302, be used for receiving this pen the first digital output data signal S1 and one second control signal C2, and whether optionally set second a digital output data signal S2 who exports according to the second control signal C2 anti-phase in this pen the first digital output data signal S1; And judging unit 306 is coupled to the first mathematical logic unit 302 and bolt-lock unit 304, be used for receiving the digital data signal of this N position and judge that the digital data signal S of this N position is compared to a transition number of times of the digital data signal of last N position, and export the first control signal C1 and the second control signal C2 according to the transition number of times, please note at this, the first control signal C1 and this second control signal C2 can be identical logical signal (for example 1), also can be not identical logical signal (for example 1 and 0).The second mathematical logic unit 308 is coupled between the first mathematical logic unit 302 and this bolt-lock unit 304, and is used for receiving and exporting this pen the first digital output data signal S1.Wherein, when the first control signal C1 triggered the first mathematical logic unit 302, the first mathematical logic unit 302 can be anti-phase with as this pen the first digital output data signal S1 with the digital data signal of this N position; And when the second control signal C2 triggers bolt-lock unit 304, this pen the second digital output data signal S2 that bolt-lock unit 304 is exported is anti-phase with this pen the first digital output data signal S1, in other words, exactly the digital data signal S of this N position is used as this pen the second digital output data signal S2; When transition number of times during greater than N/2, judging unit 306 will trigger the first control signal C1 and the second control signal C2.In addition, please noting that the second mathematical logic unit 308 and bolt-lock unit 304 are arranged at is applied in the one source pole drive circuit chip (source driver chip) 310, and the first mathematical logic unit 302 and judging unit 306 are to be external in source electrode drive circuit chip 310.

For instance, if the digital data signal that the first mathematical logic unit 302 receives is 6 RGB data-signal, and be that the RGB data-signal is separately judged, suppose that this stroke numeral data-signal S is 111100, and last stroke numeral data-signal is 110011, therefore, judging unit 306 can judge that this stroke numeral data-signal S equals 4 (namely greater than 3) compared to a transition number of times of last stroke numeral data-signal, and judging unit 306 will trigger the first control signal C1 and the second control signal C2, and when the first control signal C1 triggers the first mathematical logic unit 302, the first mathematical logic unit 302 can be anti-phase with as this pen the first digital output data signal S1 (000011) and output to the second mathematical logic unit 308 with this stroke numeral data-signal S (111100), and the second mathematical logic unit 308 should output to bolt-lock unit 304 by pen the first digital output data signal S1 (000011) again, thus, total transition number of times of the data-signal on the data-signal transmission path between the first mathematical logic unit 302 and the bolt-lock unit 304 just can be reduced to 2 times from 4 times; And when the second control signal C2 triggers bolt-lock unit 304, this pen the second digital output data signal S2 (111100) that bolt-lock unit 304 is exported is anti-phase with this pen the first digital output data signal S1 (000011), in other words, exactly this stroke numeral data-signal S (111100) is used as this pen the second digital output data signal S2 (111100), the signal that also is about to export bolt-lock unit 304 is reduced to this stroke numeral data-signal S (111100).In addition, if the RGB data-signal is judged together, then the digital data signal that receives of the first mathematical logic unit 302 will become 18 data-signal, in other words, when judging unit 306 judge this stroke numeral data-signal S compared to the transition number of times of last stroke numeral data-signal greater than 9 the time, judging unit 306 just can trigger the first control signal C1 and the second control signal C2.

Thus, data-signal transmission path that just can be between the second mathematical logic unit 308 and bolt-lock unit 304 reduces total transition number of times of data-signal.Therefore, the disclosed driving circuit 300 of the present invention can reduce power consumption, thermal value and electromagnetic interference (EMI) (electromagneticinterference, EMI) effectively.In addition, if the digital data signal that the first mathematical logic unit 302 receives is the RGB data-signal of 6,2 buses (that is 2 pixels), and be that the RGB data-signal is separately judged, then drive circuit chip 310 has that 36 signal line are used for transmitting the RGB data-signal and 6 signal line are used for transmitting the first control signal C1 and the second control signal C2; If the RGB data-signal judges together, then drive circuit chip 310 has that 36 signal line are used for transmitting the RGB data-signal and 1 signal line is used for transmitting the first control signal C1 and the second control signal C2.Note that at this above embodiments only illustrate as of the present invention, rather than restrictive condition of the present invention, for instance, the figure place of above-mentioned RGB data-signal and bus number all can change according to various design requirement.

Please refer to Fig. 4, the simplification block schematic diagram that is applied to the one source pole driving circuit 400 in the display panels for foundation one the 3rd embodiment of the present invention that Fig. 4 illustrates.As shown in Figure 4, source electrode drive circuit 400 includes: one first mathematical logic unit 402, one second mathematical logic unit 403, a bolt-lock (latch) unit 404, one first judging unit 406 and one second judging unit 408.Please note at this, the second mathematical logic unit 403, bolt-lock unit 404 and the second judging unit 408 are to be arranged in the one source pole drive circuit chip (source driver chip) 410, and source electrode drive circuit chip 410 is identical with source electrode drive circuit chip 210 in the first embodiment of the present invention, for for purpose of brevity, do not add to give unnecessary details at this.In the present embodiment, the first mathematical logic unit 402 and the first judging unit 406 are to be external in source electrode drive circuit chip 410, and the function of the first mathematical logic unit 402 and the first judging unit 406 is identical with the first mathematical logic unit 302 and judging unit 306 in the second embodiment of the present invention, therefore, in source electrode drive circuit 400, can select to utilize the second mathematical logic unit 403 and the second judging unit 408 in the source electrode drive circuit chip 410 to carry out the operation identical with the first embodiment of the present invention, or utilize the first mathematical logic unit 402 and the first judging unit 406 that are external in source electrode drive circuit chip 410 to carry out the operation identical with the second embodiment of the present invention, similarly, source electrode drive circuit 400 also can be between the second mathematical logic unit 403 and bolt-lock unit 404 the data-signal transmission path reduce total transition number of times of data-signal, so the disclosed driving circuit 400 of the present invention also can reduce power consumption effectively, thermal value and electromagnetic interference (EMI).

For instance, the first mathematical logic unit 402 is used for receiving digital data signal S and the one first control signal C1 of at least one N position, and comes the digital data signal S of anti-phase this N position optionally to produce first a digital output data signal S1 according to the first control signal C1; The second mathematical logic unit 403 is coupled to the first mathematical logic unit 402, and be used for receiving this pen the first digital output data signal S1 and one second control signal C2, and come optionally anti-phase this pen the first digital output data signal S1 to produce second a digital output data signal S2 according to the second control signal C2; Bolt-lock unit 404 is coupled to the second mathematical logic unit 403, and be used for receiving this pen the second digital output data signal S2 and one the 3rd control signal C3, and whether optionally set one the 3rd digital output data signal S3 that exports according to the 3rd control signal C3 anti-phase in this pen the second digital output data signal S2; The first judging unit 406 is coupled to the first mathematical logic unit 402, and be used for receiving the digital data signal S of this N position and judge that the digital data signal S of this N position is compared to a transition number of times of the digital data signal of last N position, and export the first control signal C1 and one the 4th control signal C4 according to this transition number of times, please note at this, the first control signal C1 and the 4th control signal C4 can be identical logical signal (for example 1), also can be not identical logical signal (for example 1 and 0); And second judging unit 408 be coupled to the second mathematical logic unit 403, the first judging unit 406 and bolt-lock unit 404, and be used for receiving digital data signal S and the 4th control signal C4 of this N position, and foundation the 4th control signal C4 comes optionally the 4th control signal C4 to be set as the 3rd control signal C3 or judges that the digital data signal S of this N position sets the second control signal C2 and the 3rd control signal C3 compared to this transition number of times of the digital data signal of last N position, please note at this, the second control signal C2 and the 3rd control signal C3 can be identical logical signal (for example 1), also can be not identical logical signal (for example 1 and 0).Wherein, when the first control signal C1 triggered the first mathematical logic unit 402, the first mathematical logic unit 402 can be anti-phase with as this pen the first digital output data signal S1 with the digital data signal S of this N position; When the second control signal C2 triggered the second mathematical logic unit 403, the second mathematical logic unit 403 was can the first digital output data signal S1 anti-phase with as this pen the second digital output data signal S2; When the 3rd control signal C3 triggered bolt-lock unit 404, the 3rd digital output data signal S3 that bolt-lock unit 404 is exported was anti-phase with this pen the second digital output data signal S2; When the first judging unit 406 is judged this transition number of times greater than N/2, the first judging unit 406 will trigger the first control signal C1 and the 4th control signal C4, and the 4th control signal C4 will trigger the second judging unit 408 the 4th control signal C4 is set as the 3rd control signal C3; And when the first judging unit 406 judged that this transition number of times is not more than N/2, bolt-lock unit 404 can not triggered by the 3rd control signal S3.In addition, the first judging unit 406 can receive one the 5th control signal C5 in addition, and according to the 5th control signal C5 and optionally activation (enabled) or anergy (disabled).When the first judging unit 406 according to the 5th control signal C5 and during anergy, the second judging unit 408 just can be used for judging that the digital data signal S of this N position sets the second control signal C2 and the 3rd control signal C3 compared to this transition number of times of the digital data signal of last N position.

In sum, the disclosed driving circuit of the present invention can be between mathematical logic unit and bolt-lock unit the data-signal transmission path reduce total transition number of times of data-signal, therefore, the disclosed driving circuit of the present invention can reduce power consumption, thermal value and electromagnetic interference (EMI) effectively.

The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims

1. A source drive circuit for a liquid crystal display panel, comprising:

A first data logic unit is used to receive at least one N-bit digital data signal and a first control signal, and selectively invert the N-bit digital data signal according to the first control signal to generate a a first digital output data signal;

A latch unit, coupled to the first data logic unit, and used to receive the first digital output data signal and a second control signal, and selectively set the outputted data according to the second control signal Whether a second digital output data signal is inverted to the first digital output data signal; and

A judging unit, coupled to the first data logic unit and the latch unit, and used for receiving the N-bit digital data signal and judging whether the N-bit digital data signal is compared with the previous N-bit digital data signal A transition count of the digital data signal, and outputting the first control signal and the second control signal according to the transition count.

2. The drive circuit according to claim 1, wherein when the first control signal triggers the first data logic unit, the first data logic unit inverts the N-bit digital data signal as the second A digital output data signal; when the second control signal triggers the latch unit, the second digital output data signal output by the latch unit is inverted from the first digital output data signal; and when the When the number of transitions is greater than N/2, the judging unit triggers the first control signal and the second control signal.

3. The driving circuit according to claim 1, wherein the first data logic unit, the latch unit and the judging unit are disposed in a source driver circuit chip applied in a liquid crystal display panel.

4. The drive circuit according to claim 1, further comprising:

a second data logic unit, coupled between the first data logic unit and the latch unit, and used to receive and output the first digital output data signal;

Wherein the second data logic unit and the latch unit are arranged in a source driver circuit chip applied in a liquid crystal display panel, and the first data logic unit and the judging unit are externally connected to the source driver circuit chip .

5. The driving circuit according to claim 1, wherein the first control signal and the second control signal are the same logic signal.

6. The driving circuit according to claim 1, wherein the first control signal and the second control signal are different logic signals.

7. A source drive circuit for a liquid crystal display panel, comprising:

A second data logic unit, coupled to the first data logic unit, for receiving the first digital output data signal and a second control signal, and selectively inverting the pen according to the second control signal the first digital output data signal to generate a second digital output data signal;

A latch unit, coupled to the second data logic unit, and used to receive the second digital output data signal and a third control signal, and selectively set the outputted data according to the third control signal Whether a third digital output data signal is inverse to the second digital output data signal;

A first judging unit, coupled to the first data logic unit, and used for receiving the N-bit digital data signal and judging whether the N-bit digital data signal is compared with the previous N-bit digital data signal A number of transitions, and outputting the first control signal and a fourth control signal according to the number of transitions; and

A second judging unit, coupled to the second data logic unit, the first judging unit and the latch unit, and used for receiving the N-bit digital data signal and the fourth control signal, and according to the first judging unit Four control signals to selectively set the fourth control signal as the third control signal or determine the number of transitions of the N-bit digital data signal compared with the previous N-bit digital data signal to set Determine the second control signal and the third control signal.

8. The drive circuit according to claim 7, wherein when the first control signal triggers the first data logic unit, the first data logic unit inverts the N-bit digital data signal as the second A digital output data signal; when the second control signal triggers the second data logic unit, the second data logic unit inverts the first digital output data signal as the second digital output data signal; when When the third control signal triggers the latch unit, the third digital output data signal output by the latch unit is in reverse phase with the second digital output data signal; when the first judging unit judges the number of transitions When greater than N/2, the first judging unit triggers the first control signal and the fourth control signal, and the fourth control signal triggers the second judging unit to set the fourth control signal as the third control signal ; and when the first judgment unit judges that the number of transitions is not greater than N/2, the latch unit will not be triggered by the third control signal.

9. The driving circuit according to claim 7, wherein the first judging unit further receives a fifth control signal, and is selectively enabled or disabled according to the fifth control signal.

10. The driving circuit according to claim 7, wherein the second data logic unit, the latch unit and the second judging unit are arranged in a source driver circuit chip applied in a liquid crystal display panel, and The first data logic unit and the first judging unit are externally connected to the source driving circuit chip.

11. The driving circuit according to claim 7, wherein the first control signal and the fourth control signal are the same logic signal.

12. The driving circuit according to claim 7, wherein the first control signal and the fourth control signal are different logic signals.

13. The driving circuit according to claim 7, wherein the second control signal and the third control signal are the same logic signal.

14. The driving circuit according to claim 7, wherein the second control signal and the third control signal are different logic signals.