CN102054753B - Manufacturing method for dual-inlay structure - Google Patents
Manufacturing method for dual-inlay structure Download PDFInfo
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Abstract
The invention provides a manufacturing method for a dual-inlay structure. The method comprises the following steps of: providing a semiconductor substrate; sequentially forming a covering layer, a medium layer, a medium antireflection layer and an isolating layer on the semiconductor substrate; forming a resist layer with a through hole pattern on the isolating layer to etch the isolating layer, the medium antireflection layer and the medium layer so as to form through holes; removing the resist layer with the through hole pattern; forming filling layers in the through holes and on the isolating layer; removing the filling layer on the isolating layer and removing a part of the filling layers in the through holes; forming resist layer with a groove pattern on the isolating layer to etch the isolating layer, the medium antireflection layer and a part of the medium layer so as to form grooves; removing the resist layer with the groove pattern; removing the left filling layers in the through holes; and removing the covering layer in the through holes; and forming metal layers in the through holes and the grooves so as to form the dual-inlay structure. By the manufacturing method, barrier defect can be prevented from forming and the yield of the product is improved.
Description
Technical field
The present invention relates to integrated circuit and make the field, particularly relate to a kind of manufacture method of dual-damascene structure.
Background technology
Current semiconductor device manufacturing technology develop rapidly, semiconductor device has had the deep-submicron structure, comprises the semiconductor element of enormous quantity in the integrated circuit.In so large-scale integrated circuit, the high-performance between the semiconductor element, highdensity connection not only interconnect in single interconnection layer, and will interconnect between multilayer.Therefore, usually provide multilayer interconnect structure, wherein a plurality of interconnection layers are stacking mutually, are used for connecting semiconductor element.The multilayer interconnect structure that forms of dual damascene (dual-damascene) technique particularly, it forms groove (trench) and through hole (via) in advance in interlayer dielectric layer, then with electric conducting material for example copper (Cu) fill described groove and through hole.
Dual-damascene technics is a kind of method that forms simultaneously the stacked on top structure of plain conductor and connector (plug), with different elements and the wire that is used for connecting each interlayer in the semiconductor wafer, and utilize the dielectric layer (inter-layer dielectrics, ILD) around it isolated with other element.The technology of dual-damascene technics focuses on the lithographic technique that the groove that metal uses is filled in etching, in the leading portion etching technics of dual-damascene technics, exist at present two kinds of methods to make the groove of dual-damascene structure, first method is to define groove on the top of dielectric layer first, utilize afterwards another resist layer to define through hole, the method is because the density of groove is quite high, so that be used for defining the surface irregularity of the resist layer of through hole, had a strong impact on the resolution of exposure imaging technique.
Another kind method is to define first the through hole that penetrates described dielectric layer fully in dielectric layer; then utilize another resist layer definition groove; before the painting erosion resistant agent layer; usually can be coated with first one deck bottom antireflective coating (Bottom Anti-Reflective Coating; BARC), to improve the resolution of exposure imaging technique.Detailed, please refer to Figure 1A to Fig. 1 G, it is the generalized section of each step corresponding construction of the manufacture method of existing dual-damascene structure.
With reference to Figure 1A, Semiconductor substrate 100 at first is provided, wherein, be formed with metal line in the Semiconductor substrate 100.For simplifying, this sentences blank structure and replaces.
With reference to Figure 1B, on Semiconductor substrate 100, form successively cover layer 110, dielectric layer 120 and medium anti-reflecting layer (Dielectric Anti-Reflective Coating, DARC) 130.
Wherein, cover layer 110 can be used for preventing that the metal line in the Semiconductor substrate 100 is diffused in the dielectric layer 120, and cover layer 110 also can prevent in the subsequent etching process simultaneously, and the metal line in the Semiconductor substrate 100 is etched.
The stacked structure that described dielectric layer 120 can be comprised of first medium layer 121, etching stop layer 122 and second medium layer 123.
The material of described medium anti-reflecting layer 130 is silicon oxynitrides, and its thickness is 1000～1500
, it can play antireflecting effect, to improve the resolution of follow-up exposure imaging technique of carrying out.
With reference to figure 1C, form the resist layer 140 with via hole image at medium anti-reflecting layer 130, and take resist layer 140 with via hole image as mask, etching medium anti-reflecting layer 130 and dielectric layer 120 form through hole 120a, and described through hole 120a exposes cover layer 110.
With reference to figure 1D, remove the resist layer with via hole image 140 shown in Fig. 1 C, expose the surface of medium anti-reflecting layer 130.
With reference to figure 1E, and in conjunction with Fig. 1 C, in through hole 120a and medium anti-reflecting layer 130 form packed layers 150.
With reference to figure 1F, and in conjunction with Fig. 1 C, remove the packed layer 150 on the medium anti-reflecting layer 130, remove simultaneously the partially filled layer 150 in the through hole 120a, and in through hole 120a, keep the packed layer 150 of a part.The thickness of the packed layer 150 that wherein, keeps in the through hole 120a should guarantee that in follow-up etching process of carrying out, cover layer 110 can not be etched and wear.
With reference to figure 1G, form bottom antireflective coating 160, the through hole 120a shown in the described bottom antireflective coating 160 blank map 1C at medium anti-reflecting layer 130.Wherein, bottom antireflective coating 160 is in order to antireflection in the follow-up photoetching process that carries out, improving photoetching resolution, but its also the nitrogen-atoms in the block media anti-reflecting layer 130 contact with the anticorrosive additive material of follow-up formation.
With reference to figure 1H, and in conjunction with Fig. 1 C, form the resist layer 170 with groove figure at bottom antireflective coating 160, and has the resist layer 170 of groove figure as mask take described, etching bottom antireflective coating 160, medium anti-reflecting layer 130 and part dielectric layer 120 form groove 120b, the position of described groove 120b is corresponding with the position of through hole 120a, and is communicated with described through hole 120a.
Yet, in actual production, find, because in above-mentioned steps, need simultaneously etching bottom antireflective coating 160, medium anti-reflecting layer 130 and dielectric layer 120, and the etch rate of described each rete is different, wherein the etch rate of bottom antireflective coating 160 is more much lower than the etch rate of medium anti-reflecting layer 130, therefore, bottom antireflective coating 160 can be filled into the surface of medium anti-reflecting layer 130 and generate attachment, this attachment can hinder the etching to medium anti-reflecting layer 130 and dielectric layer 120, and then in groove 120b, form fence defective (fence defect) 151, affected size and the profile of groove 120b.
With reference to figure 1I, and in conjunction with Fig. 1 H, remove remaining packed layer 150 in resist layer 170, bottom antireflective coating 160 and the through hole 120a with groove figure, and the cover layer 110 in the etching through hole 120a, until expose Semiconductor substrate 100.
With reference to figure 1J, and in conjunction with Figure 1A to Fig. 1 I, in through hole 120a and groove 120b, form at last metal level 180, to form dual-damascene structure.Wherein, the material of metal level 180 is preferably copper.
According to above-mentioned analysis as can be known, because institute's fence defective that produced (fencedefect) 151 in forming groove 120b process, hindered the filling of metal level 180, and form easily erose metal level 180, in addition, because the existence of fence defective 151, also can cause electric current flow obstacle between the multilayer interconnection line, and easily form the electron transfer cavity, and then affect the reliability of semiconductor device, reduce the yield of product.
In order to address the above problem, industry once attempted not forming bottom antireflective coating 160 at medium anti-reflecting layer 130, but on medium anti-reflecting layer 130, directly form the resist layer 170 with groove figure, yet, do not do in the situation of isolation there being bottom antireflective coating 160, nitrogen-atoms in the medium anti-reflecting layer 130 will react with the resist layer 170 with groove figure, form the high molecular polymer " lump " of indissoluble at the sidewall of the resist layer 170 with groove figure, also this phenomenon is called " photoresistance poisoning (resist poisoning) ", the photoresistance intoxicating phenomenon will cause groove figure defective to occur.
Summary of the invention
The invention provides a kind of manufacture method of dual-damascene structure, in the process that forms groove, produce the fence defective to solve existing manufacture method, thereby affect the reliability of semiconductor device, reduced the problem of the yield of product, and guarantee the photoresistance intoxicating phenomenon can not occur.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of dual-damascene structure, described manufacture method comprises: Semiconductor substrate is provided; On described Semiconductor substrate, form successively cover layer, dielectric layer, medium anti-reflecting layer and separator; Form the resist layer with via hole image at described separator, and take described resist layer with via hole image as mask, the described separator of etching, medium anti-reflecting layer and dielectric layer form through hole, described through hole exposes described cover layer; Remove described resist layer with via hole image; In described through hole and described separator form packed layer; Remove the packed layer on the described separator, and remove the partially filled layer in the described through hole; Form the resist layer with groove figure at described separator, and has the resist layer of groove figure as mask take described, the described separator of etching, medium anti-reflecting layer and part dielectric layer form groove, and the position of described groove is corresponding with the position of described through hole and be communicated with described through hole; Remove described resist layer with groove figure; Remove remaining packed layer in the described through hole, and remove the cover layer in the described through hole, until expose described Semiconductor substrate; In described through hole and described groove, form metal level, to form dual-damascene structure.
Optionally, described medium anti-reflecting layer comprises the first medium anti-reflecting layer and is formed at second medium anti-reflecting layer on the described first medium anti-reflecting layer.
Optionally, described first medium anti-reflecting layer is silicon oxynitride layer, and the thickness of described first medium anti-reflecting layer is 300～400
, the refractive index of described first medium anti-reflecting layer is 1.8～1.9, the molar absorption coefficient of described first medium anti-reflecting layer is 1.2～1.4.
Optionally, described second medium anti-reflecting layer is silicon oxynitride layer, and the thickness of described second medium anti-reflecting layer is 200～300
, the refractive index of described second medium anti-reflecting layer is 1.9～2.0, the molar absorption coefficient of described second medium anti-reflecting layer is 0.3～0.5.
Optionally, described separator is silicon dioxide layer, and the thickness of described separator is 30～100
Optionally, described dielectric layer comprises first medium layer, etching stop layer and the second medium layer that forms successively, and described first medium layer is silicon dioxide layer, and described etching stop layer is silicon nitride layer, and described second medium layer is silicon dioxide layer.
Optionally, described cover layer is silicon nitride layer.
Optionally, the bottom antireflective coating that formed by the organic polymer of liquid state of described packed layer.
Compared with prior art, the manufacture method of dual-damascene structure provided by the invention has been saved the step that forms bottom antireflective coating at the medium anti-reflecting layer, but on Semiconductor substrate, form successively cover layer, dielectric layer, medium anti-reflecting layer and separator, therefore, the present invention can avoid simultaneously etching bottom antireflective coating, medium anti-reflecting layer and dielectric layer, and then prevents from forming in groove the fence defective; Simultaneously, described medium anti-reflecting layer can play antireflecting effect, improve the resolution of exposure imaging technique, and the existence of described separator can be avoided described medium anti-reflecting layer and resist layer to react and produce the photoresistance intoxicating phenomenon, improve the reliability of semiconductor device, be conducive to improve the yield of product.
Description of drawings
Figure 1A to Fig. 1 J is the generalized section of each step corresponding construction of the manufacture method of existing dual-damascene structure;
The flow chart of the manufacture method of the dual-damascene structure that Fig. 2 provides for the embodiment of the invention;
The generalized section of each step corresponding construction of the manufacture method of the dual-damascene structure that Fig. 3 A to Fig. 3 I provides for the embodiment of the invention.
Embodiment
Core concept of the present invention is, a kind of manufacture method of dual-damascene structure is provided, the method has been saved the step that forms bottom antireflective coating at the medium anti-reflecting layer, but on Semiconductor substrate, form successively cover layer, dielectric layer, medium anti-reflecting layer and separator, therefore, the present invention can avoid simultaneously etching bottom antireflective coating, medium anti-reflecting layer and dielectric layer, and then prevents from forming in groove the fence defective; Simultaneously, described medium anti-reflecting layer can play antireflecting effect, improves the resolution of exposure imaging technique, and the existence of described separator can avoid described medium anti-reflecting layer and resist layer to react and generation photoresistance intoxicating phenomenon, has improved the yield of product.
Please refer to Fig. 2, the flow chart of the manufacture method of the dual-damascene structure that it provides for the embodiment of the invention, in conjunction with this figure, the method comprising the steps of:
Step S20 provides Semiconductor substrate;
Step S21 forms cover layer, dielectric layer, medium anti-reflecting layer and separator successively on described Semiconductor substrate;
Step S22 forms the resist layer with via hole image at described separator, and take described resist layer with via hole image as mask, the described separator of etching, medium anti-reflecting layer and dielectric layer form through hole, and described through hole exposes described cover layer;
Step S23 removes described resist layer with via hole image;
Step S24, in described through hole and described separator form packed layer;
Step S25 removes the packed layer on the described separator, and removes the partially filled layer in the described through hole;
Step S26, form the resist layer with groove figure at described separator, and has the resist layer of groove figure as mask take described, the described separator of etching, medium anti-reflecting layer and part dielectric layer form groove, and the position of described groove is corresponding with the position of described through hole and be communicated with described through hole;
Step S27 removes described resist layer with groove figure;
Step S28 removes remaining packed layer in the described through hole, and removes the cover layer in the described through hole, until expose described Semiconductor substrate;
Step S29 forms metal level in described through hole and described groove, to form dual-damascene structure.
Be described in more detail below in conjunction with the manufacture method of generalized section to dual-damascene structure of the present invention, the preferred embodiments of the present invention have wherein been represented, should be appreciated that those skilled in the art can revise the present invention described here, and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensively knowing for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, the confusion because they can make the present invention owing to unnecessary details.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details to realize developer's specific objective, for example according to relevant system or relevant commercial restriction, change into another embodiment by an embodiment.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-accurately ratio, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
With reference to figure 3A, Semiconductor substrate 300 at first is provided, wherein, be formed with metal line in the Semiconductor substrate 300.For simplifying, this sentences blank representation.
Because the present invention relates generally to the last part technology of semiconductor device, thus will not introduce the process that in the middle of Semiconductor substrate 300, forms semiconductor device structure, but those skilled in the art should know this.
With reference to figure 3B, on Semiconductor substrate 300, form successively cover layer 310, dielectric layer 320, medium anti-reflecting layer 330 and separator 360.
Described cover layer 310 can be used for preventing that the metal line in the Semiconductor substrate 300 is diffused in the dielectric layer 320, and cover layer 310 also can prevent in the follow-up etching process of carrying out simultaneously, and the metal line in the Semiconductor substrate 300 is etched.
In a specific embodiment of the present invention, the material of cover layer 310 is silicon nitrides.Described cover layer 310 has preferably adhesiveness with the dielectric layer 320 of follow-up formation.Certainly, the material of cover layer 310 can also be other can barrier metal the material of diffusion, for example, the carborundum of silicon oxynitride (SiON) or doping nitrogen (nitrogen dopped silicon carbite, NDC) etc.The thickness of described cover layer 310 can be 300～1000
, it can form by traditional modes such as chemical vapour deposition (CVD).
In a specific embodiment of the present invention, dielectric layer 320 comprises first medium layer 321, etching stop layer 322 and the second medium layer 323 that forms successively.
In a specific embodiment of the present invention, the material of first medium layer 321 is silicon dioxide, and the thickness of described first medium layer 321 is 1000～3000
First medium layer 321 can form by the chemical vapour deposition (CVD) mode.For example, can utilize tetraethoxysilane (TEOS) to form silica membrane as liquid source material, adopt time aumospheric pressure cvd (Sub-Atmospheric Chemical Vapor Deposition, be called for short SACVD) equipment, such as the PRODUCER chamber of company of Applied Materials.
Certainly, first medium layer 321 also can form by alternate manner, for example high-temperature thermal oxidation.And the material of first medium layer 321 also can be the silicon dioxide of doping carbon.For example, can adopt the trade mark of Material Used (Applied Materials) company is the silicon dioxide of the doping carbon of black diamond (black diamond), and the dielectric constant of the silicon dioxide of described doping carbon is lower.
In a specific embodiment of the present invention, the material of etching stop layer 322 is silicon nitrides, and wherein, the thickness of etching stop layer 322 can be 300～1000
In a specific embodiment of the present invention, the material of second medium layer 323 is silicon dioxide, and wherein, the thickness of second medium layer 323 can be 1000～3000
In a specific embodiment of the present invention, medium anti-reflecting layer 330 comprises first medium anti-reflecting layer 331 and is formed at second medium anti-reflecting layer 332 on the first medium anti-reflecting layer 331.
Preferably, the material of first medium anti-reflecting layer 331 and second medium anti-reflecting layer 332 all is silicon oxynitrides.But the refractive index (N) of described first medium anti-reflecting layer 331 and second medium anti-reflecting layer 332 and molar absorption coefficient (k) but can be not identical.
Better, the refractive index of first medium anti-reflecting layer 331 is 1.8～1.9, the molar absorption coefficient of first medium anti-reflecting layer 331 is 1.2～1.4, and the refractive index of second medium anti-reflecting layer 332 is 1.9～2.0, and the molar absorption coefficient of second medium anti-reflecting layer 332 is 0.3～0.5.
Wherein, the thickness of described first medium anti-reflecting layer 331 is 300～400
, the thickness of described second medium anti-reflecting layer 332 is 200～300
Find through the present inventor's long-term experiment demonstration, when the thickness of first medium anti-reflecting layer 331 is 380
, the refractive index of first medium anti-reflecting layer 331 is 1.8667, molar absorption coefficient is 1.2471, and the thickness of second medium anti-reflecting layer 332 is 240
, the refractive index of second medium anti-reflecting layer 332 is 1.9123, molar absorption coefficient is 0.4059 o'clock, the anti-reflection effect of described medium anti-reflecting layer 330 is best, can obtain ideal resolution in the exposure imaging technical process.
In a specific embodiment of the present invention, the material of separator 360 is silicon dioxide, and described separator 360 can form by modes such as chemical vapour deposition (CVD)s.Wherein, the thickness of separator 360 can be 30～100
Because the thinner thickness of separator 360, can not affect the effect that medium anti-reflecting layer 330 plays antireflection, and described separator 360 can stop nitrogen-atoms in the medium anti-reflecting layer 330 and the resist layer of follow-up formation to react, avoid forming at the sidewall of resist layer the high molecular polymer " lump " of indissoluble, guarantee the photoresistance intoxicating phenomenon can not occur, improved the yield of product.
With reference to figure 3C, utilize existing photoetching development technology, form the resist layer 340 with via hole image at separator 360.Then, take described resist layer 340 with via hole image as mask, etching separator 360, medium anti-reflecting layer 330 and dielectric layer 320, to form through hole 320a, described through hole 320a exposes cover layer 310.
In a specific embodiment of the present invention, what adopt when etching separator 360, medium anti-reflecting layer 330 and dielectric layer 320 is dry etching, and etching gas can comprise carbon tetrafluoride, fluoroform and argon gas.Certainly, the present invention does not limit concrete etching temperature and etching gas flow, and those skilled in the art can obtain empirical value by test.
With reference to figure 3D, can utilize the oxygen plasma cineration technics to remove the resist layer with via hole image 340 shown in Fig. 3 C, to expose the surface of separator 360.
In another specific embodiment of the present invention, utilize the oxygen plasma cineration technics to remove after the step of described resist layer 340 with via hole image, the step that can also comprise the described Semiconductor substrate 300 of wet-cleaned, described wet clean process can be removed residual photoresistance, and removes for example various organic polymers of the etching gas of separator 360 remained on surface after the etching and other residue that may exist.
With reference to figure 3E, in the through hole 320a shown in Fig. 3 D and separator 360 form packed layers 350, the bottom antireflective coating that described packed layer 350 can be comprised of the organic polymer of liquid state.
With reference to figure 3F, remove the packed layer 350 on the separator 360, remove simultaneously the partially filled layer 350 in the through hole 320a shown in the 3D, and in through hole 320a, keep the packed layer 350 of a part.The thickness of the packed layer 350 that keeps in the described through hole 320a should guarantee that in follow-up etching process of carrying out, cover layer 310 can not be etched and wear.
With reference to figure 3G, and in conjunction with Fig. 3 D to Fig. 3 F, utilize existing photoetching development technology, form the resist layer 370 with groove figure at separator 360, and take described resist layer 370 with groove figure as mask, etching separator 360, medium anti-reflecting layer 330 and part dielectric layer 320 form groove 320b, and the position of described groove 320b is corresponding with the position of through hole 320a, and be communicated with through hole 320a, and the width of groove 320b is greater than the width of through hole 320a.
Detailed, has the resist layer 370 of groove figure as mask take described, when etching separator 360, medium anti-reflecting layer 330 and part dielectric layer 320, with etching stop layer 322 as etch stop layer, that is to say, etching separator 360, medium anti-reflecting layer 330, second medium layer 323 are until after exposing etching stop layer 322, namely stop etching.
Because the manufacture method of the dual-damascene structure that the embodiment of the invention provides has been saved the step that forms bottom antireflective coating at medium anti-reflecting layer 330, but on Semiconductor substrate 300, form successively cover layer 310, dielectric layer 320, medium anti-reflecting layer 330 and separator 360, therefore, the embodiment of the invention can be avoided simultaneously etching bottom antireflective coating and other rete, and then prevents from forming in groove 320b the fence defective.
Simultaneously, medium anti-reflecting layer 330 can play better antireflecting effect, improves the resolution of exposure imaging technique, and the existence of separator 360, can avoid medium anti-reflecting layer 330 to produce the photoresistance intoxicating phenomenon with the resist layer reaction, improve the reliability of semiconductor device.
With reference to figure 3H, and in conjunction with Fig. 3 A to Fig. 3 G, remove the resist layer 370 with groove figure, and remaining packed layer 350 in the through hole 320a, and the cover layer 310 in the etching through hole 320a, until expose Semiconductor substrate 300.
With reference to figure 3I, and in conjunction with Fig. 3 A to Fig. 3 G, in through hole 320a and described groove 320b, form at last metal level 380, to form dual-damascene structure.
Preferably, the material of metal level 380 is copper.Compare with aluminum interconnecting, the advantage of copper interconnecting line is that its resistivity is lower, and conductivity is better, by its connecting lead wire of making can keep on an equal basis in addition more do littlely in the situation of heavy current bearing capacity, more intensive.In addition, copper interconnecting line also has larger advantage than aluminum interconnecting at aspects such as electromigration, RC delay, reliability and life-spans.
In sum, the invention provides a kind of manufacture method of dual-damascene structure, the method comprises: Semiconductor substrate is provided; On Semiconductor substrate, form successively cover layer, dielectric layer, medium anti-reflecting layer and separator; Form the resist layer with via hole image at separator, the described separator of etching, medium anti-reflecting layer and dielectric layer form through hole; Removal has the resist layer of via hole image; In through hole and separator form packed layer; Remove the packed layer on the separator, and remove the partially filled layer in the described through hole; Form the resist layer with groove figure at separator, etching separator, medium anti-reflecting layer and part dielectric layer form groove; Removal has the resist layer of groove figure; Remove remaining packed layer in the through hole, and remove the cover layer in the through hole; In through hole and groove, form metal level, to form dual-damascene structure.This manufacture method has been saved the step that forms bottom antireflective coating at the medium anti-reflecting layer, but on Semiconductor substrate, form successively cover layer, dielectric layer, medium anti-reflecting layer and separator, therefore, the present invention can avoid simultaneously etching bottom antireflective coating, medium anti-reflecting layer and dielectric layer, and then prevents from forming in groove the fence defective; Simultaneously, described medium anti-reflecting layer can play antireflecting effect, improves the resolution of exposure imaging technique, and the existence of described separator can avoid described medium anti-reflecting layer and resist layer to react and generation photoresistance intoxicating phenomenon, has improved the yield of product.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (18)
1. the manufacture method of a dual-damascene structure comprises:
Semiconductor substrate is provided;
On described Semiconductor substrate, form successively cover layer, dielectric layer, medium anti-reflecting layer and separator;
Form the resist layer with via hole image at described separator, and take described resist layer with via hole image as mask, the described separator of etching, medium anti-reflecting layer and dielectric layer form through hole, described through hole exposes described cover layer;
Remove described resist layer with via hole image;
In described through hole and described separator form packed layer;
Remove the packed layer on the described separator, and remove the partially filled layer in the described through hole;
Form the resist layer with groove figure at described separator, and has the resist layer of groove figure as mask take described, the described separator of etching, medium anti-reflecting layer and part dielectric layer form groove, and the position of described groove is corresponding with the position of described through hole and be communicated with described through hole;
Remove described resist layer with groove figure;
Remove remaining packed layer in the described through hole, and remove the cover layer in the described through hole, until expose described Semiconductor substrate;
In described through hole and described groove, form metal level, to form dual-damascene structure.
2. the manufacture method of dual-damascene structure as claimed in claim 1 is characterized in that, described medium anti-reflecting layer comprises the first medium anti-reflecting layer and is formed at second medium anti-reflecting layer on the described first medium anti-reflecting layer.
3. the manufacture method of dual-damascene structure as claimed in claim 2 is characterized in that, described first medium anti-reflecting layer is silicon oxynitride layer.
4. the manufacture method of dual-damascene structure as claimed in claim 3 is characterized in that, the thickness of described first medium anti-reflecting layer is 300～400
5. the manufacture method of dual-damascene structure as claimed in claim 4 is characterized in that, the refractive index of described first medium anti-reflecting layer is 1.8～1.9.
6. the manufacture method of dual-damascene structure as claimed in claim 5 is characterized in that, the molar absorption coefficient of described first medium anti-reflecting layer is 1.2～1.4.
7. the manufacture method of dual-damascene structure as claimed in claim 6 is characterized in that, described second medium anti-reflecting layer is silicon oxynitride layer.
8. the manufacture method of dual-damascene structure as claimed in claim 7 is characterized in that, the thickness of described second medium anti-reflecting layer is 200～300
9. the manufacture method of dual-damascene structure as claimed in claim 8 is characterized in that, the refractive index of described second medium anti-reflecting layer is 1.9～2.0.
10. the manufacture method of dual-damascene structure as claimed in claim 9 is characterized in that, the molar absorption coefficient of described second medium anti-reflecting layer is 0.3～0.5.
11. the manufacture method such as claim 2 or 10 described dual-damascene structures is characterized in that described separator is silicon dioxide layer.
12. the manufacture method of dual-damascene structure as claimed in claim 11 is characterized in that, the thickness of described separator is 30～100
13. the manufacture method of dual-damascene structure as claimed in claim 1 is characterized in that, described dielectric layer comprises first medium layer, etching stop layer and the second medium layer that forms successively.
14. the manufacture method of dual-damascene structure as claimed in claim 13 is characterized in that, described first medium layer is silicon dioxide layer.
15. the manufacture method of dual-damascene structure as claimed in claim 13 is characterized in that, described etching stop layer is silicon nitride layer.
16. the manufacture method of dual-damascene structure as claimed in claim 13 is characterized in that, described second medium layer is silicon dioxide layer.
17. the manufacture method of dual-damascene structure as claimed in claim 1 is characterized in that, described cover layer is silicon nitride layer.
18. the manufacture method of dual-damascene structure as claimed in claim 1 is characterized in that, the bottom antireflective coating that described packed layer is comprised of the organic polymer of liquid state.
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| CN103050433A (en) * | 2011-10-17 | 2013-04-17 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor contact hole structure and manufacturing method thereof |
| CN105575989B (en) * | 2016-03-24 | 2019-03-12 | 上海华力微电子有限公司 | Method for blocking metal contamination during filling of CMOS image sensor HDP shallow trenches |
| CN112071804A (en) * | 2020-09-17 | 2020-12-11 | 长江存储科技有限责任公司 | A kind of semiconductor device and its manufacturing method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6835652B2 (en) * | 2002-04-17 | 2004-12-28 | Nec Electronics Corporation | Method of fabricating patterns with a dual damascene process |
| US7030031B2 (en) * | 2003-06-24 | 2006-04-18 | International Business Machines Corporation | Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material |
| CN101079408A (en) * | 2006-05-22 | 2007-11-28 | 中芯国际集成电路制造(上海)有限公司 | Double-inlay structure and its making method |
| CN101106101A (en) * | 2006-07-10 | 2008-01-16 | 联华电子股份有限公司 | Single-damascene structure, dual-damascene structure and method for forming opening of single-damascene structure and dual-damascene structure |
| CN101207018A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming anti-reflecting layer and method for manufacturing dual mosaic structure |
| CN101295669A (en) * | 2007-04-29 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | Production method of double mosaic structure |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6835652B2 (en) * | 2002-04-17 | 2004-12-28 | Nec Electronics Corporation | Method of fabricating patterns with a dual damascene process |
| US7030031B2 (en) * | 2003-06-24 | 2006-04-18 | International Business Machines Corporation | Method for forming damascene structure utilizing planarizing material coupled with diffusion barrier material |
| CN101079408A (en) * | 2006-05-22 | 2007-11-28 | 中芯国际集成电路制造(上海)有限公司 | Double-inlay structure and its making method |
| CN101106101A (en) * | 2006-07-10 | 2008-01-16 | 联华电子股份有限公司 | Single-damascene structure, dual-damascene structure and method for forming opening of single-damascene structure and dual-damascene structure |
| CN101207018A (en) * | 2006-12-22 | 2008-06-25 | 中芯国际集成电路制造(上海)有限公司 | Method for forming anti-reflecting layer and method for manufacturing dual mosaic structure |
| CN101295669A (en) * | 2007-04-29 | 2008-10-29 | 中芯国际集成电路制造(上海)有限公司 | Production method of double mosaic structure |
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