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CN102054821B - Package structure with inner shield and manufacturing method thereof - Google Patents

Package structure with inner shield and manufacturing method thereof Download PDF

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Publication number
CN102054821B
CN102054821B CN 200910211804 CN200910211804A CN102054821B CN 102054821 B CN102054821 B CN 102054821B CN 200910211804 CN200910211804 CN 200910211804 CN 200910211804 A CN200910211804 A CN 200910211804A CN 102054821 B CN102054821 B CN 102054821B
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substrate
solder
electronic components
inner shield
layer
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CN102054821A (en
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廖国宪
陈建成
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/03Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
    • H01L25/0655Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10D, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00 the devices being arranged next to each other
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

The invention relates to a packaging structure with an inner shielding body and a manufacturing method thereof. The package structure includes a substrate, a plurality of electronic components, a molding compound, an inner shield and a shielding layer. The electronic components are located on the substrate. The sealing colloid is positioned on one surface of the substrate, covers the electronic components and comprises at least one groove. The groove penetrates through the upper surface and the lower surface of the sealing colloid and is positioned between the electronic components, and a distance is reserved between a short edge of the groove and one side surface of the sealing colloid. The inner shield is located in the groove and electrically connected to the substrate. The shielding layer covers the sealing colloid and one side surface of the substrate and is electrically connected with the substrate and the inner shielding body. Therefore, the inner shielding body can enable the electronic components to have low electromagnetic interference and high electromagnetic tolerance.

Description

具有内屏蔽体的封装结构及其制造方法Package structure with inner shield and manufacturing method thereof

技术领域 technical field

本发明是关于一种封装结构及其制造方法,详言之,是关于一种具有内屏蔽体的封装结构及其制造方法。The present invention relates to a packaging structure and a manufacturing method thereof, in particular, to a packaging structure with an inner shield and a manufacturing method thereof.

背景技术 Background technique

参考图1,显示已知封装结构的剖面示意图。该已知封装结构1具有一基板11、数个电子组件12、一封胶体13及一遮蔽层14。该等电子组件12位于该基板11上。该封胶体13包覆该基板的一表面111及该等电子组件12。该遮蔽层14覆盖该封胶体13及该基板11的一侧面112,且电性连接至该基板11。Referring to FIG. 1 , a schematic cross-sectional view of a known package structure is shown. The known package structure 1 has a substrate 11 , several electronic components 12 , an encapsulant 13 and a shielding layer 14 . The electronic components 12 are located on the substrate 11 . The encapsulant 13 covers a surface 111 of the substrate and the electronic components 12 . The shielding layer 14 covers the encapsulant 13 and a side surface 112 of the substrate 11 , and is electrically connected to the substrate 11 .

该已知封装结构1的缺点如下。该基板11及该遮蔽层14定义出一容置空间15,该等电子组件12都位于该容置空间15内,彼此之间没有任何屏蔽,故该等电子组件12之间具有高电磁干扰(Electromagnetic Interference,EMI)及低电磁容忍性(Electromagnetic Compatibility,EMC)。The disadvantages of this known package structure 1 are as follows. The substrate 11 and the shielding layer 14 define an accommodating space 15, and the electronic components 12 are located in the accommodating space 15 without any shielding between each other, so there is high electromagnetic interference between the electronic components 12 ( Electromagnetic Interference, EMI) and low electromagnetic tolerance (Electromagnetic Compatibility, EMC).

因此,有必要提供一种具有内屏蔽体的封装结构及其制造方法,以解决上述问题。Therefore, it is necessary to provide a packaging structure with an inner shield and a manufacturing method thereof to solve the above problems.

发明内容 Contents of the invention

本发明提供一种具有内屏蔽体的封装结构。该封装结构包括一基板、数个电子组件、一封胶体、一内屏蔽体及一遮蔽层。该基板包括一接地金属层及至少一接地焊垫。该基板具有一第一表面及一侧面。该接地金属层位于该基板内,且显露于该基板的侧面。该接地焊垫位于该基板内,显露于该基板的第一表面,且电性连接至该接地金属层。该等电子组件位于该基板的第一表面。该封胶体位于该基板的第一表面上,且包覆该等电子组件,且包括至少一沟槽、一上表面、一下表面及一侧面。该沟槽贯穿该封胶体的上表面及下表面,且位于该等电子组件之间,且该沟槽具有一长边及一短边,该短边与该封胶体的侧面之间具有一间距。该内屏蔽体位于该沟槽内,且电性连接至该接地焊垫。该遮蔽层覆盖该封胶体及该基板的侧面,且电性连接该接地金属层及该内屏蔽体。The invention provides a package structure with an inner shield. The packaging structure includes a base plate, several electronic components, sealing colloid, an inner shielding body and a shielding layer. The substrate includes a ground metal layer and at least one ground pad. The substrate has a first surface and a side surface. The ground metal layer is located in the substrate and exposed on the side of the substrate. The ground pad is located in the substrate, exposed on the first surface of the substrate, and electrically connected to the ground metal layer. The electronic components are located on the first surface of the substrate. The sealing body is located on the first surface of the substrate, covers the electronic components, and includes at least one groove, an upper surface, a lower surface and a side surface. The groove runs through the upper surface and the lower surface of the sealing body, and is located between the electronic components, and the groove has a long side and a short side, and there is a distance between the short side and the side surface of the sealing body . The inner shield is located in the trench and electrically connected to the ground pad. The shielding layer covers the sealing body and the side surfaces of the substrate, and is electrically connected to the ground metal layer and the inner shielding body.

本发明提供一种具有内屏蔽体的封装结构。该封装结构包括一基板、数个电子组件、一封胶体、一内屏蔽体及一遮蔽层。该基板包括一接地金属层及至少一接地焊垫。该基板具有一第一表面及一侧面。该接地金属层位于该基板内,且显露于该基板的侧面。该接地焊垫位于该基板内,显露于该基板的第一表面,且电性连接至该接地金属层。该等电子组件位于该基板的第一表面。该封胶体位于该基板的第一表面上,且包覆该等电子组件,且包括至少一沟槽、一上表面、一下表面及一侧面。该沟槽贯穿该封胶体的上表面及下表面,且位于该等电子组件之间。该内屏蔽体位于该沟槽内,且电性连接至该接地焊垫。该遮蔽层覆盖该封胶体及该基板的侧面,且电性连接该接地金属层及该内屏蔽体,其中该内屏蔽体的厚度与该遮蔽层的厚度的比值大于25。The invention provides a package structure with an inner shield. The packaging structure includes a base plate, several electronic components, sealing colloid, an inner shielding body and a shielding layer. The substrate includes a ground metal layer and at least one ground pad. The substrate has a first surface and a side surface. The ground metal layer is located in the substrate and exposed on the side of the substrate. The ground pad is located in the substrate, exposed on the first surface of the substrate, and electrically connected to the ground metal layer. The electronic components are located on the first surface of the substrate. The sealing body is located on the first surface of the substrate, covers the electronic components, and includes at least one groove, an upper surface, a lower surface and a side surface. The groove runs through the upper surface and the lower surface of the sealing body, and is located between the electronic components. The inner shield is located in the trench and electrically connected to the ground pad. The shielding layer covers the sealing body and the side surfaces of the substrate, and is electrically connected to the ground metal layer and the inner shielding body, wherein the ratio of the thickness of the inner shielding body to the thickness of the shielding layer is greater than 25.

本发明更提供一种具有内屏蔽体的封装结构的制造方法。该制造方法包括以下步骤:提供一基板及数个电子组件,该基板包括一接地金属层及至少一接地焊垫,该基板具有一第一表面及一侧面,该接地金属层位于该基板内,且显露于该基板的侧面,该接地焊垫位于该基板内,显露于该基板的第一表面,且电性连接至该接地金属层,该等电子组件位于该基板的第一表面;形成一封胶体于该基板的第一表面上,以包覆该等电子组件,该封胶体包括一上表面、一下表面及一侧面;移除部分该封胶体,以形成至少一沟槽,该沟槽贯穿该封胶体的上表面及下表面,且位于该等电子组件之间;填满一内屏蔽体于该沟槽内,该内屏蔽体电性连接至该接地焊垫;切割该基板及该封胶体;及形成一遮蔽层,以覆盖该封胶体及该基板的侧面,且电性连接该接地金属层及该内屏蔽体。The invention further provides a manufacturing method of the packaging structure with the inner shield. The manufacturing method includes the following steps: providing a substrate and several electronic components, the substrate includes a ground metal layer and at least one ground pad, the substrate has a first surface and a side surface, the ground metal layer is located in the substrate, And exposed on the side of the substrate, the ground pad is located in the substrate, exposed on the first surface of the substrate, and electrically connected to the ground metal layer, the electronic components are located on the first surface of the substrate; forming a The sealing body is on the first surface of the substrate to cover the electronic components, the sealing body includes an upper surface, a lower surface and a side surface; part of the sealing body is removed to form at least one groove, the groove penetrating through the upper surface and the lower surface of the sealing body, and located between the electronic components; filling an inner shield in the groove, and the inner shield is electrically connected to the grounding pad; cutting the substrate and the and forming a shielding layer to cover the side surfaces of the sealing body and the substrate, and electrically connect the grounding metal layer and the inner shielding body.

藉此,该内屏蔽体可使该等电子组件之间具有低电磁干扰及高电磁容忍性。同时,可将各种功能的电子组件整合于本发明的封装结构内,以减少最终系统产品的组成组件数,且缩小产品尺寸。In this way, the inner shield can make the electronic components have low electromagnetic interference and high electromagnetic tolerance. At the same time, electronic components with various functions can be integrated into the packaging structure of the present invention, so as to reduce the number of components in the final system product and reduce the size of the product.

附图说明Description of drawings

图1显示已知封装结构的剖面示意图;Figure 1 shows a schematic cross-sectional view of a known package structure;

图2至图11显示本发明具有内屏蔽体的封装结构的第一实施例的制造方法的示意图;及2 to 11 are schematic diagrams showing the manufacturing method of the first embodiment of the packaging structure with the inner shielding body of the present invention; and

图12至图24显示本发明具有内屏蔽体的封装结构的第二实施例的制造方法的示意图。12 to 24 are schematic diagrams showing the manufacturing method of the second embodiment of the packaging structure with an inner shield according to the present invention.

具体实施方式 Detailed ways

参考图2至图11,显示本发明具有内屏蔽体的封装结构的第一实施例的制造方法的示意图。参考图2,提供一基板21及数个电子组件(Electrical Element)22。该基板21包括一接地金属层212、至少一接地焊垫214、一上接地金属区域215及一防焊层213。该基板21具有一第一表面2111及一侧面2112。该接地金属层212位于该基板21内,且显露于该基板21的侧面2112。该接地焊垫214位于该基板21内,显露于该基板21的第一表面2111,且电性连接至该接地金属层212。Referring to FIG. 2 to FIG. 11 , there are schematic diagrams showing the manufacturing method of the first embodiment of the packaging structure with the inner shield according to the present invention. Referring to FIG. 2 , a substrate 21 and several electronic components (Electrical Element) 22 are provided. The substrate 21 includes a ground metal layer 212 , at least one ground pad 214 , an upper ground metal region 215 and a solder resist layer 213 . The substrate 21 has a first surface 2111 and a side surface 2112 . The ground metal layer 212 is located in the substrate 21 and exposed on the side surface 2112 of the substrate 21 . The ground pad 214 is located in the substrate 21 , exposed on the first surface 2111 of the substrate 21 , and electrically connected to the ground metal layer 212 .

该上接地金属区域215位于该基板21内,且显露于该基板21的第一表面2111。在本实施例中,该上接地金属区域215电性连接至该接地金属层212。然而,在其它应用中,该上接地金属区域215位于该接地金属层212。该防焊层213位于该基板21的第一表面2111,且具有至少一开口2131,显露部分该上接地金属区域215,以形成该接地焊垫214。在本实施例中,该接地焊垫214的宽度W1为300μm。该等电子组件22位于该基板21的第一表面2111。该等电子组件22为主动组件或被动组件,详言之,该等电子组件22可为数字电路、模拟电路或以铜箔形成于该基板21的第一表面2111的主动组件。The upper ground metal region 215 is located in the substrate 21 and exposed on the first surface 2111 of the substrate 21 . In this embodiment, the upper ground metal region 215 is electrically connected to the ground metal layer 212 . However, in other applications, the upper ground metal region 215 is located on the ground metal layer 212 . The solder resist layer 213 is located on the first surface 2111 of the substrate 21 and has at least one opening 2131 exposing a portion of the upper ground metal region 215 to form the ground pad 214 . In this embodiment, the width W 1 of the ground pad 214 is 300 μm. The electronic components 22 are located on the first surface 2111 of the substrate 21 . The electronic components 22 are active components or passive components. Specifically, the electronic components 22 can be digital circuits, analog circuits or active components formed on the first surface 2111 of the substrate 21 with copper foil.

参考图3,形成一封胶体23于该基板21的第一表面2111上,以包覆该等电子组件22,该封胶体23包括一上表面232、一下表面234及一侧面233。参考图4,移除部分该封胶体23,以形成至少一沟槽231,该沟槽231贯穿该封胶体23的上表面232及下表面234,且位于该等电子组件22之间。在本实施例中,该沟槽231显露部分该接地焊垫214。该沟槽231的宽度W2小于该接地焊垫214的宽度W1,较佳地,该沟槽231的宽度W2为50μm至200μm,更佳地,该沟槽231的宽度W2为100μm至200μm。参考图5至图7,其中,图5为图4的俯视图,图6为图4的立体图,图7为图6的局部放大图,该沟槽231的俯视形状为直线,且该沟槽231具有一长边2313及一短边2312,该短边2312及该长边2313相交。该短边2312的长度等于该沟槽231的宽度W2,该长边2313的长度L1略小于该基板21的长度L2,且大于该短边2312的长度。该短边2312与该封胶体23的侧面233之间具有一间距,亦即,该沟槽231未贯穿该封胶体23的二侧面233。在本实施例中,利用激光方法移除部分该封胶体23,以形成该沟槽231,该沟槽231的剖面形状为倒梯形,且该沟槽231的一斜面与一垂直线(图中未示)的夹角的角度为1.8°至9°。然而,在其它实施例中,该沟槽231的俯视形状可为弯曲的线段,而非直线,如图8所示。Referring to FIG. 3 , a sealing body 23 is formed on the first surface 2111 of the substrate 21 to cover the electronic components 22 . The sealing body 23 includes an upper surface 232 , a lower surface 234 and a side surface 233 . Referring to FIG. 4 , part of the encapsulant 23 is removed to form at least one groove 231 , the groove 231 runs through the upper surface 232 and the lower surface 234 of the encapsulant 23 and is located between the electronic components 22 . In this embodiment, the trench 231 exposes a portion of the ground pad 214 . The width W 2 of the groove 231 is smaller than the width W 1 of the ground pad 214 , preferably, the width W 2 of the groove 231 is 50 μm to 200 μm, more preferably, the width W 2 of the groove 231 is 100 μm to 200 μm. 5 to 7, wherein, FIG. 5 is a top view of FIG. 4, FIG. 6 is a perspective view of FIG. 4, and FIG. 7 is a partially enlarged view of FIG. It has a long side 2313 and a short side 2312, and the short side 2312 and the long side 2313 intersect. The length of the short side 2312 is equal to the width W 2 of the trench 231 , and the length L 1 of the long side 2313 is slightly smaller than the length L 2 of the substrate 21 and greater than the length of the short side 2312 . There is a distance between the short side 2312 and the side surface 233 of the sealing body 23 , that is, the groove 231 does not penetrate through the two side surfaces 233 of the sealing body 23 . In this embodiment, a part of the sealant 23 is removed by a laser method to form the groove 231. Not shown) the included angle is 1.8° to 9°. However, in other embodiments, the top view shape of the groove 231 may be a curved line segment instead of a straight line, as shown in FIG. 8 .

参考图9,填满一内屏蔽体24于该沟槽231内,该内屏蔽体24电性连接至该接地焊垫214。在本实施例中,利用网印方式(Screen Printing)方法形成该内屏蔽体24,该内屏蔽体24直接接触该接地焊垫214,且该内屏蔽体24的材质为导电材料,例如焊料(Solder)或导电胶(Conductive Epoxy)。该内屏蔽体24的宽度W2等同于该沟槽231的宽度W2,亦即,该内屏蔽体24的宽度W2为至少50μm。根据电磁屏蔽原理,频率愈低的信号,其波长愈长,则该内屏蔽体24所需的宽度W2愈大。举例而言,频率为1MHz以上的信号,该内屏蔽体24的宽度W2应为至少50μm。藉此,在本发明中,该内屏蔽体24为至少50μm,而可应用于频率为1MHz以上的信号。Referring to FIG. 9 , an inner shield 24 is filled in the groove 231 , and the inner shield 24 is electrically connected to the ground pad 214 . In this embodiment, the inner shield 24 is formed by using a screen printing method, the inner shield 24 directly contacts the ground pad 214, and the material of the inner shield 24 is a conductive material, such as solder ( Solder) or Conductive Epoxy. The width W 2 of the inner shield 24 is equal to the width W 2 of the groove 231 , that is, the width W 2 of the inner shield 24 is at least 50 μm. According to the principle of electromagnetic shielding, the lower the frequency of the signal, the longer the wavelength, and the larger the width W 2 required by the inner shield 24 is. For example, for signals with a frequency above 1 MHz, the width W 2 of the inner shield 24 should be at least 50 μm. Therefore, in the present invention, the inner shield 24 is at least 50 μm, and can be applied to signals with a frequency above 1 MHz.

参考图10,沿至少一切割线L切割该基板21及该封胶体23。参考图11,形成一遮蔽层(Conformal Shield)25,以覆盖该封胶体23及该基板21的侧面2112,且电性连接该接地金属层212及该内屏蔽体24。因此,在本发明中,该屏蔽体24及该遮蔽层25并非同时电镀而成。在本实施例中,利用溅镀方法形成该遮蔽层25,该遮蔽层25的厚度为1μm至2μm,该内屏蔽体24的厚度与该遮蔽层25的厚度的比值大于25,且该遮蔽层25的材质为镍。然而,在其它应用中,可利用电镀方法形成该遮蔽层25,该遮蔽层25的材质可为铜,且更可利用溅镀方法形成一抗氧化层(图中未示),以覆盖该遮蔽层25。较佳地,该抗氧化层(图中未示)的厚度为40nm,且其材质为不锈钢。藉此,该抗氧化层(图中未示)可避免该遮蔽层25氧化,而提升产品良率。Referring to FIG. 10 , the substrate 21 and the encapsulant 23 are cut along at least one cutting line L. Referring to FIG. 11, a shielding layer (Conformal Shield) 25 is formed to cover the sealing body 23 and the side surface 2112 of the substrate 21, and electrically connect the grounding metal layer 212 and the inner shielding body 24. Therefore, in the present invention, the shielding body 24 and the shielding layer 25 are not electroplated at the same time. In this embodiment, the shielding layer 25 is formed by sputtering, the thickness of the shielding layer 25 is 1 μm to 2 μm, the ratio of the thickness of the inner shield 24 to the thickness of the shielding layer 25 is greater than 25, and the shielding layer 25 is made of nickel. However, in other applications, the masking layer 25 can be formed by electroplating, the material of the masking layer 25 can be copper, and an anti-oxidation layer (not shown) can be formed by sputtering to cover the masking layer 25. Layer 25. Preferably, the anti-oxidation layer (not shown in the figure) has a thickness of 40nm and is made of stainless steel. In this way, the anti-oxidation layer (not shown in the figure) can prevent the shielding layer 25 from being oxidized, thereby improving product yield.

藉此,该内屏蔽体24可隔离该等电子组件22,故该屏蔽体24可使该等电子组件22之间具有低电磁干扰(Electromagnetic Interference,EMI)及高电磁容忍性(Electromagnetic Compatibility,EMC)。同时,可将各种功能的电子组件22整合于该封装结构2内,以减少最终系统产品的组成组件数,且缩小产品尺寸。Thereby, the inner shield 24 can isolate the electronic components 22, so the shield 24 can make the electronic components 22 have low electromagnetic interference (Electromagnetic Interference, EMI) and high electromagnetic tolerance (Electromagnetic Compatibility, EMC). ). At the same time, electronic components 22 with various functions can be integrated into the packaging structure 2 to reduce the number of components in the final system product and reduce the size of the product.

再参考图11,显示本发明具有内屏蔽体的封装结构的第一实施例的剖面示意图。该具有内屏蔽体的封装结构2包括一基板21、数个电子组件22、一封胶体23、一内屏蔽体24及一遮蔽层25。该基板21包括一接地金属层212、至少一接地焊垫214、一上接地金属区域215及一防焊层213。该基板21具有一第一表面2111及一侧面2112。该接地金属层212位于该基板21内,且显露于该基板21的侧面2112。该接地焊垫214位于该基板21内,显露于该基板21的第一表面2111,且电性连接至该接地金属层212。Referring again to FIG. 11 , it shows a schematic cross-sectional view of the first embodiment of the package structure with the inner shield of the present invention. The package structure 2 with an inner shield includes a substrate 21 , several electronic components 22 , an encapsulant 23 , an inner shield 24 and a shielding layer 25 . The substrate 21 includes a ground metal layer 212 , at least one ground pad 214 , an upper ground metal region 215 and a solder resist layer 213 . The substrate 21 has a first surface 2111 and a side surface 2112 . The ground metal layer 212 is located in the substrate 21 and exposed on the side surface 2112 of the substrate 21 . The ground pad 214 is located in the substrate 21 , exposed on the first surface 2111 of the substrate 21 , and electrically connected to the ground metal layer 212 .

该上接地金属区域215位于该基板21内,且显露于该基板21的第一表面2111。在本实施例中,该上接地金属区域215电性连接至该接地金属层212。然而,在其它应用中,该上接地金属区域215位于该接地金属层212。该防焊层213位于该基板21的第一表面2111,且具有至少一开口2131,显露部分该上接地金属区域215,以形成该接地焊垫214。在本实施例中,该接地焊垫214的宽度W1为300μm。The upper ground metal region 215 is located in the substrate 21 and exposed on the first surface 2111 of the substrate 21 . In this embodiment, the upper ground metal region 215 is electrically connected to the ground metal layer 212 . However, in other applications, the upper ground metal region 215 is located on the ground metal layer 212 . The solder resist layer 213 is located on the first surface 2111 of the substrate 21 and has at least one opening 2131 exposing a portion of the upper ground metal region 215 to form the ground pad 214 . In this embodiment, the width W 1 of the ground pad 214 is 300 μm.

该等电子组件22位于该基板21的第一表面2111。在本实施例中,该等电子组件22为主动组件或被动组件,详言之,该等电子组件22可为数字电路、模拟电路或以铜箔形成于该基板21的第一表面2111的主动组件。该封胶体23位于该基板21的第一表面2111上,且包覆该等电子组件22,且包括至少一沟槽231、一上表面232、一下表面234及一侧面233。该沟槽231贯穿该封胶体23的上表面232及下表面234,位于该等电子组件22之间。在本实施例中,该沟槽231具有一长边2313及一短边2312,该短边2312与该封胶体23的侧面233之间具有一间距,如图5至图7所示。The electronic components 22 are located on the first surface 2111 of the substrate 21 . In this embodiment, the electronic components 22 are active components or passive components. Specifically, the electronic components 22 can be digital circuits, analog circuits or active components formed on the first surface 2111 of the substrate 21 with copper foil. components. The encapsulant 23 is located on the first surface 2111 of the substrate 21 and covers the electronic components 22 , and includes at least one groove 231 , an upper surface 232 , a lower surface 234 and a side surface 233 . The groove 231 runs through the upper surface 232 and the lower surface 234 of the encapsulant 23 and is located between the electronic components 22 . In this embodiment, the groove 231 has a long side 2313 and a short side 2312 , and there is a distance between the short side 2312 and the side surface 233 of the sealing body 23 , as shown in FIGS. 5 to 7 .

该内屏蔽体24位于该沟槽231内,且电性连接至该接地焊垫214。在本实施例中,该内屏蔽体24的材质为导电材料,例如焊料(Solder)或导电胶(ConductiveEpoxy)。该内屏蔽体24的宽度W2小于该接地焊垫214的宽度W1,较佳地,该内屏蔽体24的宽度W2为50μm至200μm,更佳地,该内屏蔽体24的宽度W2为100μm至200μm。The inner shield 24 is located in the trench 231 and is electrically connected to the ground pad 214 . In this embodiment, the inner shield 24 is made of conductive material, such as solder or conductive glue. The width W 2 of the inner shield 24 is smaller than the width W 1 of the ground pad 214 , preferably, the width W 2 of the inner shield 24 is 50 μm to 200 μm, more preferably, the width W of the inner shield 24 2 is 100 μm to 200 μm.

该遮蔽层25覆盖该封胶体23及该基板21的侧面2112,且电性连接该接地金属层212及该内屏蔽体24。在本实施例中,该遮蔽层25的厚度为1μm至2μm,该内屏蔽体24的厚度与该遮蔽层25的厚度的比值大于25,且该遮蔽层25的材质为镍。然而,在其它应用中,该遮蔽层25的材质可为铜,且该具有内屏蔽体的封装结构2更可包括一抗氧化层(图中未示)。该抗氧化层(图中未示)覆盖该遮蔽层25。较佳地,该抗氧化层(图中未示)的厚度为40nm,且其材质为不锈钢。The shielding layer 25 covers the sealing body 23 and the side surface 2112 of the substrate 21 , and is electrically connected to the ground metal layer 212 and the inner shielding body 24 . In this embodiment, the shielding layer 25 has a thickness of 1 μm to 2 μm, the ratio of the thickness of the inner shielding body 24 to the thickness of the shielding layer 25 is greater than 25, and the shielding layer 25 is made of nickel. However, in other applications, the material of the shielding layer 25 can be copper, and the package structure 2 with the inner shield can further include an anti-oxidation layer (not shown in the figure). The anti-oxidation layer (not shown in the figure) covers the shielding layer 25 . Preferably, the anti-oxidation layer (not shown in the figure) has a thickness of 40nm and is made of stainless steel.

参考图12至图24,显示本发明具有内屏蔽体的封装结构的第二实施例的制造方法的示意图。本实施例的具有内屏蔽体的封装结构的制造方法与第一实施例的具有内屏蔽体的封装结构的制造方法(图2至图11)大致相同,其中相同的组件赋予相同的编号。本实施例与第一实施例不同处在于提供该基板21及该等电子组件22时,更形成至少一第一焊料26于该接地焊垫214上。Referring to FIG. 12 to FIG. 24 , there are schematic diagrams showing the manufacturing method of the second embodiment of the package structure with the inner shield of the present invention. The manufacturing method of the packaging structure with an inner shield in this embodiment is substantially the same as the manufacturing method of the packaging structure with an inner shield in the first embodiment ( FIGS. 2 to 11 ), wherein the same components are assigned the same numbers. The difference between this embodiment and the first embodiment is that at least one first solder 26 is further formed on the ground pad 214 when the substrate 21 and the electronic components 22 are provided.

参考图12,提供该基板21。在本实施例中,该基板21的接地焊垫214为一连续不间断的长形区块,其面积较大且完整,如图13所示。藉此,后续在形成该第一焊料26及该内屏蔽体24于该接地焊垫214上时,其接触面积较大,则低电磁干扰的功效较佳。但是,后续在形成该第一焊料26于该接地焊垫214上时,该第一焊料26需涂布的面积太大,导致回焊该第一焊料26后,其隆起的厚度不一致。然而,在其它应用中,该基板21的接地焊垫214可包括数个区段2141,相邻二区段2141之间具有一间距,如图14所示。藉此,该接地焊垫214的区段2141的面积较小,使得形成且回焊该第一焊料26后,其隆起的厚度较一致。Referring to Fig. 12, the substrate 21 is provided. In this embodiment, the ground pad 214 of the substrate 21 is a continuous and uninterrupted elongated block with a large and complete area, as shown in FIG. 13 . In this way, when the first solder 26 and the inner shield 24 are formed on the ground pad 214 later, the contact area is larger, and the effect of low electromagnetic interference is better. However, when the first solder 26 is formed on the grounding pad 214 later, the first solder 26 needs to be applied to an area that is too large, resulting in inconsistent thicknesses of the bumps after reflowing the first solder 26 . However, in other applications, the ground pad 214 of the substrate 21 may include several sections 2141 , and there is a gap between two adjacent sections 2141 , as shown in FIG. 14 . Thereby, the area of the section 2141 of the ground pad 214 is smaller, so that after the first solder 26 is formed and reflowed, the thickness of the protrusion is relatively consistent.

参考图15,形成该第一焊料26于该接地焊垫214上,该第一焊料26电性连接至该内屏蔽体24。参考图16,提供该等电子组件22。该等电子组件22为主动组件,例如芯片,其包括至少一第二焊料27。接着,回焊(Reflow)该第一焊料26及该第二焊料27,使该第一焊料26的表面为圆弧状,且利用该第二焊料27将该等电子组件22设置于该基板21上。然而,在其它应用中,该等电子组件22可为被动组件,则在形成该第一焊料26于该接地焊垫214上时,更形成该第二焊料27于该上接地金属区域215上。参考图17,形成该封胶体23。参考图18,在移除部分该封胶体23,以形成至少一沟槽231时,该沟槽231显露部分该第一焊料26。藉此,当利用激光方法移除部分该封胶体23时,该第一焊料26可保护该接地焊垫214,避免该接地焊垫214受到激光损害。该沟槽231包括数个区段2311,相邻二区段2311之间具有一间距,如图19至图21所示。藉此,该沟槽231的区段2311的长宽深比较小,使得形成该内屏蔽体24时,能轻易填满该沟槽231的区段2311,而提升产品良率。参考图22,在形成一内屏蔽体24时,该内屏蔽体24通过该第一焊料26电性连接至该接地焊垫214。参考图23,沿该切割线L切割该基板21及该封胶体23。参考图24,形成该遮蔽层25。Referring to FIG. 15 , the first solder 26 is formed on the ground pad 214 , and the first solder 26 is electrically connected to the inner shield 24 . Referring to Figure 16, the electronic assemblies 22 are provided. The electronic components 22 are active components, such as chips, which include at least one second solder 27 . Then, reflow the first solder 26 and the second solder 27 to make the surface of the first solder 26 arc-shaped, and use the second solder 27 to arrange the electronic components 22 on the substrate 21 superior. However, in other applications, the electronic components 22 can be passive components, and when the first solder 26 is formed on the ground pad 214 , the second solder 27 is further formed on the upper ground metal region 215 . Referring to FIG. 17 , the sealing body 23 is formed. Referring to FIG. 18 , when part of the encapsulant 23 is removed to form at least one groove 231 , the groove 231 exposes a portion of the first solder 26 . In this way, when a part of the encapsulant 23 is removed by a laser method, the first solder 26 can protect the ground pad 214 and prevent the ground pad 214 from being damaged by the laser. The groove 231 includes several sections 2311 , and there is a distance between two adjacent sections 2311 , as shown in FIGS. 19 to 21 . Thereby, the ratio of length, width and depth of the section 2311 of the trench 231 is small, so that the section 2311 of the trench 231 can be easily filled when forming the inner shield 24 , thereby improving the product yield. Referring to FIG. 22 , when forming an inner shield 24 , the inner shield 24 is electrically connected to the ground pad 214 through the first solder 26 . Referring to FIG. 23 , the substrate 21 and the encapsulant 23 are cut along the cutting line L. Referring to FIG. Referring to FIG. 24, the shielding layer 25 is formed.

再参考图24,显示本发明具有内屏蔽体的封装结构的第二实施例的剖面示意图。本实施例的具有内屏蔽体的封装结构3与第一实施例的具有内屏蔽体的封装结构2(图11)大致相同,其中相同的组件赋予相同的编号。本实施例与第一实施例不同处在于该具有内屏蔽体的封装结构3更包括至少一第一焊料26。该第一焊料26位于该接地焊垫214上,电性连接至该内屏蔽体24,且该第一焊料26的表面为圆弧状。此外,该内屏蔽体24包括数个区段241,相邻二区段241之间具有一间距。Referring again to FIG. 24 , it shows a schematic cross-sectional view of a second embodiment of the packaging structure with an inner shield according to the present invention. The packaging structure 3 with an inner shield of this embodiment is substantially the same as the packaging structure 2 with an inner shield of the first embodiment ( FIG. 11 ), wherein the same components are given the same numbers. The difference between this embodiment and the first embodiment is that the packaging structure 3 with the inner shield further includes at least one first solder 26 . The first solder 26 is located on the ground pad 214 and electrically connected to the inner shield 24 , and the surface of the first solder 26 is arc-shaped. In addition, the inner shield 24 includes several sections 241 , and there is a gap between two adjacent sections 241 .

惟上述实施例仅为说明本发明的原理及其功效,而非用以限制本发明。因此,习于此技术的人士对上述实施例进行修改及变化仍不脱本发明的精神。本发明的权利范围应如权利要求书所列。However, the above-mentioned embodiments are only to illustrate the principles and effects of the present invention, not to limit the present invention. Therefore, those skilled in the art can modify and change the above embodiments without departing from the spirit of the present invention. The scope of rights of the present invention should be listed in the claims.

Claims (18)

1.一种具有内屏蔽体的封装结构,包括:1. A packaging structure with an inner shield, comprising: 一基板,具有一第一表面及一侧面,且包括:A substrate has a first surface and a side surface, and includes: 一接地金属层,位于该基板内,且显露于该基板的侧面;及a grounded metal layer within the substrate and exposed on the side of the substrate; and 至少一接地焊垫,位于该基板内,显露于该基板的第一表面,且电性连接至该接地金属层;At least one ground pad is located in the substrate, exposed on the first surface of the substrate, and electrically connected to the ground metal layer; 数个电子组件,位于该基板的第一表面;a plurality of electronic components located on the first surface of the substrate; 至少一第一焊料,位于该接地焊垫表面;at least one first solder located on the surface of the ground pad; 一封胶体,位于该基板的第一表面上,且包覆该等电子组件,该封胶体包括至少一沟槽、一上表面、一下表面及一侧面,该沟槽贯穿该封胶体的上表面及下表面,且位于该等电子组件之间,且该沟槽具有一长边及一短边,该短边与该封胶体的侧面之间具有一间距;An encapsulant is located on the first surface of the substrate and covers the electronic components, the encapsulant includes at least one groove, an upper surface, a lower surface and a side surface, the groove runs through the upper surface of the encapsulant and the lower surface, and are located between the electronic components, and the groove has a long side and a short side, and there is a distance between the short side and the side of the sealing body; 一内屏蔽体,位于该沟槽内,且通过该第一焊料电性连接至该接地焊垫;及an inner shield located in the trench and electrically connected to the ground pad through the first solder; and 一遮蔽层,覆盖该封胶体及该基板的侧面,且电性连接该接地金属层及该内屏蔽体。A shielding layer covers the sealing body and the side surface of the substrate, and electrically connects the grounding metal layer and the inner shielding body. 2.如权利要求1的封装结构,其中该基板更包括一上接地金属区域及一防焊层,该上接地金属区域位于该基板内,且显露于该基板的第一表面,该防焊层位于该基板的第一表面,且具有至少一开口,显露部分该上接地金属区域,以形成该接地焊垫。2. The package structure according to claim 1, wherein the substrate further comprises an upper ground metal region and a solder resist layer, the upper ground metal region is located in the substrate and exposed on the first surface of the substrate, the solder resist layer It is located on the first surface of the substrate and has at least one opening to expose a part of the upper ground metal region to form the ground pad. 3.如权利要求1的封装结构,其中该沟槽的长边为直线或弯曲的线段。3. The package structure according to claim 1, wherein the long side of the groove is a straight line or a curved line segment. 4.如权利要求1的封装结构,其中该内屏蔽体的材质为焊料或导电胶。4. The package structure according to claim 1, wherein the inner shield is made of solder or conductive glue. 5.如权利要求1的封装结构,更包括一抗氧化层,该抗氧化层覆盖该遮蔽层。5. The package structure of claim 1, further comprising an anti-oxidation layer covering the shielding layer. 6.一种具有内屏蔽体的封装结构,包括:6. A packaging structure with an inner shield, comprising: 一基板,具有一第一表面及一侧面,且包括:A substrate has a first surface and a side surface, and includes: 一接地金属层,位于该基板内,且显露于该基板的侧面;及a grounded metal layer within the substrate and exposed on the side of the substrate; and 至少一接地焊垫,位于该基板内,显露于该基板的第一表面,且电性连接至该接地金属层;At least one ground pad is located in the substrate, exposed on the first surface of the substrate, and electrically connected to the ground metal layer; 数个电子组件,位于该基板的第一表面;a plurality of electronic components located on the first surface of the substrate; 至少一第一焊料,位于该接地焊垫表面;at least one first solder located on the surface of the ground pad; 一封胶体,位于该基板的第一表面上,且包覆该等电子组件,该封胶体包括至少一沟槽、一上表面、一下表面及一侧面,该沟槽贯穿该封胶体的上表面及下表面,且位于该等电子组件之间;An encapsulant is located on the first surface of the substrate and covers the electronic components, the encapsulant includes at least one groove, an upper surface, a lower surface and a side surface, the groove runs through the upper surface of the encapsulant and the lower surface between the electronic components; 一内屏蔽体,位于该沟槽内,且通过该第一焊料电性连接至该接地焊垫;及an inner shield located in the trench and electrically connected to the ground pad through the first solder; and 一遮蔽层,覆盖该封胶体及该基板的侧面,且电性连接该接地金属层及该内屏蔽体,其中该内屏蔽体的厚度与该遮蔽层的厚度的比值大于25。A shielding layer covers the sealing body and the side surface of the substrate, and electrically connects the grounding metal layer and the inner shielding body, wherein the ratio of the thickness of the inner shielding body to the thickness of the shielding layer is greater than 25. 7.如权利要求6的封装结构,其中该基板更包括一上接地金属区域及一防焊层,该上接地金属区域位于该基板内,且显露于该基板的第一表面,该防焊层位于该基板的第一表面,且具有至少一开口,显露部分该上接地金属区域,以形成该接地焊垫。7. The package structure according to claim 6, wherein the substrate further comprises an upper ground metal region and a solder resist layer, the upper ground metal region is located in the substrate and exposed on the first surface of the substrate, the solder resist layer It is located on the first surface of the substrate and has at least one opening to expose a part of the upper ground metal region to form the ground pad. 8.如权利要求6的封装结构,其中该内屏蔽体包括数个区段,相邻二区段之间具有一间距。8. The package structure of claim 6, wherein the inner shield comprises several sections, and there is a gap between two adjacent sections. 9.如权利要求6的封装结构,其中该第一焊料的表面为圆弧状。9. The package structure of claim 6, wherein a surface of the first solder is arc-shaped. 10.一种具有内屏蔽体的封装结构的制造方法,包括:10. A method of manufacturing a packaging structure with an inner shield, comprising: 提供一基板及数个电子组件,该基板具有一第一表面及一侧面,且包括一接地金属层及至少一接地焊垫,该接地金属层位于该基板内,且显露于该基板的侧面,该接地焊垫位于该基板内,显露于该基板的第一表面,且电性连接至该接地金属层,该等电子组件位于该基板的第一表面;A substrate and several electronic components are provided, the substrate has a first surface and a side surface, and includes a ground metal layer and at least one ground pad, the ground metal layer is located in the substrate and exposed on the side of the substrate, The ground pad is located in the substrate, exposed on the first surface of the substrate, and electrically connected to the ground metal layer, and the electronic components are located on the first surface of the substrate; 形成至少一第一焊料于该接地焊垫上;forming at least one first solder on the ground pad; 形成一封胶体于该基板的第一表面上,以包覆该等电子组件,该封胶体包括一上表面、一下表面及一侧面;forming a sealant on the first surface of the substrate to cover the electronic components, the sealant comprising an upper surface, a lower surface and a side surface; 移除部分该封胶体,以形成至少一沟槽,该沟槽贯穿该封胶体的上表面及下表面,且位于该等电子组件之间;removing part of the sealing body to form at least one groove, the groove runs through the upper surface and the lower surface of the sealing body, and is located between the electronic components; 填满一内屏蔽体于该沟槽内,该内屏蔽体通过该第一焊料电性连接至该接地焊垫;an inner shield is filled in the trench, and the inner shield is electrically connected to the ground pad through the first solder; 切割该基板及该封胶体;及cutting the substrate and the encapsulant; and 形成一遮蔽层,以覆盖该封胶体及该基板的侧面,且电性连接该接地金属层及该内屏蔽体。A shielding layer is formed to cover the sealing body and the side surfaces of the substrate, and is electrically connected to the grounding metal layer and the inner shielding body. 11.如权利要求10的方法,其中该基板更包括一上接地金属区域及一防焊层,该上接地金属区域位于该基板内,且显露于该基板的第一表面,该防焊层位于该基板的第一表面,且具有至少一开口,显露部分该上接地金属区域,以形成该接地焊垫。11. The method according to claim 10, wherein the substrate further comprises an upper ground metal region and a solder resist layer, the upper ground metal region is located in the substrate and exposed on the first surface of the substrate, the solder resist layer is located The first surface of the substrate has at least one opening exposing a part of the upper ground metal region to form the ground pad. 12.如权利要求10的方法,其中该提供一基板及数个电子组件的步骤之后,更包括一回焊该第一焊料的步骤,使该第一焊料的表面为圆弧状。12. The method of claim 10, further comprising a step of reflowing the first solder after the step of providing a substrate and a plurality of electronic components, so that the surface of the first solder is arc-shaped. 13.如权利要求10的方法,其中该沟槽显露部分该第一焊料。13. The method of claim 10, wherein the trench exposes a portion of the first solder. 14.如权利要求10的方法,其中该沟槽具有一长边及一短边,该短边与该封胶体的侧面之间具有一间距。14. The method of claim 10, wherein the groove has a long side and a short side, and there is a distance between the short side and the side of the encapsulant. 15.如权利要求10的方法,其中该沟槽包括数个区段,相邻二区段之间具有一间距。15. The method of claim 10, wherein the groove comprises a plurality of sections, and there is a gap between two adjacent sections. 16.如权利要求10的方法,其中该填满一内屏蔽体于该沟槽内的步骤中,利用网印方式方法形成该内屏蔽体。16. The method of claim 10, wherein in the step of filling an inner shield in the trench, the inner shield is formed by screen printing. 17.如权利要求10的方法,其中该内屏蔽体的材质为焊料或导电胶。17. The method of claim 10, wherein the inner shield is made of solder or conductive glue. 18.如权利要求10的方法,其中该形成一遮蔽层的步骤之后,更包括形成一抗氧化层的步骤,该抗氧化层覆盖该遮蔽层。18. The method of claim 10, further comprising the step of forming an anti-oxidation layer after the step of forming a masking layer, and the anti-oxidation layer covers the masking layer.
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Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102364683A (en) * 2011-10-21 2012-02-29 华为终端有限公司 Packaging structure and method thereof, and electronic equipment
CN103137595A (en) * 2011-11-25 2013-06-05 亚旭电子科技(江苏)有限公司 System-level encapsulation module part and manufacturing method thereof
CN103681625B (en) * 2012-09-24 2016-05-25 环旭电子股份有限公司 Electronic module with and manufacture method
TWI554196B (en) * 2013-07-31 2016-10-11 環旭電子股份有限公司 Electronic packaging device and manufacturing method thereof
CN104347595B (en) * 2013-07-31 2017-04-12 环旭电子股份有限公司 Electronic packaging module and manufacturing method thereof
CN104347533B (en) * 2013-08-01 2020-05-26 日月光半导体制造股份有限公司 Semiconductor package and method of manufacturing the same
US9564937B2 (en) * 2013-11-05 2017-02-07 Skyworks Solutions, Inc. Devices and methods related to packaging of radio-frequency devices on ceramic substrates
CN103617991A (en) * 2013-11-20 2014-03-05 华进半导体封装先导技术研发中心有限公司 Semiconductor encapsulation electromagnetic shielding structure and manufacturing method
TWI509767B (en) 2013-12-13 2015-11-21 Universal Scient Ind Shanghai Electronic package module and manufacturing method thereof
CN104716102B (en) * 2013-12-13 2017-07-21 环旭电子股份有限公司 Electronic package module and method of manufacturing the same
US9949359B2 (en) 2014-03-18 2018-04-17 Apple Inc. Multi-layer thin-film coatings for system-in-package assemblies in portable electronic devices
US9913412B2 (en) 2014-03-18 2018-03-06 Apple Inc. Shielding structures for system-in-package assemblies in portable electronic devices
CN105023851B (en) * 2014-04-28 2018-05-01 环旭电子股份有限公司 Method for manufacturing electronic packaging module
US9820373B2 (en) 2014-06-26 2017-11-14 Apple Inc. Thermal solutions for system-in-package assemblies in portable electronic devices
CN110071099A (en) * 2014-07-30 2019-07-30 日月光半导体制造股份有限公司 The manufacturing method of Electronic Packaging modular structure and Electronic Packaging module
CN106033755A (en) * 2015-03-17 2016-10-19 晟碟信息科技(上海)有限公司 Semiconductor device and substrate tape with EMI shielding
TWI570842B (en) * 2015-07-03 2017-02-11 矽品精密工業股份有限公司 Electronic package and method for fabricating the same
JP6728917B2 (en) * 2016-04-12 2020-07-22 Tdk株式会社 Method of manufacturing electronic circuit module
CN106169428B (en) * 2016-08-31 2018-08-31 华天科技(昆山)电子有限公司 Chip-packaging structure for slowing down electromagnetic interference and packaging method
US10784230B2 (en) * 2016-11-15 2020-09-22 Advanced Semiconductor Engineering, Inc. Compartment shielding for warpage improvement
US10147835B2 (en) * 2017-03-17 2018-12-04 Advanced Semiconductor Engineering, Inc. Optical device and method of manufacturing the same
CN108735715A (en) * 2017-04-20 2018-11-02 吴明哲 Selective electromagnetic shielding package structure and manufacturing method thereof
JP7111112B2 (en) 2018-01-05 2022-08-02 株式会社村田製作所 high frequency module
CN111769107A (en) * 2019-04-01 2020-10-13 菱生精密工业股份有限公司 Light Sensing Module Package Structure
CN110335862A (en) * 2019-06-17 2019-10-15 青岛歌尔微电子研究院有限公司 A kind of shielding process of SIP encapsulation
CN111162755B (en) * 2020-01-16 2021-09-21 诺思(天津)微系统有限责任公司 A Bulk Acoustic Wave Duplex Filter
CN111554675A (en) * 2020-05-18 2020-08-18 甬矽电子(宁波)股份有限公司 Electromagnetic shielding structure, electromagnetic shielding structure manufacturing method and electronic product
CN111696963A (en) * 2020-07-14 2020-09-22 立讯电子科技(昆山)有限公司 Packaging structure and manufacturing method thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101401206A (en) * 2006-03-29 2009-04-01 京瓷株式会社 Circuit module, wireless communication device, and method for manufacturing circuit module

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101401206A (en) * 2006-03-29 2009-04-01 京瓷株式会社 Circuit module, wireless communication device, and method for manufacturing circuit module

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JP特开2004-172176A 2004.06.17

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