CN102056414A - Manufacturing method of printed circuit board - Google Patents
Manufacturing method of printed circuit board Download PDFInfo
- Publication number
- CN102056414A CN102056414A CN 201010622826 CN201010622826A CN102056414A CN 102056414 A CN102056414 A CN 102056414A CN 201010622826 CN201010622826 CN 201010622826 CN 201010622826 A CN201010622826 A CN 201010622826A CN 102056414 A CN102056414 A CN 102056414A
- Authority
- CN
- China
- Prior art keywords
- printed circuit
- circuit board
- pcb
- layer
- symmetry
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 claims abstract description 66
- 238000003825 pressing Methods 0.000 claims abstract description 39
- 238000003475 lamination Methods 0.000 claims abstract description 17
- 238000003491 array Methods 0.000 claims description 14
- 238000012546 transfer Methods 0.000 claims description 8
- 230000004927 fusion Effects 0.000 claims description 7
- 239000011248 coating agent Substances 0.000 abstract description 8
- 238000000576 coating method Methods 0.000 abstract description 8
- 230000008602 contraction Effects 0.000 abstract 1
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 230000003044 adaptive effect Effects 0.000 description 1
- 239000005030 aluminium foil Substances 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
Images
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
本发明实施例公开了一种印刷电路板的制作方法，涉及印刷电路领域，用以解决多层板制作过程中，对称层芯板涨缩系数不匹配、镀层不均匀、压板时芯板无法全部配对的问题。本发明实施例中的印刷电路板的制作方法包括：将所述印刷电路板的两个对称层的图形在同一芯板上以对称的形式制作；通过层压的方式将各所述芯板进行压合。本发明实施例中的方案适用于各层图形厚度和绝缘层厚度对称排列的印刷电路板。
The embodiment of the present invention discloses a method for manufacturing a printed circuit board, which relates to the field of printed circuit boards, and is used to solve the problem of mismatched expansion and contraction coefficients of the symmetrical layer core board, uneven coating, and failure of the core board to be completely flat when pressing the board. pairing problem. The manufacturing method of the printed circuit board in the embodiment of the present invention includes: making the patterns of the two symmetrical layers of the printed circuit board in a symmetrical form on the same core board; Lamination. The solutions in the embodiments of the present invention are applicable to printed circuit boards in which the pattern thicknesses of various layers and the insulating layer thicknesses are symmetrically arranged.
Description
Technical field
The present invention relates to printed circuit field, relate in particular to a kind of manufacture method of printed circuit board (PCB).
Background technology
Be provided with via through regular meeting in printed circuit board (PCB), described via runs through the entire circuit plate, is attached to metal film structures on the via inwall and can connects circuit between the different layers.Along with the raising of circuit structure integrated level, the also corresponding increase of the current densities that on the circuit board of unit are, is provided with.Yet, general via only plays electric path (interconnection) effect of electronic component and does not bear the task of supporting electronic component, therefore for the integrated needs of adaptive circuit height, in existing multilayer board, introduced and buried/blind hole structure, can only need between the internal layer of electric interconnection through hole to be set like this, on simultaneously corresponding other layer structure electronic component or circuit structure can be set with this lead to the hole site.
Owing to bury/the blind hole structure layout is in the part layer structure of multilayer board, therefore, have bury/multiple-plate production and processing of blind hole structure is more more complex than conventional multi-layer sheet, repeatedly hole, the holeization, electroplate and process such as pressing plate repeatedly as needs; Long because of its production procedure, each layer central layer independently made, so be easy to occur that each central layer harmomegathus coefficient does not match, uneven coating is even, central layer such as can't all match at problem during pressing plate.
Summary of the invention
Embodiments of the invention provide a kind of manufacture method of printed circuit board (PCB), in the multi-layer sheet manufacturing process that solves each layer pattern thickness and thickness of insulating layer symmetric arrays, the problem that symmetrical layers central layer harmomegathus coefficient does not match, uneven coating is even, central layer can't all match during pressing plate.
For achieving the above object, embodiments of the invention adopt following technical scheme:
A kind of manufacture method of printed circuit board (PCB), each layer pattern thickness and thickness of insulating layer symmetric arrays in the described printed circuit board (PCB); Described manufacture method comprises:
Figure form with symmetry on same central layer of two symmetrical layers of described printed circuit board (PCB) is made;
Mode by lamination is carried out pressing with each described central layer.
The manufacture method of the printed circuit board (PCB) that the embodiment of the invention provides, printed circuit board (PCB) at each layer pattern thickness and thickness of insulating layer symmetric arrays, figure with two symmetrical layers in its production jigsaw process is produced on same the central layer symmetrically, not only can shorten production procedure, and since symmetrical two-layer be to make with layer, its central layer harmomegathus coefficient and the coating uniformity all are consistent; Therefore, the scheme that provides in the embodiment of the invention is provided, can solve in the multi-layer sheet manufacturing process of each layer pattern thickness and thickness of insulating layer symmetric arrays the problem that symmetrical layers central layer harmomegathus coefficient does not match, uneven coating is even, central layer can't all match during pressing plate.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the accompanying drawing of required use is done to introduce simply in will describing embodiment below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the flow chart of the print circuit plates making method of one embodiment of the invention;
Fig. 2 is the schematic diagram of the corresponding graphics field of a certain figure layer;
Fig. 3 is the flow chart of the print circuit plates making method of another embodiment of the present invention;
Fig. 4 is the schematic diagram that the solder side behind component side and the mirror image carries out jigsaw;
Fig. 5 is the schematic diagram that the L5 layer behind L2 layer and the mirror image carries out jigsaw;
Fig. 6 is the schematic diagram that the L4 layer behind L3 layer and the mirror image carries out jigsaw;
Fig. 7 is for being symmetrical arranged first kind of situation of location hole in the graphics field;
Fig. 8 is for being symmetrical arranged second kind of situation of location hole in the graphics field;
Fig. 9 is for carrying out the schematic diagram of second pressing lamination to six laminates.
Embodiment
The invention provides a kind of manufacture method of printed circuit board (PCB), each layer pattern thickness and thickness of insulating layer symmetric arrays in the described printed circuit board (PCB); Described manufacture method comprises:
Figure form with symmetry on same central layer of two symmetrical layers of described printed circuit board (PCB) is made;
Mode by lamination is carried out pressing with each described central layer.
Preferably, in various embodiments of the present invention, the figure of described two symmetrical layers with described printed circuit board (PCB) form with symmetry on same central layer is made, and comprising:
The figure of two symmetrical layers of the described printed circuit board (PCB) form with symmetry is plotted on the same egative film;
With two symmetrical figure transfer of drawing on the described egative film to same central layer.
Preferably, in various embodiments of the present invention, the symmetry axis of the figure of described two symmetrical layers on same egative film is first symmetry axis;
Before described two symmetrical figure transfer of drawing on described egative film are to the same central layer, also comprise:
On same egative film, be second symmetry axis with the center line that parallels with described first symmetry axis in the described figure, fusion area and location hole are set symmetrically.
But, alternately,, then also can fusion area and location hole be set symmetrically on described central layer, be used for following process and handle (for example lamination) by alternate manner if do not adopt the egative film branch mode.
Preferably, in various embodiments of the present invention, comprise at least one in the described location hole and be used to prevent the inverted location hole of printed circuit board (PCB).
Preferably, in various embodiments of the present invention, also comprise:
Corresponding to described fusion area and location hole, be second symmetry axis with the center line that is parallel to described first symmetry axis in the described figure, rivet target, rivet hole, pin location hole and pin target are set symmetrically.
But, alternately,, then also can rivet target, rivet hole, pin location hole and pin target be set symmetrically on described central layer, be used for following process and handle (for example lamination) by alternate manner if do not adopt the egative film branch mode.
Preferably, in various embodiments of the present invention, before making with the form of symmetry on the same central layer, also comprise at the figure of described two symmetrical layers with described printed circuit board (PCB):
Make the unit data and the mirror image unit data thereof of one deck at least, the unit data of the symmetrical layers that described mirror image unit data is this layer.
Preferably, in various embodiments of the present invention, before making with the form of symmetry on the same central layer, also comprise at the figure of described two symmetrical layers with described printed circuit board (PCB):
Make the auxiliary process limit data and the mirror image auxiliary process limit data thereof of one deck at least, described mirror image auxiliary process limit data is the auxiliary process limit data of the symmetrical layers of this layer.
Preferably, in various embodiments of the present invention, if the circuit number of plies of described printed circuit board (PCB) is 2N, wherein N is the natural number (for example being 2) more than or equal to 1, and the central layer that then described mode by lamination will be formed with the figure of symmetry carries out pressing, specifically comprises:
According to predefined procedure the central layer that N is formed with the figure of symmetry is carried out pressing, obtain the N laminate after the first pressing;
With after the described N laminate Rotate 180 degree with the pressing of the described N laminate of another piece, be the printed circuit board (PCB) of 2N thereby obtain the two cover circuit numbers of plies simultaneously.
Preferably, in various embodiments of the present invention, if the circuit number of plies of described printed circuit board (PCB) is 2N+1, wherein N is the natural number (for example being 2) more than or equal to 1, the central layer that then described mode by lamination will be formed with the figure of symmetry carries out pressing, specifically comprises:
According to predefined procedure the central layer that N is formed with the figure of symmetry is carried out pressing, obtain the N laminate after the first pressing;
With a described N laminate Rotate 180 degree;
Another described N laminate, N+1 laminate and described postrotational N laminate are arranged and pressing in turn, are the printed circuit board (PCB) of 2N+1 thereby obtain the two cover circuit numbers of plies simultaneously.
Preferably, in various embodiments of the present invention, described printed circuit board (PCB) is to have to bury/printed circuit board (PCB) of blind hole structure.
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
As shown in Figure 1, the print circuit plates making method in the embodiment of the invention is mainly used in the printed circuit board (PCB) of each layer pattern thickness and thickness of insulating layer symmetric arrays; Wherein, described each layer pattern can be but be not limited to be to be made by Copper Foil or aluminium foil.
Particularly, described print circuit plates making method comprises:
101, when producing jigsaw, the figure of two symmetrical layers in the described printed circuit board (PCB) form with symmetry is plotted on same the egative film.
Wherein, two symmetrical layers refer to two figure layers of symmetric arrays in the described printed circuit board (PCB); Same plane in, promptly on same egative film draw again by the form with symmetry for the figure of these two symmetrical layers.
102, with two symmetrical figure transfer of drawing on the described egative film to same central layer.
103, the central layer that will be formed with the figure of symmetry of the mode by lamination carries out pressing according to predefined procedure.
Above-mentioned manufacture method mainly is the printed circuit board (PCB) at each layer pattern thickness and thickness of insulating layer symmetric arrays; In the production jigsaw process of printed circuit board (PCB), two symmetrical figure layer graphs of a correspondence are plotted on same the egative film symmetrically, and symmetrical two figure layers are produced on same the central layer symmetrically, can shorten production procedure, and because two symmetrical figure layers are to make with layer, its central layer harmomegathus coefficient and the coating uniformity all are consistent; Therefore, utilize such scheme, can solve in the multi-layer sheet manufacturing process of each layer pattern thickness and thickness of insulating layer symmetric arrays, the problem that symmetrical layers central layer harmomegathus coefficient does not match, uneven coating is even, central layer can't all match during pressing plate.
Such scheme goes for the printed circuit board (PCB) that the circuit number of plies is an even number, also goes for the printed circuit board (PCB) that the circuit number of plies is an odd number.
Below with the circuit number of plies be even number printed circuit board (PCB) be made as example, and further introduce print circuit plates making method in the embodiment of the invention by another specific embodiment.
The data that the relevant PCB design that needed elder generation that the client is provided before entering the print circuit plates making flow process requires is analyzed.If the circuit number of plies of the printed circuit board (PCB) that the client need make is even number and each layer pattern thickness and thickness of insulating layer symmetric arrays, then can utilize the method in the embodiment of the invention to make printed circuit board (PCB); Otherwise, still should utilize conventional method to make printed circuit board (PCB).
When carrying out analysis, the PCB design that also needs to provide according to the client requires and PCB (Print Circuit Broad, printed circuit board (PCB)) jigsaw utilance, determines the symmetry axis direction of image when carrying out mirror image of a certain figure layer.As center line among Fig. 21 or center line 2.
In the present embodiment, the circuit number of plies of setting printed circuit board (PCB) is 2N, and wherein N is the natural number more than or equal to 1.
As shown in Figure 3, the print circuit plates making method in the present embodiment specifically may further comprise the steps:
301, make the unit data and the mirror image unit data thereof of a certain figure layer, the unit data of the symmetric graph layer that described mirror image unit data is this figure layer.
In this step, can finish the making of unit data (Pcb Step) according to the manufacture method of routine; Afterwards, make and the symmetrical mirror image unit data (Mirror Pcb Step) of this unit data, and upgrade each layer data.
302, the auxiliary process limit data and the mirror image auxiliary process limit data thereof of the layer of figure described in the making step 301, described mirror image auxiliary process limit data is the auxiliary process limit data of the symmetric graph layer of this figure layer.
After completing steps 301, also need to finish the making of auxiliary process limit data (Set Step), and create the auxiliary process limit data (Mirror Set Step) behind the mirror image according to customer requirement, upgrade corresponding each layer data simultaneously.
303, produce jigsaw and make, in the jigsaw process, the form of two the symmetrical figure layer graphs of a correspondence in the described printed circuit board (PCB) with symmetry is plotted on same the egative film.
At the circuit number of plies is the printed circuit board (PCB) of 2N, exactly the figure of the 1st layer (component side) and the figure of 2N layer (solder side) is stitched together symmetrically, is plotted on same the egative film.Similarly, the figure of the 2nd layer pattern and 2N-1 layer is stitched together symmetrically, and is plotted on same the egative film; ...; The figure of N layer pattern and N+1 layer is stitched together symmetrically, and is plotted on same the egative film.
With six laminates is example, and the solder side (BOT) behind component side (TOP) and the mirror image is stitched together, and sees also Fig. 4; L5 layer behind L2 layer and the mirror image is stitched together, sees also Fig. 5; L4 layer behind L3 layer and the mirror image is stitched together, sees also Fig. 6.
304, be first symmetry axis with the symmetrical symmetry axis of two figure layer graphs of a correspondence on same egative film; In each figure layer graph of a correspondence, be second symmetry axis with the center line that is parallel to described first symmetry axis in this figure, fusion area and location hole are set symmetrically.Comprise at least one in the described location hole and be used to prevent the inverted location hole of printed circuit board (PCB).
In addition, when described fusion area and location hole are set, need be second symmetry axis also with the center line that is parallel to described first symmetry axis in the described figure, rivet target, rivet hole, pin location hole and pin target are set symmetrically.
Be example so that location hole to be set below, and step 304 be described further in conjunction with graphics field shown in Figure 2.
As can see from Figure 2, need to be provided with 1,2,3,4 four location hole in the figure of a certain figure layer, its mesopore 1 is used for counnter attack (prevent printed circuit board (PCB) be inverted in the lamination process).Because hole 1 and hole 2 are not symmetrically arranged, therefore when symmetrical jigsaw, can be blocked and can't use, therefore the figure of a certain figure layer and the symmetric graph layer of this figure layer to be made on same central layer, just symmetrical location hole need be set in figure shown in Figure 2, to avoid two symmetrical location holes of scheming in the layer to align and then can't accurately locate to circuit board.
If with the center line among Fig. 21 is second symmetry axis, then as shown in Figure 7, set up hole 5 and hole 6; Wherein, hole 5 and hole 2 about center line 1 symmetry, hole 6 and hole 1 about center line 1 symmetry;
If with the center line among Fig. 22 is second symmetry axis, then as shown in Figure 8, set up hole 5 ' and hole 6 '; Wherein, hole 5 ' with hole 3 about center line 2 symmetries, hole 6 ' with hole 1 about center line 2 symmetries.
305, produce the film according to the graphic plotting that designs.
Two corresponding central layers of figure layer of symmetry only need be drawn the film of one of them symmetric graph layer.For example, six laminates of above-mentioned introduction only need be drawn component side (TOP layer) film, the L2 layer film and the L3 layer film.
306, with two symmetrical figure transfer of drawing on the egative film to same central layer, and the central layer that the mode by lamination will be formed with the figure of symmetry carries out pressing according to predefined procedure.
In this step, be example with six layers of blind hole plate.Particularly, the execution of step 306 can comprise following process:
The figure transfer of A, L2 layer and L5 layer;
Because the image of L2 and L5 layer on same egative film, therefore can be transferred to the figure on L2 layer and the L5 layer egative film on the central layer simultaneously, need protect the basic copper of L3 layer and L4 layer this moment, for shifting L3 layer and L4 layer pattern behind the lamination.
B, one step press;
L2-L3 (or L4-L5) central layer and component side (or solder side) Copper Foil and corresponding resin are pressed into a three ply board, i.e. the three ply board of component side-L3 layer (or L4 layer-solder side).
C, power auger blind hole, Kong Hua etc.;
D, L3 layer and L4 layer pattern shift;
Shift L3 layer and L4 layer egative film figure, the basic copper of component side (or solder side) need protect, for transfer element face behind the secondary lamination and solder side figure.
Through after the above-mentioned steps, according to predefined procedure 3 central layers that are formed with symmetric figure are carried out pressing, obtained the three ply board after the first pressing.
E, second pressing;
Central layer figure after two identical process blind holes are electroplated carries out lamination to figure after the location hole on the frame overlaps, and is about to pressing is good in the B step a three ply board and another piece three ply board behind the symmetry axis mirror image and is pressed into six laminates.Specifically see also Fig. 9, get two three ply boards after the identical above-mentioned first pressing, will be wherein a three ply board Rotate 180 degree, and with another piece three ply board contraposition pressing, thereby obtain six layers of blind hole plate of two covers simultaneously.
F, outer graphics are made.
Outer graphics is made the graphic making that comprises component side, and this process is identical with common multiple-plate outer graphics making, repeats no more herein.
In the foregoing description, be that example is illustrated the method among the present invention only with six layers of blind hole plate.For the other types printed circuit board (PCB) of non-six layers of blind hole structure, its production principle is identical, can be with reference to the manufacturing process of above-mentioned six layers of blind hole plate.
In addition, if the circuit number of plies of printed circuit board (PCB) is odd number and each layer pattern thickness and thickness of insulating layer symmetric arrays, be example with 7 layers pcb boards, when carrying out pressing, can earlier the 1-3 layer be carried out pressing, obtain 3 laminates after the first pressing afterwards; With described 3 laminate Rotate 180 degree, and another described 3 laminates, the 4th laminate and described postrotational 3 laminates being arranged in turn, carry out second pressing, is 7 printed circuit board (PCB) thereby obtain the two cover circuit numbers of plies simultaneously.The specific implementation process can repeat no more with reference to the making of above-mentioned six laminates herein.
The scheme that provides in the embodiment of the invention goes for the printed circuit board (PCB) of each layer pattern thickness and thickness of insulating layer symmetric arrays, is particularly useful for meeting having of above-mentioned condition to bury/printed circuit board (PCB) of blind hole structure.
Utilize such scheme, not only can separate in the multi-layer sheet manufacturing process of each layer pattern thickness and thickness of insulating layer symmetric arrays, the problem that symmetrical layers central layer harmomegathus coefficient does not match, uneven coating is even, central layer can't all match during pressing plate; And can improve and bury/make efficiency of the printed circuit board (PCB) of blind hole structure, shorten the manufacture craft consumed time.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the variation that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (10)
1. the manufacture method of a printed circuit board (PCB), each layer pattern thickness and thickness of insulating layer symmetric arrays in the described printed circuit board (PCB); It is characterized in that described manufacture method comprises:
Figure form with symmetry on same central layer of two symmetrical layers of described printed circuit board (PCB) is made;
Mode by lamination is carried out pressing with each described central layer.
2. the manufacture method of printed circuit board (PCB) according to claim 1 is characterized in that, the figure of described two symmetrical layers with described printed circuit board (PCB) form with symmetry on same central layer is made, and comprising:
The figure of two symmetrical layers of the described printed circuit board (PCB) form with symmetry is plotted on the same egative film;
With two symmetrical figure transfer of drawing on the described egative film to same central layer.
3. the manufacture method of printed circuit board (PCB) according to claim 2 is characterized in that, the symmetry axis of the figure of described two symmetrical layers on same egative film is first symmetry axis;
Before described two symmetrical figure transfer of drawing on described egative film are to the same central layer, also comprise:
On same egative film, be second symmetry axis with the center line that parallels with described first symmetry axis in the described figure, fusion area and location hole are set symmetrically.
4. the manufacture method of printed circuit board (PCB) according to claim 3 is characterized in that, comprises at least one in the described location hole and is used to prevent the inverted location hole of printed circuit board (PCB).
5. according to the manufacture method of claim 3 or 4 described printed circuit board (PCB)s, it is characterized in that, also comprise:
Corresponding to described fusion area and location hole, be second symmetry axis with the center line that is parallel to described first symmetry axis in the described figure, rivet target, rivet hole, pin location hole and pin target are set symmetrically.
6. according to the manufacture method of each described printed circuit board (PCB) in the claim 1 to 5, it is characterized in that, before making with the form of symmetry on the same central layer, also comprise at the figure of described two symmetrical layers with described printed circuit board (PCB):
Make the unit data and the mirror image unit data thereof of one deck at least, the unit data of the symmetrical layers that described mirror image unit data is this layer.
7. the manufacture method of printed circuit board (PCB) according to claim 6 is characterized in that,, also comprises before making with the form of symmetry on the same central layer at the figure of described two symmetrical layers with described printed circuit board (PCB):
Make the auxiliary process limit data and the mirror image auxiliary process limit data thereof of one deck at least, described mirror image auxiliary process limit data is the auxiliary process limit data of the symmetrical layers of this layer.
8. according to the manufacture method of arbitrary described printed circuit board (PCB) in the claim 1 to 7, it is characterized in that, if the circuit number of plies of described printed circuit board (PCB) is 2N, wherein N is the natural number more than or equal to 1, the central layer that then described mode by lamination will be formed with the figure of symmetry carries out pressing, specifically comprises:
According to predefined procedure the central layer that N is formed with the figure of symmetry is carried out pressing, obtain the N laminate after the first pressing;
With after the described N laminate Rotate 180 degree with the pressing of the described N laminate of another piece, be the printed circuit board (PCB) of 2N thereby obtain the two cover circuit numbers of plies simultaneously.
9. according to the manufacture method of arbitrary described printed circuit board (PCB) in the claim 1 to 7, it is characterized in that, if the circuit number of plies of described printed circuit board (PCB) is 2N+1, wherein N is the natural number more than or equal to 1, the central layer that then described mode by lamination will be formed with the figure of symmetry carries out pressing, specifically comprises:
According to predefined procedure the central layer that N is formed with the figure of symmetry is carried out pressing, obtain the N laminate after the first pressing;
With a described N laminate Rotate 180 degree;
Another described N laminate, N+1 laminate and described postrotational N laminate are arranged and pressing in turn, are the printed circuit board (PCB) of 2N+1 thereby obtain the two cover circuit numbers of plies simultaneously.
10. according to the manufacture method of arbitrary described printed circuit board (PCB) in the claim 1 to 9, it is characterized in that described printed circuit board (PCB) is to have to bury/printed circuit board (PCB) of blind hole structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010622826 CN102056414A (en) | 2010-12-29 | 2010-12-29 | Manufacturing method of printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010622826 CN102056414A (en) | 2010-12-29 | 2010-12-29 | Manufacturing method of printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102056414A true CN102056414A (en) | 2011-05-11 |
Family
ID=43960163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201010622826 Pending CN102056414A (en) | 2010-12-29 | 2010-12-29 | Manufacturing method of printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102056414A (en) |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102427669A (en) * | 2011-11-15 | 2012-04-25 | 华南理工大学 | Method for manufacturing double-sided printed circuit board |
| CN103179807A (en) * | 2013-03-07 | 2013-06-26 | 深圳崇达多层线路板有限公司 | Method for improving warping of PCB (printed circuit board) by blind holes |
| CN103429013A (en) * | 2012-05-16 | 2013-12-04 | 北大方正集团有限公司 | Multi-layer printed wiring board and manufacturing method thereof |
| CN103687315A (en) * | 2013-12-12 | 2014-03-26 | 广州兴森快捷电路科技有限公司 | Designing method of punching alignment target |
| CN103957673A (en) * | 2014-05-21 | 2014-07-30 | 赣州市深联电路有限公司 | Method for preventing copper coil from wrinkling in multi-layer board pressing process |
| CN104968150A (en) * | 2015-06-30 | 2015-10-07 | 开平依利安达电子第三有限公司 | High-layer circuit board manufactured by applying mirror symmetry and manufacturing method thereof |
| CN105632941A (en) * | 2016-02-02 | 2016-06-01 | 广州兴森快捷电路科技有限公司 | Expansion and shrinkage process control-based production method for package substrate |
| CN106231785A (en) * | 2016-08-18 | 2016-12-14 | 深圳崇达多层线路板有限公司 | Printed circuit board (PCB) pressing structure and multilayer board |
| CN107148168A (en) * | 2017-05-08 | 2017-09-08 | 江苏博敏电子有限公司 | A kind of fusion process of pressure programming |
| CN107708285A (en) * | 2016-08-09 | 2018-02-16 | 北大方正集团有限公司 | The preparation method of multilayer circuit board and multilayer circuit board |
| CN110324993A (en) * | 2019-07-29 | 2019-10-11 | 重庆伟鼎电子科技有限公司 | Circuit board pressing is to pressure |
| CN110708893A (en) * | 2019-09-30 | 2020-01-17 | 奥士康科技股份有限公司 | Method for manufacturing inner layer graph of multilayer PCB |
| CN111315158A (en) * | 2020-03-27 | 2020-06-19 | 深圳市景旺电子股份有限公司 | Circuit board manufacturing method and circuit board |
| CN115734523A (en) * | 2022-11-30 | 2023-03-03 | 珠海中京电子电路有限公司 | Method for manufacturing inner layer of high-density circuit board and application thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101080164A (en) * | 2007-06-27 | 2007-11-28 | 迈普（四川）通信技术有限公司 | Board joint method of dual-side printed circuit board |
| CN101662897A (en) * | 2009-09-04 | 2010-03-03 | 东莞美维电路有限公司 | Manufacturing method for multilayer stacking printed wiring board |
-
2010
- 2010-12-29 CN CN 201010622826 patent/CN102056414A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101080164A (en) * | 2007-06-27 | 2007-11-28 | 迈普（四川）通信技术有限公司 | Board joint method of dual-side printed circuit board |
| CN101662897A (en) * | 2009-09-04 | 2010-03-03 | 东莞美维电路有限公司 | Manufacturing method for multilayer stacking printed wiring board |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102427669B (en) * | 2011-11-15 | 2013-05-08 | 华南理工大学 | Manufacture method of dual-sided printed circuit board |
| CN102427669A (en) * | 2011-11-15 | 2012-04-25 | 华南理工大学 | Method for manufacturing double-sided printed circuit board |
| CN103429013A (en) * | 2012-05-16 | 2013-12-04 | 北大方正集团有限公司 | Multi-layer printed wiring board and manufacturing method thereof |
| CN103429013B (en) * | 2012-05-16 | 2016-05-18 | 北大方正集团有限公司 | Multilayer printed wiring board and preparation method thereof |
| CN103179807B (en) * | 2013-03-07 | 2015-12-02 | 深圳崇达多层线路板有限公司 | A kind of method improving blind buried via hole PCB warpage |
| CN103179807A (en) * | 2013-03-07 | 2013-06-26 | 深圳崇达多层线路板有限公司 | Method for improving warping of PCB (printed circuit board) by blind holes |
| CN103687315A (en) * | 2013-12-12 | 2014-03-26 | 广州兴森快捷电路科技有限公司 | Designing method of punching alignment target |
| CN103957673A (en) * | 2014-05-21 | 2014-07-30 | 赣州市深联电路有限公司 | Method for preventing copper coil from wrinkling in multi-layer board pressing process |
| CN104968150A (en) * | 2015-06-30 | 2015-10-07 | 开平依利安达电子第三有限公司 | High-layer circuit board manufactured by applying mirror symmetry and manufacturing method thereof |
| CN105632941A (en) * | 2016-02-02 | 2016-06-01 | 广州兴森快捷电路科技有限公司 | Expansion and shrinkage process control-based production method for package substrate |
| CN105632941B (en) * | 2016-02-02 | 2018-06-22 | 广州兴森快捷电路科技有限公司 | A kind of production and processing method of the package substrate based on harmomegathus process control |
| CN107708285A (en) * | 2016-08-09 | 2018-02-16 | 北大方正集团有限公司 | The preparation method of multilayer circuit board and multilayer circuit board |
| CN107708285B (en) * | 2016-08-09 | 2020-10-16 | 北大方正集团有限公司 | Multilayer circuit board and preparation method of multilayer circuit board |
| CN106231785A (en) * | 2016-08-18 | 2016-12-14 | 深圳崇达多层线路板有限公司 | Printed circuit board (PCB) pressing structure and multilayer board |
| CN107148168A (en) * | 2017-05-08 | 2017-09-08 | 江苏博敏电子有限公司 | A kind of fusion process of pressure programming |
| CN110324993A (en) * | 2019-07-29 | 2019-10-11 | 重庆伟鼎电子科技有限公司 | Circuit board pressing is to pressure |
| CN110708893A (en) * | 2019-09-30 | 2020-01-17 | 奥士康科技股份有限公司 | Method for manufacturing inner layer graph of multilayer PCB |
| CN111315158A (en) * | 2020-03-27 | 2020-06-19 | 深圳市景旺电子股份有限公司 | Circuit board manufacturing method and circuit board |
| CN115734523A (en) * | 2022-11-30 | 2023-03-03 | 珠海中京电子电路有限公司 | Method for manufacturing inner layer of high-density circuit board and application thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102056414A (en) | Manufacturing method of printed circuit board | |
| US8052881B2 (en) | Method of manufacturing multilayer printed circuit board having buried holes | |
| CN105704948B (en) | The production method of ultra-thin printed circuit board and ultra-thin printed circuit board | |
| TW201410097A (en) | Multilayer flexible printed circuit board and method for manufacturing same | |
| CN103369866B (en) | The manufacture method of a kind of printed wiring board containing blind hole and printed wiring board thereof | |
| CN103327756A (en) | Multilayer circuit board with partial mixed structure and manufacturing method thereof | |
| CN110099523A (en) | A kind of manufacture craft of multilayer circuit board | |
| CN102458053A (en) | Manufacturing method of circuit board | |
| CN103096647B (en) | The manufacture method of folding type printed circuit board (PCB) | |
| US20140318848A1 (en) | Wiring board and fabrication method therefor | |
| CN105979698A (en) | Rigid-flex circuit board and preparation method thereof | |
| CN104735923A (en) | Method for manufacturing rigidity and flexibility combined plate | |
| CN104302125A (en) | Alignment system and alignment method for high-density interconnection printed circuit board | |
| CN103889167A (en) | Method for forming via holes and embedded holes in multilayer circuit board | |
| CN105163499A (en) | Method for manufacturing stepped groove of printed circuit board (PCB) | |
| CN110072340B (en) | Manufacturing method of same-layer dual-copper circuit board | |
| US20120080137A1 (en) | Manufacturing method of circuit board | |
| CN104853542A (en) | Manufacturing method of rigid-flex printed circuit board | |
| CN102036486B (en) | Method for making false double-sided board | |
| CN110072350A (en) | Multilayer circuit board processing method | |
| CN110650597B (en) | Circuit board, manufacturing method thereof and electronic equipment | |
| CN204090296U (en) | Blind buried via hole printed circuit board (PCB) | |
| US20120152595A1 (en) | Multilayer printed circuit board and method of manufacturing the same | |
| CN220292257U (en) | Primary and secondary printed wiring board structure convenient to equipment | |
| CN222339664U (en) | Multilayer electronic circuit board and folded multilayer electronic circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20110511 |