CN102053217A - Method for quickly processing wafer after sort interruption under working condition - Google Patents
Method for quickly processing wafer after sort interruption under working condition Download PDFInfo
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- CN102053217A CN102053217A CN2009102017650A CN200910201765A CN102053217A CN 102053217 A CN102053217 A CN 102053217A CN 2009102017650 A CN2009102017650 A CN 2009102017650A CN 200910201765 A CN200910201765 A CN 200910201765A CN 102053217 A CN102053217 A CN 102053217A
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Abstract
The invention discloses a method for quickly processing a wafer after sort interruption under the working condition. The method comprises the following steps of: 1, recording real-time test results of a wafer into an appointed file in sequence during sort, and saving information of sorted chips; 2, judging whether the operation to be performed by a sort device on the wafer is fortification operation before sort of each wafer, and directly sorting each chip if the operation is not the fortification operation; 3, reading the information in the file in sequence if the operation is the fortification operation, and transmitting the information to the corresponding chips in the wafer until the information of the last chip of the former operation saved in the file; and 4, sorting the residual chips after all the tested chips are processed, and saving the sorted information into the appointed file according to the step 1. The quickly processing method can quickly process the sorted chips, so the sort efficiency is improved greatly.
Description
Technical field
The present invention relates to a kind of semiconductor test method, the method for fast processing when being specifically related to after a kind of wafer interrupt test again fortification.
Background technology
After the wafer manufacturing was finished, test was unusual important step.Test is the school report of wafer production process.In test process, the electrical ability and the circuit function of each chip all are detected.Wafer sort chip testing just (chip sort) or wafer electrical measurement (wafer sort).
When test, wafer is fixed on the chuck of pull of vacuum, and aims at very thin proving installation electroprobe, and proving installation contacts with each welded gasket of chip simultaneously.Electroprobe test circuit and note the result under the driving of power supply.Quantity, order and the type of test are controlled by computer program.Test machine is robotization, so aim at auxiliary that the test job of back (manual-alignment or use automatic vision system) need not the operator with first wafer at the proving installation electroprobe.
Test is for following three targets.The first, before wafer is delivered to encapsulation factory, identify qualified chip.The second, the electrical parameter of devices/circuits carries out characteristic evaluation.Engineers needs the distribution of monitoring parameter to keep the quality level of technology.The 3rd, the certified products of chip and the accounting of defective products provide the feedback of comprehensive achievement can for the wafer production personnel.Qualified chip and the defective products position on wafer is noted with the form of wafer figure on computers.
Wafer sort is one of main chip yields statistical method.Along with improving, area of chip increase and density makes that the expense of wafer sort is increasing.So, chip needs longer test duration and accurate more complicated power supply, mechanical hook-up and computer system to carry out test job and test results monitored.Vision inspection system also is accurate and expensive more along with chip size expansion.The designer of chip is required test pattern is introduced storage array.How the designer of test simplifies testing process more and effectively, for example uses the test procedure of simplifying in the qualified back of chip parameter assessment exploring, and the chip in addition also can the interlacing test wafer perhaps carries out the test of a plurality of chips simultaneously.
In present technology, the detecting information of wafer just uploads to test data management system after one piece of wafer sort finishes.When one piece of wafer has only been tested under a part of situation, test macro is electricity down suddenly, and the test result of then having finished will be lost.As shown in Figure 1 be the test synoptic diagram of a wafer, dash area is for having tested the part that white portion fails to test for system's reason.
Particularly chronic as some product test, reach under the situation about six hours, test means the very big loss of production capacity again.
Summary of the invention
The method of fast processing when technical matters to be solved by this invention provides after a kind of wafer interrupt test fortification again, it can improve the efficient of testing.
In order to solve above technical matters, the method for fast processing when the invention provides after a kind of wafer interrupt test again fortification; May further comprise the steps: the real-time testing result wafer in step 1, the test process records in the file of appointment successively, and preserves the information of test chip; Step 2, at each wafer before test, transmit a zone bit and give proving installation, judge whether proving installation is again that fortification are operated to the operation that this piece wafer will carry out; If not fortification operation again, directly each chip is tested; Step 3 is if fortification operation again, the information in the read step one described file successively then, and give relevant chip in the wafer, the information of last chip that operated the last time of preserving described information transmission in described file; After the chip of step 4, all tested mistakes disposes, begin remaining chip is tested, and one described detecting information is kept at the file of appointment set by step, up to end of test (EOT).
Beneficial effect of the present invention is: carry out fast processing to testing the chip that finishes, greatly improved testing efficiency.
Description of drawings
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
Fig. 1 is the synoptic diagram that wafer is tested;
Fig. 2 is the synoptic diagram of the described flow process of the embodiment of the invention.
Embodiment
The problem to be solved in the present invention is that the detecting information of wafer just uploads to test data management system after one piece of wafer sort finishes.When one piece of wafer has only been tested under a part of situation, test macro runs into down faults such as electricity suddenly, and the test result of then having finished will be lost.Particularly chronic as some product test, reach under the situation about six hours, test means the very big loss of production capacity again.
Method of the present invention is after restarting test, and the chip information of testing before quick definition finishes is finished follow-up test by normal flow process afterwards again.May further comprise the steps:
1) in test process, after each chip testing finishes, all can append in real time and preserve test result in the file of following format, the name of file is with " log number+slot number " name.Need be the test result of wafer according to the format record of table 1 in the file of appointment (" log number+slot number "), and be saved on the hard disk.
| X | 29 | Y | 63 | bin | 1 |
| X | 30 | Y | 63 | bin | 1 |
| X | 31 | Y | 63 | bin | 2 |
| X | 32 | Y | 63 | bin | 1 |
| X | 33 | Y | 63 | bin | 1 |
| X | 34 | Y | 63 | bin | 1 |
| X | 35 | Y | 63 | bin | 1 |
| X | 36 | Y | 63 | bin | 1 |
| X | 37 | Y | 63 | bin | 4 |
| X | 38 | Y | 63 | bin | 1 |
| X | 39 | Y | 63 | bin | 1 |
| X | 40 | Y | 63 | bin | 1 |
| X | 41 | Y | 63 | bin | 1 |
| X | 42 | Y | 63 | bin | 1 |
| X | 43 | Y | 63 | bin | 1 |
| X | 44 | Y | 63 | bin | 1 |
| X | 45 | Y | 63 | bin | 1 |
| X | 41 | Y | 64 | bin | 8 |
| X | 40 | Y | 64 | bin | 1 |
| X | 30 | Y | 64 | bin | 1 |
Table 1
2) each wafer all will transmit a zone bit and give proving installation before test, and whether the operation of telling this piece of proving installation wafer to carry out is again the fortification operations
3) if fortification again, then enter the flow process of this patent suggestion, this flow process has comprised the operation of the chip of testing being carried out branch bin, read row/row/stitch (X/Y/bin) information in " log number+slot number " file successively, and they are transferred to relevant chip in the wafer by general purpose interface bus GPIB, carry out the chip that last time, test finished so very soon, that is read last column of file " log number+slot number ".
4) chip of all tested mistakes is processed finish after, enter normal testing process, this flow process the inside has comprised all test events
5) if not fortification operation again, directly carry out normal testing process
6) finish until test
As shown in table 2 below, use this systems approach to carry out fast processing to testing the chip that finishes, greatly improved testing efficiency.
Table 2
The present invention is not limited to embodiment discussed above.More than the description of embodiment is intended in order to describe and illustrate the technical scheme that the present invention relates to.Based on the conspicuous conversion of the present invention enlightenment or substitute and also should be considered to fall into protection scope of the present invention.Above embodiment is used for disclosing best implementation method of the present invention, so that those of ordinary skill in the art can use numerous embodiments of the present invention and multiple alternative reaches purpose of the present invention.
Claims (2)
1. the method for fast processing during fortification again after the wafer interrupt test; It is characterized in that, may further comprise the steps:
Real-time testing result wafer in step 1, the test process records in the file of appointment successively, and preserves the information of test chip;
Step 2, at each wafer before test, transmit a zone bit and give proving installation, judge whether proving installation is again that fortification are operated to the operation that this piece wafer will carry out; If not fortification operation again, directly each chip is tested;
Step 3 is if fortification operation again, the information in the read step one described file successively then, and give relevant chip in the wafer, the information of last chip that operated the last time of preserving described information transmission in described file;
After the chip of step 4, all tested mistakes disposes, begin remaining chip is tested, and one described detecting information is kept at the file of appointment set by step, up to end of test (EOT).
2. the method for fast processing during fortification again after the wafer interrupt test as claimed in claim 1; It is characterized in that the real-time testing information of described wafer comprises the capable information of each piece chip under test, column information and stitch information.
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| CN2009102017650A CN102053217A (en) | 2009-11-05 | 2009-11-05 | Method for quickly processing wafer after sort interruption under working condition |
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| CN2009102017650A CN102053217A (en) | 2009-11-05 | 2009-11-05 | Method for quickly processing wafer after sort interruption under working condition |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104483616A (en) * | 2014-12-29 | 2015-04-01 | 上海华虹宏力半导体制造有限公司 | Classification method of chip bin maps in wafer circuit probing |
| CN112798998A (en) * | 2020-12-31 | 2021-05-14 | 杭州广立微电子股份有限公司 | A method for handling abnormal state of wafer test probe card |
| CN112834907A (en) * | 2020-12-31 | 2021-05-25 | 杭州广立微电子股份有限公司 | A Test System Supporting Log File Configuration |
| CN112989141A (en) * | 2021-03-15 | 2021-06-18 | 上海华力微电子有限公司 | Method and system for inquiring interrupted wafer batch LOT |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020000826A1 (en) * | 2000-06-30 | 2002-01-03 | Takayuki Takao | Semiconductor parametric testing apparatus |
| US6498999B1 (en) * | 2000-07-24 | 2002-12-24 | Lsi Logic Corporation | Method and apparatus for design verification of an integrated circuit using a simulation test bench environment |
| CN1767164A (en) * | 2004-10-29 | 2006-05-03 | 力晶半导体股份有限公司 | Chip testing device and chip testing method with automatic recovery function |
| CN101014049A (en) * | 2007-02-14 | 2007-08-08 | 中兴通讯股份有限公司 | Method for managing timer of terminal wireless communication protocol stack sofeware |
| CN101051959A (en) * | 2007-05-11 | 2007-10-10 | 北京邮电大学 | Detecting method for network link band width based on hop-by-hop time stamp label |
| CN101183321A (en) * | 2007-12-14 | 2008-05-21 | 中国人民解放军国防科学技术大学 | A kind of out-of-band diagnostic test interface and test method for parallel computer system |
| US20100036637A1 (en) * | 2002-05-24 | 2010-02-11 | Test Advantage, Inc. | Methods and apparatus for hybrid outlier detection |
-
2009
- 2009-11-05 CN CN2009102017650A patent/CN102053217A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020000826A1 (en) * | 2000-06-30 | 2002-01-03 | Takayuki Takao | Semiconductor parametric testing apparatus |
| US6498999B1 (en) * | 2000-07-24 | 2002-12-24 | Lsi Logic Corporation | Method and apparatus for design verification of an integrated circuit using a simulation test bench environment |
| US20100036637A1 (en) * | 2002-05-24 | 2010-02-11 | Test Advantage, Inc. | Methods and apparatus for hybrid outlier detection |
| CN1767164A (en) * | 2004-10-29 | 2006-05-03 | 力晶半导体股份有限公司 | Chip testing device and chip testing method with automatic recovery function |
| CN101014049A (en) * | 2007-02-14 | 2007-08-08 | 中兴通讯股份有限公司 | Method for managing timer of terminal wireless communication protocol stack sofeware |
| CN101051959A (en) * | 2007-05-11 | 2007-10-10 | 北京邮电大学 | Detecting method for network link band width based on hop-by-hop time stamp label |
| CN101183321A (en) * | 2007-12-14 | 2008-05-21 | 中国人民解放军国防科学技术大学 | A kind of out-of-band diagnostic test interface and test method for parallel computer system |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104483616A (en) * | 2014-12-29 | 2015-04-01 | 上海华虹宏力半导体制造有限公司 | Classification method of chip bin maps in wafer circuit probing |
| CN112798998A (en) * | 2020-12-31 | 2021-05-14 | 杭州广立微电子股份有限公司 | A method for handling abnormal state of wafer test probe card |
| CN112834907A (en) * | 2020-12-31 | 2021-05-25 | 杭州广立微电子股份有限公司 | A Test System Supporting Log File Configuration |
| CN112989141A (en) * | 2021-03-15 | 2021-06-18 | 上海华力微电子有限公司 | Method and system for inquiring interrupted wafer batch LOT |
| CN112989141B (en) * | 2021-03-15 | 2024-05-28 | 上海华力微电子有限公司 | Method and system for inquiring and interrupting LOT of wafer batch |
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Application publication date: 20110511 |