CN102074218B - Liquid crystal display system capable of improving non-uniform brightness of liquid crystal display panel - Google Patents
Liquid crystal display system capable of improving non-uniform brightness of liquid crystal display panel Download PDFInfo
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Abstract
The invention relates to a liquid crystal display system capable of improving non-uniform brightness of a liquid crystal display panel. The system comprises the liquid crystal display panel, a scanning driving circuit and a data driving circuit, wherein the liquid crystal panel is provided with a plurality of pixels; the scanning driving circuit is used for receiving a first external control signal and a second external control signal and controls the enabling sequence of a plurality of gate electrode scanning lines according to the first external control signal and the second external control signal; and the data driving circuit is coupled to the plurality of data scanning lines and is used for receiving display data, the first external control signal and the second external control signal and determining the writing sequence of the data voltage of each sub-pixel of each data scanning line according to the first external control signal and the second external control signal.
Description
Technical field
The invention relates to a kind of liquid crystal display systems, espespecially a kind of by two external control signals, to improve the liquid crystal display systems of liquid crystal panel lightness inequality.
Background technology
Please refer to Fig. 1, Fig. 1 is the synoptic diagram for prior art explanation liquid crystal display systems 100.Liquid crystal display systems 100 comprises a liquid crystal panel 102, one source pole driver (source driver) 104 and one gate pole driver (gate driver) 106, wherein a plurality of gate sweep traces GO1-GOn of a plurality of data scanning line SO1-SOn of source electrode driver 104 and gate pole driver 106 is a plurality of pixels that are coupled on the liquid crystal panel 102, and source electrode driver 104 is that the demonstration data-switching that will receive becomes data voltage, to write pixel corresponding on the liquid crystal panel 102.After the gate sweep trace GO1 among a plurality of gate sweep traces GO1-GOn is by gate pole driver 106 activations, source electrode driver 104 will discharge and recharge the voltage of corresponding GTG according to corresponding data voltage corresponding to the pixel of gate sweep trace GO1 on the liquid crystal panel 102.Please refer to Fig. 2, Fig. 2 is the synoptic diagram for the type of attachment of explanation dual-gate (dual gate) liquid crystal panel pixel.As shown in Figure 2, two adjacent pixels are to share a data sweep trace, so can reduce the quantity of the driver element in the source electrode driver 104, wherein GO1, GO2, GO3, GO4, GO5, GO6 ... for being coupled to the gate sweep trace of gate pole driver 106; SO1, SO2, SO3, SO4 ... for being coupled to the data scanning line of source electrode driver 104; R, G, B are the red, green, blue sub-pixel in each pixel.
Please refer to Fig. 3, Fig. 3 is the synoptic diagram for the dual-gate liquid crystal panel pixel of explanation 2dot polarity driven.As shown in Figure 3, in the data writing voltage time of a data scanning line, open two gate sweep trace GO1 and GO2, that is the data scanning line will be in the data writing voltage time of a data scanning line, and data writing voltage is to sub-pixel R (GO1), G (GO2) corresponding to gate sweep trace GO1 and GO2.And in the data writing voltage time of next data scanning line, open two gate sweep trace GO3 and GO4, that is the data scanning line will be in the data writing voltage time of a data scanning line, and data writing voltage is to sub-pixel R (GO3), G (GO4) corresponding to gate sweep trace GO3 and GO4.But under the trend that panel size is increasing and resolution is more and more higher now, the time that the gate sweep trace is opened relatively shortens, and has therefore shortened the time of pixel charging.Please refer to Fig. 4 A and Fig. 4 B, Fig. 4 A is for illustrating when data scanning line SO1 writes pattern antithetical phrase pixel data writing voltage with the Z-shaped data voltage, the synoptic diagram that corresponding gate sweep trace is sequentially opened, Fig. 4 B are to work as data scanning line SO1 for explanation to write pattern to the synoptic diagram of the dual-gate liquid crystal panel data writing voltage of the 2dot polarity driven of Fig. 3 with the Z-shaped data voltage.Shown in Fig. 4 A, the opening sequence of gate sweep trace is GO1 à GO2 à GO3 à GO4 à ..., therefore, the order of data scanning line data writing voltage is R (GO1) à G (GO2) à R (GO3) à G à (GO4) ....Within the time that gate sweep trace GO1 opens, the polarity of data scanning line SO1 data writing voltage is that R (GO1) not yet reaches stable state; Within the time that gate sweep trace GO2 opens, the polarity of data scanning line SO1 data writing voltage is that G (GO2) has reached stable state.In like manner, may extend to gate sweep trace GO3/GO4 corresponding to the situation of data scanning line SO1.Therefore, shown in Fig. 4 B, the charge volume of the first row sub-pixel R can be not enough as can be known, and the charge volume of the second row sub-pixel G has reached predetermined accurate position, so can be because of the different problems that form perpendicular line (vertical line) of brightness between adjacent subpixels R, the G.
Please refer to Fig. 5, Fig. 5 is the synoptic diagram for the 1+2 dot polarity driven of explanation dual-gate liquid crystal panel pixel.Different with Fig. 3 is, when data scanning line SO1 data writing voltage, and this guild's luminance shortage of sub-pixel G.In like manner, when data scanning line SO2 data writing voltage, this guild's luminance shortage of sub-pixel R.So can be because of the different problems that form perpendicular line of brightness between the adjacent subpixels.
Summary of the invention
One embodiment of the invention provide a kind of liquid crystal display systems that improves the liquid crystal panel lightness inequality.This crystalline substance display system comprises a liquid crystal panel, scan driving circuit and a data drive circuit.This liquid crystal panel has a plurality of pixels, and wherein each pixel comprises the red, green, blue sub-pixel; This scan drive circuit has one first input port and one second input port, in order to receive respectively one first external control signal and one second external control signal, and according to this first external control signal and this second external control signal, control the activation order of a plurality of gate sweep traces; And this data drive circuit is to be coupled to a plurality of data scanning lines, show data in order to receive one, this data drive circuit has one first input port and one second input port, in order to receive respectively this first external control signal and this second external control signal, and according to this first external control signal and this second external control signal, determine the write sequence of data voltage of each sub-pixel of each data scanning line.
Another embodiment of the present invention provides a kind of liquid crystal display systems that improves the liquid crystal panel lightness inequality.This crystalline substance display system comprises a liquid crystal panel, scan driving circuit and a data drive circuit.This liquid crystal panel has a plurality of pixels, and wherein each pixel comprises the red, green, blue sub-pixel; This data drive circuit is to be coupled to a plurality of data scanning lines, this data drive circuit has one first input port and one second input port, in order to receive respectively one first external control signal and one second external control signal, this data drive circuit shows data, this first external control signal and this second external control signal in order to receive one, and according to this first external control signal and this second external control signal, determine the write sequence of data voltage of each sub-pixel of each data scanning line, and produce activation order signal; Reaching this scan drive circuit is to receive this activation order signal, and according to this activation order signal, controls the activation order of a plurality of gate sweep traces.
The invention provides a kind of liquid crystal display systems that improves the liquid crystal panel lightness inequality, to utilize one first external control signal and one second external control signal, with the write sequence of the data voltage of the activation order of controlling a plurality of gate sweep traces and each sub-pixel of determining each data scanning line.Therefore, the present invention can improve a liquid crystal panel in the prior art because of the different problems that form perpendicular line of brightness.
Description of drawings
Fig. 1 is the synoptic diagram for prior art explanation liquid crystal display systems.
Fig. 2 is the synoptic diagram for the type of attachment of explanation dual-gate liquid crystal panel pixel.
Fig. 3 is the synoptic diagram for the dual-gate liquid crystal panel pixel of explanation 2dot polarity driven.
Fig. 4 A is for the synoptic diagram that corresponding gate sweep trace is sequentially opened is described when the data scanning line writes pattern antithetical phrase pixel data writing voltage with the Z-shaped data voltage.
Fig. 4 B works as the data scanning line for explanation to write pattern to the synoptic diagram of the dual-gate liquid crystal panel data writing voltage of the 2dot polarity driven of the 3rd figure with the Z-shaped data voltage.
Fig. 5 is the synoptic diagram for the dual-gate liquid crystal panel pixel of explanation 1+2 dot polarity driven.
Fig. 6 is the synoptic diagram that improves the liquid crystal display systems of liquid crystal panel lightness inequality for one embodiment of the invention explanation.
Fig. 7 A is the synoptic diagram for the explanation scan drive circuit.
Fig. 7 B is the synoptic diagram for the explanation data drive circuit.
Fig. 8 A is the synoptic diagram that concerns for the first external control signal, the second external control signal, the first multiplexer enable signal, the second multiplexer enable signal and the gate sweep trace opening sequence of explanation liquid crystal display systems.
Fig. 8 B is the synoptic diagram that writes pattern for explanation arc type data voltage.
Fig. 8 C is for the synoptic diagram that corresponding gate sweep trace is sequentially opened is described when the data scanning line writes pattern antithetical phrase pixel data writing voltage with the arc type data voltage.
Fig. 8 D is the synoptic diagram that writes pattern for explanation Z+ arc type data voltage.
Fig. 9 is the synoptic diagram that improves the liquid crystal display systems of liquid crystal panel lightness inequality for the another embodiment of the present invention explanation.
Figure 10 A is the synoptic diagram for the explanation data drive circuit.
Figure 10 B is the synoptic diagram for the counter-rotating data writing voltage that 8B figure is described.
Figure 11 is the synoptic diagram that concerns for the first external control signal of explanation liquid crystal display systems, the second external control signal, the first multiplexer enable signal, the second multiplexer enable signal and picture control signal.
Figure 12 is the synoptic diagram that improves the liquid crystal display systems of liquid crystal panel lightness inequality for the another embodiment of the present invention explanation.
Figure 13 A is the synoptic diagram for the explanation scan drive circuit.
Figure 13 B is for illustrating that scan drive circuit and data drive circuit according to activation order signal, write the synoptic diagram of pattern with the arc type data voltage.
Figure 13 C is the synoptic diagram for the explanation data drive circuit.
Figure 14 is the synoptic diagram that improves the liquid crystal display systems of liquid crystal panel lightness inequality for the another embodiment of the present invention explanation.
[primary clustering symbol description]
100,600,900,1200,1400 liquid crystal display systemss
102,602,1202 liquid crystal panels
104 source electrode drivers
106 gate pole drivers
604,1204 scan drive circuits
606,906,1206,1406 data drive circuits
6040,6060,9060,12,060 first input ports
6041,6061,9061,12,061 second input ports
9063,14063 the 3rd input ports
6042,12,042 second logical circuits
6044,12044 gate pole drivers
6046,12,046 second multiplexers
6062,9062,12062 data coding devices
6064,9064,12,064 first logical circuits
6066,9066,12066 time schedule controllers
6068,9068,12068 source electrode drivers
6070,9070,12,070 first multiplexers
ESS activation order signal
Frame picture control signal
S1, S2, S3, S4 the first multiplexer enable signal
G1, G2, G3, G4 the second multiplexer enable signal
SEL0 the first external control signal
SEL1 the second external control signal
FD the first data
The DV data voltage
DD shows data
SO1-SOn, SO2, SO3, SO4 data scanning line
GO1-GOn, GO2, GO3, GO4, GO5, GO6 gate sweep trace
R, G, B sub-pixel.
Embodiment
Please refer to Fig. 6, Fig. 6 is the synoptic diagram that improves the liquid crystal display systems 600 of liquid crystal panel lightness inequality for one embodiment of the invention explanation.Liquid crystal display systems 600 comprises a liquid crystal panel 602, scan driving circuit 604 and a data drive circuit 606.Liquid crystal panel 602 has a plurality of pixels, and wherein each pixel comprises the red, green, blue sub-pixel; Scan drive circuit 604 has one first input port 6040 and one second input port 6041, in order to receive respectively one first external control signal SEL0 and one second external control signal SEL1, and according to the first external control signal SEL0 and the second external control signal SEL1, control the activation order of a plurality of gate sweep traces GO1-GOn; Data drive circuit 606 is to be coupled to a plurality of data scanning lines SO1-SOn, show data DD in order to receive one, and data drive circuit 606 has one first input port 6060 and one second input port 6061 in addition, in order to receive respectively the first external control signal SEL0 and the second external control signal SEL1, and according to the first external control signal SEL0 and the second external control signal SEL1, determine the write sequence of data voltage of each sub-pixel of each data scanning line.For example, after the gate sweep trace GO1 among a plurality of gate sweep traces GO1-GOn is by scan drive circuit 604 activations, data drive circuit 606 will be charged to the voltage of corresponding GTG according to corresponding data voltage corresponding to the pixel of gate sweep trace GO1 on the liquid crystal panel 602.In addition, to be coupled to online the switch of each pixel be to be a thin film transistor (TFT) to the scanning of each gate.
Please refer to Fig. 7 A, Fig. 7 B and Fig. 8 A, Fig. 7 A is the synoptic diagram for explanation scan drive circuit 604, Fig. 7 B is the synoptic diagram for explanation data drive circuit 606, and Fig. 8 A is the synoptic diagram that concerns for the first external control signal SEL0, the second external control signal SEL1, the first multiplexer enable signal S1, S2, S3, S4, the second multiplexer enable signal G1, G2, G3, G4 and the gate sweep trace opening sequence of explanation liquid crystal display systems 600.Shown in 7A figure, scan drive circuit 604 comprises one second logical circuit 6042, a gate pole driver 6044 and one second multiplexer 6046.The second logical circuit 6042 is in order to according to the first external control signal SEL0 and the second external control signal SEL1, produces a plurality of the second multiplexer enable signal G1, G2, G3, G4; Gate pole driver 6044 is enable signals of exporting a plurality of gate sweep traces GO1-GOn; The second multiplexer 6046 is to be coupled to gate pole driver 6044, in order to according to the enable signal of a plurality of gate sweep traces GO1-GOn and a plurality of the second multiplexer enable signal G1, G2, G3, G4, control the activation order of a plurality of gate sweep traces GO1-GOn.Shown in Fig. 8 A, for example, when the first external control signal SEL0 and the second external control signal SEL1 are all logic low potential " 0 ", the second multiplexer enable signal G1, G2, G3, G4 are all logic low potential " 0 ", so the opening sequence of gate sweep trace is GO1 à GO2 à GO3 à GO4 à GO5 à GO6 à GO7 à GO8 ...When the first external control signal SEL0 is that logic low potential " 0 " and the second external control signal SEL1 are when being logic high potential " 1 ", the second multiplexer enable signal G1, G2, G3, G4 are all logic high potential " 1 ", so the opening sequence of gate sweep trace is GO2 à GO1 à GO4 à GO3 à GO6 à GO5 à GO8 à GO7 ...When the first external control signal SEL0 is that logic high potential " 1 " and the second external control signal SEL1 are when being logic low potential " 0 ", the second multiplexer enable signal G2, G4 are logic high potential " 1 ", the second multiplexer enable signal G1, G3 are logic low potential " 0 ", so the opening sequence of gate sweep trace is GO1 à GO2 à GO4 à GO3 à GO5 à GO6 à GO8 à GO7 ...When the first external control signal SEL0 and the second external control signal SEL1 are all logic high potential " 1 ", the second multiplexer enable signal G3, G4 are logic high potential " 1 ", the second multiplexer enable signal G1, G2 are logic low potential " 0 ", so the opening sequence of gate sweep trace is GO1 à GO2 à GO3 à GO4 à GO6 à GO5 à GO8 à GO7 ...
Shown in Fig. 7 B, data drive circuit 606 comprises a data decoder 6062, one first logical circuit 6064, time schedule controller 6066, one source pole driver 6068 and one first multiplexer 6070.Data decoder 6062 is in order to will showing that data DD is converted to one first data FD, and wherein the form of the first data FD is to be liquid crystal panel 602 displayable forms; The first logical circuit 6064 is in order to according to the first external control signal SEL0 and the second external control signal SEL1, produces a plurality of the first multiplexer enable signal S1, S2, S3, S4; Time schedule controller 6066 is to be coupled to data decoder 6062 and the first logical circuit 6064, in order to process the sequential of the first data FD; Source electrode driver 6068 is to be coupled to time schedule controller 6066, is corresponding data voltage DV in order to change the first data FD; The first multiplexer 6070 is to be coupled to source electrode driver 6068 and the first logical circuit 6064, in order to according to data voltage DV and a plurality of the first multiplexer enable signal S1, S2, S3, S4, determine the write sequence of data voltage of each sub-pixel of each data scanning line.Shown in Fig. 8 A, for example, when the first external control signal SEL0 and the second external control signal SEL1 are all logic low potential " 0 ", the first multiplexer enable signal S1, S2, S3, S4 is all logic low potential " 0 ", is the sub-pixel G (GO8) that sub-pixel R (GO7) à that sub-pixel G (GO6) à that sub-pixel R (GO5) à that sub-pixel G (GO4) à that sub-pixel R (GO3) à that sub-pixel G (GO2) à that sub-pixel R (GO1) à that is coupled to gate sweep trace GO1 is coupled to gate sweep trace GO2 is coupled to gate sweep trace GO3 is coupled to gate sweep trace GO4 is coupled to gate sweep trace GO5 is coupled to gate sweep trace GO6 is coupled to gate sweep trace GO7 is coupled to gate sweep trace GO8 so the write sequence of the data voltage of the sub-pixel on the data scanning line SO1 is the opening sequence that corresponds to the gate sweep trace.The principle of operation of remainder data sweep trace is identical with data scanning line SO1, does not repeat them here.When the first external control signal SEL0 is that logic low potential " 0 " and the second external control signal SEL1 are when being logic high potential " 1 ", the first multiplexer enable signal S1, S2, S3, S4 is all logic high potential " 1 ", is the sub-pixel R (GO7) that sub-pixel G (GO8) that sub-pixel R (GO5) à that sub-pixel G (GO6) à that sub-pixel R (GO3) à that sub-pixel G (GO4) à that sub-pixel R (GO1) à that sub-pixel G (GO2) à that is coupled to gate sweep trace GO2 is coupled to gate sweep trace GO1 is coupled to gate sweep trace GO4 is coupled to gate sweep trace GO3 is coupled to gate sweep trace GO6 is coupled to gate sweep trace GO5 is coupled to gate sweep trace GO8 is coupled to gate sweep trace GO7 so the write sequence of the data voltage of the sub-pixel on the data scanning line SO1 is the opening sequence that corresponds to the gate sweep trace.The principle of operation of remainder data sweep trace is identical with data scanning line SO1, does not repeat them here.When the first external control signal SEL0 is that logic high potential " 1 " and the second external control signal SEL1 are when being logic low potential " 0 ", the first multiplexer enable signal S2, S4 is logic high potential " 1 ", the first multiplexer enable signal S1, S3 is logic low potential " 0 ", is the sub-pixel R (GO7) that sub-pixel G (GO8) that sub-pixel G (GO6) à that sub-pixel R (GO5) à that sub-pixel R (GO3) à that sub-pixel G (GO4) à that sub-pixel G (GO2) à that sub-pixel R (GO1) à that is coupled to gate sweep trace GO1 is coupled to gate sweep trace GO2 is coupled to gate sweep trace GO4 is coupled to gate sweep trace GO3 is coupled to gate sweep trace GO5 is coupled to gate sweep trace GO6 is coupled to gate sweep trace GO8 is coupled to gate sweep trace GO7 so the write sequence of the data voltage of the sub-pixel on the data scanning line SO1 is the opening sequence that corresponds to the gate sweep trace.The principle of operation of remainder data sweep trace is identical with data scanning line SO1, does not repeat them here.When the first external control signal SEL0 and the second external control signal SEL1 are all logic high potential " 1 ", the first multiplexer enable signal S3, S4 is logic high potential " 1 ", the first multiplexer enable signal S1, S2 is logic low potential " 0 ", is the sub-pixel R (GO7) that sub-pixel G (GO8) à that sub-pixel R (GO5) à that sub-pixel G (GO6) à that sub-pixel G (GO4) à that sub-pixel R (GO3) à that sub-pixel G (GO2) à that sub-pixel R (GO1) à that is coupled to gate sweep trace GO1 is coupled to gate sweep trace GO2 is coupled to gate sweep trace GO3 is coupled to gate sweep trace GO4 is coupled to gate sweep trace GO6 is coupled to gate sweep trace GO5 is coupled to gate sweep trace GO8 is coupled to gate sweep trace GO7 so the write sequence of the data voltage of the sub-pixel on the data scanning line SO1 is the opening sequence that corresponds to the gate sweep trace.The principle of operation of remainder data sweep trace is identical with data scanning line SO1, does not repeat them here.
Please refer to Fig. 8 A, Fig. 8 B, Fig. 8 C and Fig. 8 D, Fig. 8 B is the synoptic diagram that writes pattern for explanation arc type data voltage, Fig. 8 C is for illustrating when data scanning line SO1 writes pattern antithetical phrase pixel data writing voltage with the arc type data voltage, the synoptic diagram that corresponding gate sweep trace is sequentially opened, Fig. 8 D are the synoptic diagram that writes pattern for explanation Z+ arc type data voltage.Shown in Fig. 8 B, when the first external control signal SEL0 is logic high potential " 1 " and the second external control signal SEL1 when being logic low potential " 0 ", data drive circuit 606 is opening sequence (the GO1 à GO2 à GO4 à GO3 à GO5 à GO6 à GO8 à GO7 that correspond to the gate sweep trace ...) be the pattern that writes of the data voltage of arc type.And shown in 8C figure, because the polarity of data scanning line SO1 data writing voltage is to replace for positive and negative, so can solve the perpendicular line problem of liquid crystal panel 602.
In addition, shown in Fig. 8 D, when the first external control signal SEL0 and the second external control signal SEL1 were all logic high potential " 1 ", data drive circuit 606 was opening sequence (the GO1 à GO2 à GO3 à GO4 à GO6 à GO5 à GO8 à GO7 that correspond to the gate sweep trace ...) be the pattern that writes of the data voltage of Z+ arc type.In addition, the present invention is not limited to the corresponding relation that writes pattern of the data voltage of the first external control signal SEL0, the second external control signal SEL1 of Fig. 8 A and data drive circuit 606.
In addition, when the first external control signal SEL0 and the second external control signal SEL1 were all logic low potential " 0 ", data drive circuit 606 was the patterns that write for the data voltage of Z-shaped; When the first external control signal SEL0 is logic low potential " 0 " and the second external control signal SEL1 when being logic high potential " 1 ", data drive circuit 606 is the patterns that write for the data voltage of anti-Z-shaped.Because above-mentioned two kinds of situations all have the problem of the perpendicular line in the prior art, so not in scope of the present invention.In addition, liquid crystal display systems 600 and be not suitable for the liquid crystal panel of dual-gate liquid crystal panel pixel of the 2 dot polarity driven of Fig. 3.
Please refer to Fig. 9, Fig. 9 is the synoptic diagram that improves the liquid crystal display systems 900 of liquid crystal panel lightness inequality for the another embodiment of the present invention explanation.The difference of liquid crystal display systems 900 and liquid crystal display systems 600 is that data drive circuit 906 includes one the 3rd input port 9063 in addition, in order to receive picture control signal frame, and according to picture control signal frame, counter-rotating writes the order corresponding to the data voltage of each pixel of each data scanning line.Please refer to Figure 10 A and Figure 10 B, Figure 10 A is the synoptic diagram of explanation data drive circuit 906, and Figure 10 B is the synoptic diagram for the counter-rotating data writing voltage of key diagram 8B.Shown in Figure 10 A, data drive circuit 906 comprises a data decoder 9062, one first logical circuit 9064, time schedule controller 9066, one source pole driver 9068 and one first multiplexer 9070, wherein picture control signal frame is by the first logical circuit 9064, control time schedule controller 9066 and the first multiplexer 9070 write order corresponding to the data voltage of each pixel of each data scanning line with counter-rotating.Shown in Fig. 8 B, data drive circuit 606 is the patterns that write for the data voltage of arc type, and therefore, shown in Figure 10 B, when picture control signal frame activation, data drive circuit 906 is the patterns that write for the data voltage of anti-arc type.Because, when picture control signal frame activation, data drive circuit 906 counter-rotatings write the order corresponding to the data voltage of each pixel of each data scanning line, so liquid crystal panel 902 is when showing odd number picture (or even number picture), data drive circuit 906 is nonreversible to write order corresponding to the data voltage of each pixel of each data scanning line, when showing even number picture (or odd number picture), data drive circuit 906 counter-rotatings write the order corresponding to the data voltage of each pixel of each data scanning line.Therefore, liquid crystal display systems 900 can be by the order of the data voltage of each pixel of each data scanning line of counter-rotating odd number picture or even number picture, to improve the problem of liquid crystal panel lightness inequality.Please refer to Figure 11, Figure 11 is the synoptic diagram that concerns for the first external control signal SEL0, the second external control signal SEL1 of explanation liquid crystal display systems 900, the first multiplexer enable signal S1, S2, S3, S4, the second multiplexer enable signal G1, G2, G3, G4 and picture control signal frame.But the present invention is not limited to the corresponding relation that writes pattern of the data voltage of the first external control signal SEL0 among Figure 11, the second external control signal SEL1, picture control signal frame and data drive circuit 606.In addition, liquid crystal display systems 900 is applicable to the liquid crystal panel of the 2 dot polarity driven dual-gate liquid crystal panel pixels of the liquid crystal panel of 1+2 dot polarity driven dual-gate liquid crystal panel pixel of the 5th figure and Fig. 3, and all the other principle of operation of liquid crystal display systems 900 are identical with liquid crystal display systems 600, do not carry at this and give unnecessary details.
Please refer to Figure 12, Figure 12 is the synoptic diagram that improves the liquid crystal display systems 1200 of liquid crystal panel lightness inequality for the another embodiment of the present invention explanation.Liquid crystal display systems 1200 comprises a liquid crystal panel 1202, scan driving circuit 1204 and a data drive circuit 1206.Liquid crystal panel 1202 has a plurality of pixels, and wherein each pixel comprises the red, green, blue sub-pixel; Data drive circuit 1206 is to be coupled to a plurality of data scanning lines SO1-SOn, shows data DD in order to receive one.Data drive circuit 1206 has one first input port 12060 and one second input port 12061, in order to receive respectively one first external control signal SEL0 and one second external control signal SEL1, and data drive circuit 1206 and according to the first external control signal SEL0 and the second external control signal SEL1, determine the write sequence of data voltage of each sub-pixel of each data scanning line, and produce activation order signal ESS; Scan drive circuit 1204 is to receive activation order signal ESS, and according to activation order signal ESS, controls the activation order of a plurality of gate sweep traces GO1-GOn.For example, after the gate sweep trace GO1 among a plurality of gate sweep traces GO1-GOn is by scan drive circuit 1204 activations, data drive circuit 1206 will discharge and recharge the voltage of corresponding GTG according to corresponding data voltage corresponding to the pixel of gate sweep trace GO1 on the liquid crystal panel 1202.In addition, to be coupled to online the switch of each pixel be to be a thin film transistor (TFT) to the scanning of each gate.
Please refer to Figure 13 A, Figure 13 B and Figure 13 C, Figure 13 A is the synoptic diagram for explanation scan drive circuit 1204, Figure 13 B is for illustrating that scan drive circuit 1204 and data drive circuit 1206 are according to activation order signal ESS, write the synoptic diagram of pattern with the arc type data voltage, Figure 13 C is the synoptic diagram for explanation data drive circuit 1206.As shown in FIG. 13A, scan drive circuit 1204 comprises one second logical circuit 12042, a gate pole driver 12044 and one second multiplexer 12046.The second logical circuit 12042 is in order to according to activation order signal ESS, produces a plurality of the second multiplexer enable signal G1, G2, G3, G4; Gate pole driver 12044 is enable signals of exporting a plurality of gate sweep traces GO1-GOn; And the second multiplexer 12046 is to be coupled to gate pole driver 12044, in order to according to the enable signal of a plurality of gate sweep traces GO1-GOn and a plurality of the second multiplexer enable signal G1, G2, G3, G4, control the activation order of a plurality of gate sweep traces GO1-GOn.Shown in Figure 13 B, when activation order signal ESS activation, the opening sequence of inversion scanning driving circuit 1204.Therefore, the opening sequence of gate sweep trace is GO1 à GO2 à GO4 à GO3 à GO5 à GO6 à GO8 à GO7, and data drive circuit 1206 writes pattern data writing voltage according to the opening sequence of gate sweep trace with the arc type data voltage.Shown in Figure 13 C, data drive circuit 1206 comprises a data decoder 12062, one first logical circuit 12064, time schedule controller 12066, one source pole driver 12068 and one first multiplexer 12070.Data decoder 12062 is in order to will showing that data DD is converted to one first data FD, and wherein the form of the first data FD is to be liquid crystal panel 1202 displayable forms; The first logical circuit 12064 is in order to according to the first external control signal SEL0 and the second external control signal SEL1, produces a plurality of the first multiplexer enable signal S1, S2, S3, S4 and activation order signal ESS; Time schedule controller 12066 is to be coupled to data decoder 12062 and the first logical circuit 12064, in order to process the sequential of the first data FD; Source electrode driver 12068 is to be coupled to time schedule controller 12066, is corresponding data voltage DV in order to change the first data FD; And the first multiplexer 12070 is to be coupled to source electrode driver 12068 and the first logical circuit 12064, in order to according to data voltage DV and a plurality of the first multiplexer enable signal S1, S2, S3, S4, determine the write sequence of data voltage of each sub-pixel of each data scanning line.
The difference of liquid crystal display systems 1200 and liquid crystal display systems 600 is that scan drive circuit 1204 does not have the first input port and the second input port.Therefore, the second logical circuit 12042 of scan drive circuit 1204 is according to the activation order signal ESS that is produced by data drive circuit 1206, produces a plurality of the second multiplexer enable signal G1, G2, G3, G4.In addition, all the other principle of operation of liquid crystal display systems 1200 are identical with liquid crystal display systems 600, do not carry at this and give unnecessary details.
Please refer to Figure 14, Figure 14 is the synoptic diagram that improves the liquid crystal display systems 1400 of liquid crystal panel lightness inequality for the another embodiment of the present invention explanation.The difference of liquid crystal display systems 1400 and liquid crystal display systems 1200 is that data drive circuit 1406 includes one the 3rd input port 14063 in addition, in order to receive picture control signal frame, and according to picture control signal frame, counter-rotating writes the order corresponding to the data voltage of each pixel of each data scanning line.In addition, all the other principle of operation of liquid crystal display systems 1400 are identical with liquid crystal display systems 1200, do not carry at this and give unnecessary details.
In sum, a kind of liquid crystal display systems that improves the liquid crystal panel lightness inequality provided by the present invention, to utilize the first external control signal and the second external control signal, with the write sequence of the data voltage of the activation order of controlling a plurality of gate sweep traces and each sub-pixel of determining each data scanning line.Therefore, the present invention can improve liquid crystal panel in the prior art because of the different problems that form perpendicular line (vertical line) of brightness.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (10)
1. a liquid crystal display systems that improves the liquid crystal panel lightness inequality is characterized in that, comprises:
One liquid crystal panel has a plurality of pixels, and wherein each pixel comprises the red, green, blue sub-pixel;
Scan driving circuit, have one first input port and one second input port, in order to receiving respectively one first external control signal and one second external control signal, and according to this first external control signal and this second external control signal, control the activation order of a plurality of gate sweep traces; And
One data drive circuit, be coupled to a plurality of data scanning lines, show data in order to receive one, this data drive circuit has one first input port and one second input port, in order to receive respectively this first external control signal and this second external control signal, and according to this first external control signal and this second external control signal, determine the write sequence of data voltage of each sub-pixel of each data scanning line.
2. liquid crystal display systems according to claim 1 is characterized in that, wherein this data drive circuit comprises:
One data decoder was converted to one first data in order to should show data, and wherein the form of this first data is to be the displayable form of this liquid crystal panel;
One first logical circuit in order to according to this first external control signal and this second external control signal, produces a plurality of the first multiplexer enable signals;
Time schedule controller is coupled to this data decoder and this first logical circuit, in order to process the sequential of this first data;
The one source pole driver is coupled to this time schedule controller, is corresponding data voltage in order to change this first data; And
One first multiplexer is coupled to this source electrode driver and this first logical circuit, in order to according to this data voltage and these a plurality of first multiplexer enable signals, determines the write sequence of data voltage of each sub-pixel of each data scanning line.
3. liquid crystal display systems according to claim 1 is characterized in that, wherein this scan drive circuit comprises:
One second logical circuit in order to according to this first external control signal and this second external control signal, produces a plurality of the second multiplexer enable signals;
One gate pole driver is in order to export the enable signal of these a plurality of gate sweep traces; And
One second multiplexer is coupled to this gate pole driver, in order to the enable signal and these a plurality of second multiplexer enable signals according to these a plurality of gate sweep traces, controls the activation order of these a plurality of gate sweep traces.
4. liquid crystal display systems according to claim 1, it is characterized in that: wherein this data drive circuit includes one the 3rd input port in addition, in order to receive picture control signal, and according to this picture control signal, counter-rotating writes the order corresponding to the data voltage of each pixel of each data scanning line.
5. liquid crystal display systems according to claim 1 is characterized in that: wherein to be coupled to the switch of each pixel be to be a thin film transistor (TFT) to each gate sweep trace.
6. a liquid crystal display systems that improves the liquid crystal panel lightness inequality is characterized in that, comprises:
One liquid crystal panel has a plurality of pixels, and wherein each pixel comprises the red, green, blue sub-pixel;
One data drive circuit, be coupled to a plurality of data scanning lines, show data in order to receive one, this data drive circuit has one first input port and one second input port, in order to receive respectively one first external control signal and one second external control signal, and according to this first external control signal and this second external control signal, determine the write sequence of data voltage of each sub-pixel of each data scanning line, and produce activation order signal; And
Scan driving circuit in order to receiving this activation order signal, and according to this activation order signal, is controlled the activation order of a plurality of gate sweep traces.
7. liquid crystal display systems according to claim 6 is characterized in that, wherein this data drive circuit comprises:
One data decoder was converted to one first data in order to should show data, and wherein the form of this first data is to be the displayable form of this liquid crystal panel;
One first logical circuit in order to according to this first external control signal and this second external control signal, produces a plurality of the first multiplexer enable signals and this activation order signal;
Time schedule controller is coupled to this data decoder and this first logical circuit, in order to process the sequential of this first data;
The one source pole driver is coupled to this time schedule controller, is corresponding data voltage in order to change this first data; And
One first multiplexer is coupled to this source electrode driver and this first logical circuit, and in order to according to this data voltage and these a plurality of first multiplexer enable signals, the pixel that this data voltage is corresponding discharges and recharges the voltage of a corresponding GTG.
8. liquid crystal display systems according to claim 6 is characterized in that, wherein this scan drive circuit comprises:
One second logical circuit in order to according to this activation order signal, produces a plurality of the second multiplexer enable signals;
One gate pole driver is in order to export the enable signal of these a plurality of gate sweep traces; And
One second multiplexer is coupled to this gate pole driver, in order to the enable signal and these a plurality of second multiplexer enable signals according to these a plurality of gate sweep traces, controls the activation order of these a plurality of gate sweep traces.
9. liquid crystal display systems according to claim 6, it is characterized in that, wherein this data drive circuit includes one the 3rd input port in addition, in order to receive picture control signal, and according to this picture control signal, counter-rotating writes the order corresponding to the data voltage of each pixel of each data scanning line.
10. liquid crystal display systems according to claim 6 is characterized in that, wherein to be coupled to the switch of each pixel be to be a thin film transistor (TFT) to each gate sweep trace.
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| CN 201110045100 CN102074218B (en) | 2011-02-25 | 2011-02-25 | Liquid crystal display system capable of improving non-uniform brightness of liquid crystal display panel |
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| CN102737591A (en) * | 2011-04-12 | 2012-10-17 | 联咏科技股份有限公司 | Gate driver of dual-gate display and frame control method thereof |
| CN103943075A (en) * | 2013-01-23 | 2014-07-23 | 联咏科技股份有限公司 | Gate driving circuit and gate line driving method of display panel |
| TWI559277B (en) * | 2015-04-15 | 2016-11-21 | Display and its scanning method | |
| CN109817150A (en) * | 2019-03-28 | 2019-05-28 | 京东方科技集团股份有限公司 | Pixel driving method, pixel driving device and display device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101055708A (en) * | 2007-05-09 | 2007-10-17 | 友达光电股份有限公司 | Driving method |
| CN101533610A (en) * | 2008-03-11 | 2009-09-16 | 深圳安凯微电子技术有限公司 | Method and chip for controlling red, green and blue scanning sequences output to liquid crystal display |
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| TWI373030B (en) * | 2007-10-19 | 2012-09-21 | Au Optronics Corp | Shift register, gate driving circuit with bi-directional transmission function, and lcd with double frame rate |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101055708A (en) * | 2007-05-09 | 2007-10-17 | 友达光电股份有限公司 | Driving method |
| CN101533610A (en) * | 2008-03-11 | 2009-09-16 | 深圳安凯微电子技术有限公司 | Method and chip for controlling red, green and blue scanning sequences output to liquid crystal display |
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Effective date of registration: 20170807 Address after: 1#, building third, fourth, 6 West Road, Mawei West Road, Mawei District, Fujian, Fuzhou Co-patentee after: Chunghwa Picture Tubes Ltd. Patentee after: CPT DISPLAY TECHNOLOGY (SHENZHEN)CO., LTD. Address before: 350015, Xingye Road, Mawei Science Park, Fujian, Fuzhou 1, China Co-patentee before: Chunghwa Picture Tubes Ltd. Patentee before: Fujian Huaying Display Technology Co., Ltd. |
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