CN102075430B - Compression and message matching method for deep message detection deterministic finite automation (DFA) state transfer tables - Google Patents
Compression and message matching method for deep message detection deterministic finite automation (DFA) state transfer tables Download PDFInfo
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Abstract
The invention relates to a compression and message matching method for deep message detection deterministic finite automation (DFA) state transfer tables. Before network equipment carries out seven-layer deep detection on the messages, a character library described in regular expression is needed to be converted into the DFA state transfer table, and the table is generally very large and is difficult to store and to realize high-speed message matching. In the method, a bitmap coding mode is used to compress the DFA state transfer table, a compressible part can be stored in a high-speed memory after being compressed, and an incompressible part is stored in a dynamic random access memory (DRAM), so the storage space occupied by the DFA state transfer table is effectively reduced, and the high-speed message matching is easily realized.
Description
Technical field
The present invention relates to data communication field, particularly the Network Security Device field is specifically related to the method that a kind of compression and message to the DFA state-transition table that is applied to the deep message detection matees.
Background technology
Have numerous architectures in the computer network, for the interconnect problem of the network that solves different architecture, the ISO of International Standards Organization formulated open systems interconnection reference model in 1981.This model is divided into 7 layers to the work of network service; They are respectively physical layer (Physical Layer) from low to high; Data link layer (Data Link Layer), network layer (Network Layer), transport layer (Transport Layer); Session layer (Session Layer), presentation layer (Presentation Layer) and application layer (Application Layer).Three layers of ground floors to the belong to low three layers of OSI Reference Model, are responsible for creating the link that network service connects; The 4th layer is the high four layers of OSI Reference Model to layer 7, is specifically responsible for data communication end to end.
Traditional Network Security Device is only analyzed four layers and following content of message, i.e. information such as source IP address, purpose IP address, source port number, destination slogan, protocol type.But this technology has very large limitation, and plurality of applications cannot not be fixing the TCP/UDP port, therefore only analyzes four layers of message and following content and does not discern these application.In addition, network invasion monitoring, virus detect etc. also must analyze message more than four layers to seven layers content.
Therefore, present Network Security Device all trends towards using deep packet inspection technology to analyze message content and behavior thereof.Promptly use the feature database of describing by regular expression to come recognition application classification, network intrusions behavior, virus etc.Before software or hardware carry out the matching characteristic storehouse to message, need convert regular expression to NFA (non-definite state automata) state-transition table or DFA (confirming state automata) state-transition table so that search and mate.
Wherein the memory space of NFA state-transition table is less, but is not suitable for the high-speed message coupling.
The DFA state-transition table and converting the DFA state-transition table to, regular expression has the space explosion problem, because need take a large amount of memory spaces.Take a large amount of memory spaces and just must use outside DRAM, like DDR/DDR2/DDR3 DRAM.Because the characteristic of DRAM need be opened during visit DRAM memory cell and close the inner ranks of DRAM, the random access data need the time of tens nanoseconds, so the message matching speed can't adapt to the flow of a plurality of gigabit networking interfaces.
Summary of the invention
To the problems referred to above; The applicant has carried out improving research; Provide a kind of deep message to detect the compression and the message matching process of DFA state-transition table, can effectively reduce the memory space that the DFA state-transition table takies, and suitable hardware circuit is realized the high-speed message coupling.
Technical scheme of the present invention is following:
A kind of deep message detects the compression and the message matching process of DFA state-transition table; To each row of DFA state-transition table, close input character that transfering state is identical and transfering state thereof are with (bebinning character, bitmap; Transfering state) tlv triple is represented, deposits in the high-speed memory; When searching the transfering state of input character, PARALLEL MATCHING is with the tlv triple of delegation.
Its further technical scheme is:
Following steps are carried out in the compression of DFA state-transition table successively:
1) to each statusline, the input character that transfering state is identical is divided into same group;
2) to each statusline, with dividing adjacent and contiguous input character and transfering state thereof to represent with (bebinning character, bitmap, transfering state) tlv triple at same group; Wherein bebinning character is minimum input character in dividing into groups; Bitmap calculates the deviant of each input character of this group with respect to bebinning character with binary representation, with on the bitmap with the corresponding bit position 1 of these deviants, all the other bit positions 0;
3),, encode by a plurality of said tlv triple when dividing when same group input character can not be encoded by single said tlv triple to each statusline;
4) to each statusline, if the number of its said tlv triple that comprises is no more than preset threshold values, then this statusline leaves in the high-speed memory with the mode of above-mentioned tlv triple coding; Otherwise this statusline does not compress, and is stored among the outer DRAM of sheet with the mode of one-dimensional linear array;
5) state value is remapped, make and to deposit the state value that the state value deposited in the high-speed memory of tlv triple is all deposited less than the outer DRAM of sheet; Minimum in the state value that the outer DRAM of sheet is deposited is as cut off value;
The message coupling is carried out following steps successively:
6) with the initial state of DFA state-transition table and message initial character as initial input;
7) if this state be final state finish the coupling; If state value is less than said cut off value, then execution in step 8 is searched the high-speed memory of depositing tlv triple; Otherwise execution in step 9 is searched the outer DRAM of sheet;
8) according to the mode of one-dimensional linear array indexing, from the high-speed memory of depositing tlv triple, read all tlv triple coding of this statusline, bitmap bit offset value in each tlv triple coding is put 1 character and this message character and mate; If match, the next character of transfering state and message of then getting this character place tlv triple is as input, execution in step 7; If do not match any tlv triple, then coupling failure and end;
9), outside sheet, read corresponding transfering state the DRAM according to the mode of two-dimensional linear array indexing; If transfering state is arranged, the next character of then getting this transfering state and message is as input, execution in step 7; If there is not transfering state, then coupling failure and end.
And its further technical scheme is:
Said each bitmap accounts for 4 ~ 16 bits, and the width of each bitmap is fixed.
The threshold values that said each statusline comprises the tlv triple number is 2 ~ 32.
Said tlv triple can leave in the interior high-speed memory of sheet or in the outer high-speed memory of sheet, said high-speed memory comprises SRAM.
Useful technique effect of the present invention is:
The present invention is based on identical these two characteristics of sparse and close input character transfering state of DFA state-transition table; Adopt the tlv triple coded system of bebinning character, bitmap, transfering state; Can effectively compress the DFA state-transition table; Thereby compression section is put into high-speed memory, effectively reduce the outer DRAM memory space requirements of sheet.In addition, the DFA state-transition table leaves in and also helps hardware realization high-speed message coupling in the high-speed memory.
Description of drawings
Fig. 1 realizes hardware configuration sketch map of the present invention.
Embodiment
Further specify below in conjunction with the accompanying drawing specific embodiments of the invention.
Table 1 shows the DFA state-transition table of existing employing standard two-dimensional linear storage of array form.
As shown in table 1, abscissa 0 ~ 255th, input character (8 bit widths, totally 256), ordinate S (0) ~ S (N) is a state.Under this state of each line display, the transfering state of corresponding each input character.If input character does not have transfering state, the failure of just expression coupling also finishes.According to two-dimensional linear addressable array mode, use (state, input character) to find transfering state from the DFA state-transition table as index.
Through the analysis of DFA state-transition table that many regular expressions are converted to, can find two characteristics: a) table is sparse, and promptly quite most of (state, input character) do not have transfering state; B) to same state, the transfering state of many adjacent or contiguous input characters is identical.Based on above-mentioned two characteristics, the present invention adopts the bitmap coded mode to come the DFA state-transition table is compressed.
Table 2 shows the DFA state-transition table that adopts bitmap coded compression memory form of the present invention.
In order to realize being compressed to table 2 from table 1, the concrete compression method of the present invention is following:
Step 1) is divided into groups input character to each statusline, and the input character that transfering state is identical is divided into same group.
Step 2), representes with (bebinning character, bitmap, transfering state) tlv triple dividing at same group transfering state identical and adjacent or contiguous input character and transfering state to each statusline.
Bebinning character is minimum input character in dividing into groups.Bitmap is with binary representation, and low bit on the right.Calculate the deviant of the input character of this group with respect to bebinning character, with on the bitmap with the corresponding bit position 1 of these deviants, all the other bit positions 0.
Step 3) can be 4 ~ 16 bits because the width of bitmap is fixed.Therefore to each statusline,, can encode by a plurality of tlv triple when dividing when same group input character can not be encoded by single (bebinning character, bitmap, transfering state) tlv triple.The form that final each statusline of formation is encoded by one or more (bebinning character, bitmap, transfering state) tlv triple.
Step 4) is to each statusline, if the number of above-mentioned tlv triple is no more than certain preset threshold values (such as 8 or 16), then this statusline is stored in the on-chip SRAM with the mode of above-mentioned tlv triple coding; Otherwise this statusline does not compress, and is stored among the outer DRAM of sheet with the mode of one-dimensional linear array.
Through above-mentioned compression step, can the compressible portion of DFA state-transition table be left in the on-chip SRAM, incompressible part is placed among the outer DRAM of sheet.
Step 5) remaps to state value simultaneously, makes the DFA state value that the DFA state value deposited in the on-chip SRAM is all deposited less than the outer DRAM of sheet.So only need with a cut off value (being the minimum in the state value deposited of the outer DRAM of sheet) relatively size can the differentiation state be to leave in the on-chip SRAM, still leave in outside the sheet among the DRAM.
Come compression method of the present invention is specified through a real example below.
Table 3 shows the DFA state-transition table fragment of the uncompressed of a reality.
As shown in table 3, be 16 o'clock in current state, input character 5,7,8,11 corresponding transfering states are 17, and input character 6,9,10,12 corresponding transfering states are 23, and other input character does not have transfering state.
At first this statusline is divided into groups to input character by transfering state, promptly input character 5,7,8,11 is as a grouping, and input character 6,9,10,12 divides into groups as another, minimum input character 5 and 6 in bebinning character is respectively and divides into groups.
Each input character deducts bebinning character and obtains deviant in will dividing into groups, and is 1 with the bit position of this deviation post of bitmap, and other bit position of bitmap is 0.Such as the grouping that for input character is 5,7,8,11, bebinning character is 5, and respectively each character being calculated deviant is 5-5=0,7-5=2,8-5=3,11-5=6.Then 0,2 of bitmap, 3,6 bit positions are 1, obtain 01001101 (bitmap is with binary representation, low bit on the right, promptly rightmost is the 0th bit, Far Left is the 7th bit).For input character is 6,9,10,12 grouping, also adopts the formation bitmap that uses the same method.
After this DFA state-transition table compresses tlv triple (bebinning character, bitmap, transfering state) encoding compression through bitmap; State 16 corresponding row finally can be encoded into following two tlv triple: (5,01001101,17), (6; 01011001,23), leaves in the on-chip SRAM.
Suppose that each state value takies 4 bytes, the byte that each statusline of then original DFA state-transition table takies is: 4*256=1024.
Suppose that bitmap field takies a byte, each tlv triple takies 6 bytes, and every row fixedly tlv triple number is 8, and the byte that each statusline that then uses bitmap of the present invention to compress the DFA state-transition table of tlv triple coding takies is: 8*6=48.Memory space requirements greatly reduces.
Corresponding with above-mentioned compression, the concrete message matching process of the present invention is following:
Step 6) with the initial state of DFA state-transition table and message initial character as initial input.
If this state of step 7) is a final state, then finish coupling; If state value is less than cut off value, then execution in step 8 is searched on-chip SRAM; Otherwise execution in step 9 is searched the outer DRAM of sheet.
Step 8) is according to the mode of one-dimensional linear array indexing, from on-chip SRAM, reads all tlv triple codings of this statusline, bitmap bit offset value in each tlv triple coding put 1 character and this message character and matees; If match, the next character of transfering state and message of then getting this character place tlv triple is as input, execution in step 7; If do not match any tlv triple, then coupling failure and end.
Step 9) reads corresponding transfering state according to the mode of two-dimensional linear array indexing the DRAM outside sheet; If transfering state is arranged, the next character of then getting this transfering state and message is as input, execution in step 7; If there is not transfering state, then coupling failure and end.
Fig. 1 shows and realizes hardware configuration sketch map of the present invention.As shown in Figure 1; The feature database that CPU describes regular expression converts the DFA state-transition table to; And use the bitmap coded mode of this patent invention to compress, and compression section is write in the ASIC/FPGA on-chip SRAM, compression section does not write among the outer DRAM of ASIC/FPGA sheet.Concrete compression step is described with above-mentioned technical scheme.The ASIC/FPGA Memory Controller Hub is accomplished the read-write sequence control of SRAM and DRAM.ASIC/FPGA message matching module is responsible for message is removed to mate the DFA state-transition table that leaves among on-chip SRAM and the outer DRAM of sheet.Concrete message coupling step is described with above-mentioned technical scheme.
It should be noted that among the present invention that after compression tlv triple not only can leave in the sheet in the high-speed memory (like SRAM), also can leave in the outer high-speed memory of sheet.And this high-speed memory also can select the other forms of memory of speed more than existing DRAM for use except that adopting SRAM, and in the future through the high-speed DRAM of new generation of technological innovation.
Above-described only is preferred implementation of the present invention, the invention is not restricted to above embodiment.Be appreciated that other improvement and variation that those skilled in the art directly derive or associate under the prerequisite that does not break away from spirit of the present invention and design, all should think to be included within protection scope of the present invention.
Claims (4)
1. a deep message detects the compression and the message matching process of DFA state-transition table; It is characterized in that: to each row of DFA state-transition table; Close input character that transfering state is identical and transfering state thereof are with (bebinning character; Bitmap, transfering state) tlv triple is represented, is deposited in the high-speed memory; When searching the transfering state of input character, PARALLEL MATCHING is with the tlv triple of delegation;
Following steps are carried out in the compression of DFA state-transition table successively:
1) to each statusline, the input character that transfering state is identical is divided into same group;
2) to each statusline, with dividing adjacent or contiguous input character and transfering state thereof to represent with (bebinning character, bitmap, transfering state) tlv triple at same group; Wherein bebinning character is minimum input character in dividing into groups; Bitmap calculates the deviant of each input character of this group with respect to bebinning character with binary representation, with on the bitmap with the corresponding bit position 1 of these deviants, all the other bit positions 0;
3),, encode by a plurality of said tlv triple when dividing when same group input character can not be encoded by single said tlv triple to each statusline;
4) to each statusline, if the number of its said tlv triple that comprises is no more than preset threshold values, then this statusline leaves in the high-speed memory with the mode of above-mentioned tlv triple coding; Otherwise this statusline does not compress, and is stored among the outer DRAM of sheet with the mode of one-dimensional linear array;
5) state value is remapped, make and to deposit the state value that the state value deposited in the high-speed memory of tlv triple is all deposited less than the outer DRAM of sheet; Minimum in the state value that the outer DRAM of sheet is deposited is as cut off value;
The message coupling is carried out following steps successively:
6) with the initial state of DFA state-transition table and message initial character as initial input;
7) if this state be final state finish the coupling; If state value is less than said cut off value, then execution in step 8 is searched the high-speed memory of depositing tlv triple; Otherwise execution in step 9 is searched the outer DRAM of sheet;
8) according to the mode of one-dimensional linear array indexing, from the high-speed memory of depositing tlv triple, read all tlv triple coding of this statusline, bitmap bit offset value in each tlv triple coding is put 1 character and this input character and mate; If match, the next character of transfering state and message of then getting this character place tlv triple is as input, execution in step 7; If do not match any tlv triple, then coupling failure and end;
9), outside sheet, read corresponding transfering state the DRAM according to the mode of two-dimensional linear array indexing; If transfering state is arranged, the next character of then getting this transfering state and message is as input, execution in step 7; If there is not transfering state, then coupling failure and end.
2. detect the compression and the message matching process of DFA state-transition table according to the said deep message of claim 1, it is characterized in that: said each bitmap accounts for 4 ~ 16 bits, and the width of each bitmap is fixed.
3. detect the compression and the message matching process of DFA state-transition table according to the said deep message of claim 1, it is characterized in that: the threshold values that said each statusline comprises the tlv triple number is 2 ~ 32.
4. detect the compression and the message matching process of DFA state-transition table according to the said deep message of claim 1, it is characterized in that: said tlv triple can leave in the interior high-speed memory of sheet or in the outer high-speed memory of sheet, said high-speed memory comprises SRAM.
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| CN102387050A (en) * | 2011-12-13 | 2012-03-21 | 曙光信息产业(北京)有限公司 | System and method utilizing automata to achieve message depth detection |
| CN102868571B (en) * | 2012-08-07 | 2015-04-08 | 华为技术有限公司 | Method and device for rule matching |
| CN102932203B (en) * | 2012-10-31 | 2015-06-10 | 东软集团股份有限公司 | Method and device for inspecting deep packets among heterogeneous platforms |
| CN103685221A (en) * | 2013-09-05 | 2014-03-26 | 北京科能腾达信息技术股份有限公司 | A network invasion detection method |
| CN103685224A (en) * | 2013-09-05 | 2014-03-26 | 北京安博达通科技有限责任公司 | A network invasion detection method |
| CN104023000A (en) * | 2013-09-05 | 2014-09-03 | 田玥 | Network intrusion detection method |
| CN103560878B (en) * | 2013-09-30 | 2017-02-01 | 东软集团股份有限公司 | DFA operation method and system based on DPI signature features |
| CN103957012B (en) * | 2014-04-18 | 2017-06-06 | 华为技术有限公司 | A kind of compression method and device of DFA matrixes |
| CN104104557B (en) * | 2014-06-24 | 2017-03-22 | 北京天融信科技有限公司 | Deep packet detection device orienting IPv6 security gateway |
| CN111382327B (en) * | 2020-05-29 | 2020-09-04 | 湖南戎腾网络科技有限公司 | Character string matching device and method |
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