CN102104376B - Phase generating device and phase generating method - Google Patents

Abstract

The invention discloses a phase generation device and a phase generation method, and is capable of reducing the power consumption of a circuit during operation substantially, and improving the glitch phenomenon, generated during an operation process, of the circuit. The phase generation device disclosed by the invention comprises a phase selection unit and a phase generation unit. The phase selection unit is used for selecting one of a plurality of input frequencies according to a part of bits of a digital signal in order to generate a reference frequency, wherein the input frequencies have different phases respectively. The phase generation unit is used for eliminating the frequency of the reference frequency, and selectively carrying out delay treatment on the frequency-eliminated reference frequency according to the other part of bits of the digital signal in order to generate an output frequency.

Description

Phase generating device and phase generating method

technical field

The invention relates to a phase generating device and its related method, especially a digital phase generating device and its related method.

Background technique

Please refer to Figure 1. FIG. 1 is a schematic diagram of a conventional phase generator 10 . For example, the phase generator 10 can be a phase digital-to-analog converter (Phase DAC). Conventionally, the phase generator 10 generates a phase in an analog manner. Furthermore, the phase generator 10 is used to interpolate two differential input clocks (CLK0+, CLK0−, CLK1+, CLK1−) with different phases to generate an output clock CLK2 with a new phase. The phase generator 10 includes a first differential pair of transistors M1, M2, a second differential pair of transistors M3, M4, a first load 12, a second load 14, a first reference current source 16 and a second Reference current source 18, wherein the gate terminals Na and Nb of the transistors M1 and M2 of the first differential pair respectively receive a first positive input frequency CLK0+ and a first negative input frequency CLK0- of the first differential input frequency, and the second differential input frequency The gate terminals Nc and Nd of the dynamic pair transistors M3 and M4 respectively receive a second positive input frequency CLK1+ and a second negative input frequency CLK1 − of the second differential input frequency. The first reference current source 16 and the second reference current source 18 respectively provide a first current I1 and a second current I2 to the first differential pair transistors M1 , M2 and the second differential pair transistors M3 , M4 . Please note that the coupling relationship between each component in the phase generator 10 has been shown in FIG. 1 , and will not be repeated here.

The phase generator 10 interpolates the output frequency CLK2 with a new phase according to the magnitude relationship between the first current I1 and the second current I2 , as shown in FIG. 2 . FIG. 2 shows a timing diagram of the differential input frequencies (CLK0+, CLK0−, CLK1+, CLK1−) and output frequencies (CLK2+, CLK2−) of the phase generator 10 . The first positive input frequency CLK0+ and the first negative input frequency CLK0- are respectively input to the gate terminal Na and Nb at the time point ta, and the second positive input frequency CLK1+ and the second negative input frequency CLK1- are respectively input to the gate terminal Nc at the time point td , Nd. If both the first current I1 and the second current I2 can be divided into ten equal parts, then when the ratio between the first current I1 and the second current I2 is 5:5, then the phase of the output frequency (CLK2+, CLK2-) It will be just in the middle of the first differential input frequency (CLK0+, CLK0-) and the second differential input frequency (CLK1+, CLK1-), that is, the transition of the output frequency (CLK2+, CLK2-) appears at time Click on tc. When the ratio between the first current I1 and the second current I2 is 9:1, the transition of the output frequency ( CLK2 + , CLK2 − ) occurs at the time point tb. In other words, when the first current I1 is larger, the phase of the output frequency (CLK2+, CLK2−) is closer to the first differential input frequency (CLK0+, CLK0−). Conversely, when the second current I2 is larger, the phase of the output frequency (CLK2+, CLK2-) will be closer to the second differential input frequency (CLKI+, CLK1-), and so on. In this way, when both the first current I1 and the second current I2 can be divided into ten equal parts, the phase generator 10 can generate the Ten different phases. However, since the phase generator 10 generates different phases in a current steering manner, the phase generator 10 has relatively high power consumption. Therefore, how to improve the power consumption of a phase generator has become an urgent problem to be solved in the field of mixed signals.

Contents of the invention

The technical problem to be solved by the present invention is to provide a phase generating device and a phase generating method, which can greatly reduce the power consumption of the circuit during operation, and can also improve the glitch phenomenon generated during the operation of the circuit. .

In order to solve the above technical problems, the present invention provides the following technical solutions:

The invention provides a phase generating device. The phase generation device includes a phase selection unit and a phase generation unit. The phase selection unit is used for selecting one of the plurality of input frequencies according to some bits of the digital signal to generate a reference frequency, wherein the input frequencies have different phases respectively. The phase generation unit is used for frequency division of the reference frequency, and selectively performs delay processing on the divided reference frequency according to another part of the digital signal to generate the output frequency.

The present invention also provides a phase generation method for generating an output frequency with a desired phase according to a digital signal, the phase generation method comprising the following steps: (a) providing a complex input frequency, and according to a portion of the digital signal bit, select one of the input frequencies to generate a reference frequency, wherein the input frequencies respectively have different phases; (b) divide the reference frequency to generate a frequency-divided reference frequency: and (c) selectively performing delay processing on the frequency-divided reference frequency according to another part of the digital signal to generate the output frequency.

The phase generating device and the phase generating method adopted in the present invention can avoid using the known current driving (current steering) circuit because the phase converting device is implemented in the form of a digital circuit, so the phase generating devices 100, 800 can greatly The reduction of power consumption of the circuit during operation. On the other hand, through the selection circuit 106 and its related method disclosed in the present invention, the phase generating device 100, 800 can further improve the glitch phenomenon generated during the operation of the circuit.

Description of drawings

FIG. 1 is a schematic diagram of a conventional phase generator.

FIG. 2 is a timing diagram of generating a differential input frequency and an output frequency of the converter of FIG. 1 .

FIG. 3 is a schematic diagram of an embodiment of a phase generating device according to the present invention.

FIG. 4 is a schematic diagram of an embodiment of a selection circuit of the phase generating device in FIG. 3 .

Fig. 5 is a plurality of input frequencies, a first selected input frequency, a first frequency, a first frequency division frequency, a second frequency, a reference frequency and a fifth frequency division of the phase generating device of Fig. 3 Frequency timing diagram.

FIG. 6 is a timing diagram of a second frequency, a second frequency division frequency, the first output frequency, the fifth frequency division frequency and a sixth frequency division frequency of the phase generating device shown in FIG. 3 .

7 is a timing diagram of the first output frequency, a second output frequency, an output signal, a selection signal, a control signal and an output frequency of the selection circuit of the phase generator shown in FIG. 3 .

FIG. 8 is a schematic diagram of another embodiment of the phase generating device of the present invention.

[Description of main component symbols]

10 phase generators

12, 14 load

16, 18 reference current source

100, 800 phase generating device

102, 104, 802, 804 frequency generating device

106, 806 selection circuit

108 reference phase generation circuit

1021, 1041, 1082, 8021, 8041, 8082 phase selector

1022, 1024, 1026, 1042, 1044, 1046, 8023, 8043 inverters

1023, 1025, 1043, 1045, 1084, 1086, 8022, 8042, 8084 frequency dividers

1062 multiplexer

1064 control signal generation circuit

1064a AND gate

1064b buffer

210, 410 phase selection unit

220, 230, 420, 430, 820, 840 phase generation unit

Detailed ways

Please refer to Figure 3. FIG. 3 is a schematic diagram of an embodiment of a phase generating device 100 according to the present invention. The phase generator 100 uses a plurality of input frequencies Sin to convert a digital signal into an output frequency Sout with a specific output phase, wherein the specific output phase corresponds to the digital signal. These input frequencies Sin have different input phases respectively, wherein the input phases of each input frequency Sin and the input phases of its adjacent input frequencies Sin have substantially the same phase difference. For example, if there are 8 input frequencies Sin (ie Sin1-Sin8), these 8 input frequencies Sin can be used to represent 8 different input phases. Therefore, in order to describe the spirit of the present invention more clearly, the following description about the phase generating device 100 is based on the input frequency Sin of 8 different input phases and the digital signal based on 6 bits (that is, (b5, b4, b3, b2 , b1, b0)), generating an output frequency Sout with a specific output phase as an example for illustration.

In the embodiment of FIG. 3 , the phase generating device 100 includes a first and a second frequency generating device 102 , 104 , a selection circuit 106 and a reference phase generating circuit 108 . The first frequency generating device 102 generates a first output frequency Sc1 with a first output phase P1 according to the input frequency Sin and a first digital signal Sd1 . The second frequency generating device 104 generates a second output frequency Sc2 with a second output phase according to the input frequency Sin and a second digital signal Sd2. The selection circuit 106 is coupled to the first and second frequency generating devices 102 and 104, and is used to generate the first and second output frequencies respectively from the first and second frequency generating devices 102 and 104 according to a selection signal Sup One of Sc1 and Sc2 is selected as the output frequency Sout. The reference phase generating circuit 108 is used to provide at least one reference phase to the first and second frequency generating devices 102 and 104 as reference phases of the first output phase P1 and the second output phase P2. In this embodiment, the second output frequency Sc2 generated by the second frequency generating device 104 is the output frequency Sout currently output by the phase generating device 100, and the first output frequency Sc1 generated by the first frequency generating device 102 is The phase generator 100 then outputs the output frequency Sout. In other words, the selection circuit 106 is used to switch the second output frequency Sc2 currently used as the output frequency Sout to the first output frequency Sc1 according to the selection signal Sup to be the output frequency Sout to be output next.

The first frequency generation device 102 includes a first phase selection unit 210 , a first phase generation unit 220 , and a second phase generation unit 230 . The first phase selection unit 210 selects one of the input frequencies Sin according to some bits of the first digital signal Sd1 to generate a reference frequency (ie, the first frequency Ssc1 in the embodiment of FIG. 3 ). The first phase generating unit 220 divides the reference frequency, and then selectively delays the divided reference frequency according to another part of the first digital signal Sd1. The second phase generating unit 230 then divides the output frequency of the first phase generating unit 220, and selectively divides the frequency-divided output of the first phase generating unit 220 according to another part of the first digital signal Sd1. The frequency is delayed. In the embodiment of FIG. 3 , the first phase selection unit 210 includes a first phase selector 1021 and a first inverter 1022 . The first phase generating unit 220 includes a first frequency divider 1023 and a second inverter 1024 . The second phase generating unit 230 includes a second frequency divider 1025 and a third inverter 1026 . Wherein, the first inverter 1022, the second inverter 1024 and the third inverter 1026 are used for delaying the phase by 180 degrees. The first phase selector 1021 is used to select a first selected input frequency Ss1 having a first corresponding phase Ps1 among the input frequencies Sin according to digital signals (b5, b4, b3, b2, b1, b0), And output the first selected input frequency Ss1, where b5 is the most significant bit (MostSignificant Bit) in the digital signal (b5, b4, b3, b2, b1, b0), and b0 is the digital signal (b5, b4, b3, The least significant bit (Least Significant Bit) in b2, b1, b0), and so on. Further, the first phase selector 1021 selects one of the input frequencies Sin according to a first bit set in the digital signal (b5, b4, b3, b2, b1, b0) as the first Select the input frequency Ss1. The first inverter 1022 is coupled to the first phase selector 1021, and is used to selectively select the first input according to a second bit set in the digital signal (b5, b4, b3, b2, b1, b0). The frequency Ss1 is subjected to an inversion process to generate a first frequency Ssc1. In the present invention, the first set of bits includes at least one least significant bit of the digital signal (b5, b4, b3, b2, b1, b0), and the first inverter 1022 according to at least one significant bit of the second set of bits bits to selectively invert. Furthermore, in this embodiment, the first bit sets the bits (b2, b1, b0) in the coefficient bit signal (b5, b4, b3, b2, b1, b0). Since the 8 input frequencies Sin have 8 different input phases, the first phase selector 1021 selects one of the corresponding input frequencies from the input frequencies Sin according to the (b2, b1, b0) bits. And the second bit sets the b3 bit in the coefficient bit signal (b5, b4, b3, b2, b1, b0). When the b3 bit is a high level bit, the first inverter 1021 inverts the first selected input frequency Ss1 to generate the first frequency Ssc1. Conversely, when the b3 bit is a low level bit, the first inverter 1021 does not perform inversion processing, but directly outputs the selected input frequency Ss1 as the first frequency Ssc1.

The first frequency divider 1023 is coupled to the first inverter 1022 and is used for performing a frequency division operation on the first frequency Ssc1 to generate a first frequency division frequency Sdc1. The second inverter 1024 is coupled to the first frequency divider 1023, and is used to selectively divide the first frequency Sdc1 according to the bit b4 in the digital signal (b5, b4, b3, b2, b1, b0). Inverting is performed to generate a second frequency Ssc2 with a second phase Ps2. When the second inverter 1024 does not invert the first frequency division frequency Sdc1, the first frequency division frequency Sdc1 is the second frequency Ssc2. When the second inverter 1024 inverts the first frequency division frequency Sdc1, the output of the second inverter 1024 is the second frequency Ssc2. The second frequency divider 1025 receives the second frequency Ssc2 and is used for performing a frequency division operation on the second frequency Ssc2 to generate a second frequency division frequency Sdc2. The third inverter 1026 is coupled to the second frequency divider 1025, and is used to selectively divide the second frequency Sdc2 according to the bit b5 in the digital signal (b5, b4, b3, b2, b1, b0). The inversion process is performed to generate the first output frequency Sc1 with the first output phase P1. When the third inverter 1026 does not invert the second frequency division frequency Sdc2, the second frequency division frequency Sdc2 is the first output frequency Sc1. When the third inverter 1026 inverts the second frequency division frequency Sdc2, the output of the third inverter 1026 is the first output frequency Sc1.

The second frequency generation device 104 includes a second phase selection unit 410 , a third phase generation unit 420 , and a fourth phase generation unit 430 . The second phase selection unit 410 includes a second phase selector 1041 and a fourth inverter 1042 . The third phase generating unit 420 includes a third frequency divider 1043 and a fifth inverter 1044 . The fourth phase generating unit 430 includes a fourth frequency divider 1045 and a sixth inverter 1046 . The second frequency generating device 104 is based on a digital signal (c5, c4, c3, c2, c1, c0) to generate a second output frequency Sc2, and its detailed operating principle is the same as the aforementioned first frequency generating device 102, I won't repeat them here.

Please refer to FIG. 4 , which is a schematic diagram of an embodiment of the selection circuit 106 of the phase generating device 100 in FIG. 3 . The selection circuit 106 includes a multiplexer 1062 and a control signal generation circuit 1064 . The multiplexer 1062 has a first terminal N1 and a second terminal N2 respectively coupled to the first and second frequency generators 102 and 104, for outputting from the first output frequency Sc1 and the second frequency according to a control signal Se One of the two output frequencies Sc2 is selected as the output frequency Sout. The control signal generating circuit 1064 is used for generating the control signal Se according to the first output frequency Sc1 and the second output frequency Sc2 and the selection signal Sup. In this embodiment, the control signal generating circuit 1064 includes an AND gate (ANDGate) 1064a and a register 1064b. The AND gate 1064a has two input terminals N3 and N4 for respectively receiving the first output frequency Sc1 and the second output frequency Sc2, and an output terminal N5 for outputting an output signal Sn5. The register 1064b has a data input terminal D for receiving the selection signal Sup, a frequency control terminal CK coupled to the AND gate 1064a for receiving the output signal Sn5, and a data output terminal Q for outputting the control signal Se.

In this embodiment, since the digital signal input to the phase generating device 100 has 6 bits, the output frequency Sout generated by the phase generating device 100 can have 64 different phase options. On the other hand, since the phase generating device 100 of this embodiment needs to generate an output frequency Sout with a frequency of 100 MHz from 8 phases of 8 input frequencies Sin with a frequency of 400 MHz, the output frequency Sout can have 64 different phases. Therefore, the first frequency divider 1023 and the second frequency divider 1025 respectively perform a frequency division operation of dividing by two on the first frequency Ssc1 and the second frequency Ssc2 . Similarly, the third frequency divider 1043 and the fourth frequency divider 1045 will also perform frequency division operation of dividing by two on the third frequency Ssc3 and the fourth frequency Ssc4 respectively. The detailed operation and function of the phase generating device 100 are further described in the following paragraphs.

Please refer to FIG. 5. FIG. 5 is the timing sequence of the eight input frequencies Sin, the first selected input frequency Ss1, the first frequency Ssc1, the first frequency-dividing frequency Sdc1, and the second frequency Ssc2 of the phase generator 100 shown in FIG. picture. In order to describe the spirit of the present invention more clearly, the phase generating device 100 of this embodiment uses digital signals (b5, b4, b3, b2, b1, b0) as (0, 0, 0, 0, 0, 0) and (1, 1, 1, 1, 1, 1) for illustration, the frequency of each of the input frequencies Sin is 400MHz, and the frequency of the first output frequency Sc1 is 100MHz. Therefore, when the input frequencies Sin are input to the phase generating device 100, between time points t1-t2, that is, within the half cycle of the first input frequency Sin1 among the input frequencies Sin, there will be 8 different phases. When the digital signal (b5, b4, b3, b2, b1, b0) is (0, 0, 0, 0, 0, 0), the first phase selector 1021 is based on the digital signal (0, 0, 0, 0 , 0, 0) in the first bit set (b2, b1, b0) (ie (0, 0, 0)) to select one of the input frequencies Sin. Since the first specific bit set (0, 0, 0) corresponds to the first input frequency Sin1 of the input frequencies Sin, the first phase selector 1021 will select the input frequency Sin1 as the first selected Input frequency Ss1. Next, the first inverter 1022 is used to selectively adjust the first selected input frequency Ss1 according to the second bit set (ie b3=0) in the digital signal (0, 0, 0, 0, 0, 0). Perform reverse processing. Since the second bit set b3 is a low-level bit, the first inverter 1021 does not invert the first selected input frequency Ss1, and directly outputs (bypass) the first selected input frequency Ss1 as the first selected input frequency Ss1. A frequency Ssc1. In this way, the first frequency Ssc1 with the first corresponding phase Ps1_(0, 0, 0, 0, 0, 0) (relative to the time point t1) is generated.

On the other hand, when the digital signal (b4, b3, b2, b1, b0) is (1, 1, 1, 1, 1, 1), the first phase selector 1021 according to the digital signal (1, 1, 1, 1, 1, 1) in the first bit set (b2, b1, b0) (ie (1, 1, 1)) to select one of the input frequencies Sin. Since the first bit set (1, 1, 1) corresponds to the input frequency Sin8 of the input frequencies Sin, the first phase selector 1021 selects the input frequency Sin8 as the first selected input frequency Ss1. Next, the first inverter 1022 is used to selectively convert the first selected input frequency Ss1 according to the second bit set (ie b3=1) in the digital signal (1, 1, 1, 1, 1, 1). Perform reverse processing. Since the second bit set b3 is a high-level bit, the first inverter 1022 inverts the first selected input frequency Ss1, and outputs the inverted input frequency Sin8 (ie, Sin8_bar) is the first frequency Ssc1. In this way, a first frequency Ssc1 with a first corresponding phase Ps1_(1, 1, 1, 1, 1, 1) (phase at time point t3 relative to time point t1) is generated, as shown in FIG. 5 shown. In other words, since each of the input frequencies Sin can be processed through inversion to generate 8 input frequencies corresponding to the other 8 phases, the output frequency of the first inverter 1022 (that is, the first The frequency Ssc1) can then have 16 different phase options (relative to the time point t1).

Next, the first frequency Ssc1 is divided by two by the first frequency divider 1023 to generate the first frequency division frequency Sdc1. Taking the digital signal (b5, b4, b3, b2, b1, b0) as an example (0, 0, 0, 0, 0, 0), since the digital signal (b5, b4, b3, b2, b1, b0) Bit b4 in is a low level bit, so the second inverter 1024 does not invert the first frequency division frequency Sdc1 and directly outputs (bypass) the first frequency division frequency Sdc1 as the second frequency Ssc2. In this way, the second frequency Ssc2 with the second phase Ps2_(0, 0, 0, 0, 0, 0) (relative to the time point t1) is generated. On the other hand, when the digital signal (b5, b4, b3, b2, b1, b0) is (1, 1, 1, 1, 1, 1) as an example, since the digital signal (b5, b4, b3, b2, The bit b4 in b1, b0) is a high level bit, so the second inverter 1024 will invert the first frequency division frequency Sdc1 to generate an inverted first frequency division frequency Sdc1 (that is, Sdc1_bar ), and output the inverted first frequency division frequency Sdc1 as the second frequency Ssc2. In this way, the second frequency Ssc2 generated by the second inverter 1024 has a second phase Ps2_(1, 1, 1, 1, 1, 1) (time point t4 relative to time point t1). In other words, when the first frequency Ssc1 generated by the first inverter 1022 is divided by the first frequency divider 1023, the frequency of the first frequency division Sdc1 will be 200 MHz, and according to the digital signals (b5, b4, b3, b2, b1, b0), the phase system of the first frequency division frequency Sdc1 can have 16 different phase options. Similarly, since each input frequency can be processed by the second inverter 1024 to generate 16 frequencies corresponding to the other 16 different phases, the second frequency Ssc2 output by the second inverter 1024 The phase can have 32 different phase options. Please note that the frequency of the second frequency Ssc2 with 32 possible phases is also 200 MHz.

Then, the second frequency Ssc2 with the second phase Ps2 and a frequency of 200 MHz is sent to the second frequency divider 1025 to generate the second frequency division frequency Sdc2. Please refer to Figure 6. FIG. 6 is a timing diagram of the second frequency Ssc2 , the second frequency-dividing frequency Sdc2 and the first output frequency Sc1 of the phase generator 100 shown in FIG. 3 . Similarly, when the digital signal (b5, b4, b3, b2, b1, b0) is (0, 0, 0, 0, 0, 0) as an example, since the digital signal (b5, b4, b3, b2, b1 , b0) bit b5 is a low level bit, so the third inverter 1026 does not invert the second frequency division frequency Sdc2 and directly outputs the second frequency division frequency Sdc2 as the first output frequency Sc1. In this way, the first output frequency Sc1 with the output phase P1_(0, 0, 0, 0, 0, 0) (relative to the time point t1) is generated. On the other hand, when the digital signal (b5, b4, b3, b2, b1, b0) is (1, 1, 1, 1, 1, 1) as an example, since the digital signal (b5, b4, b3, b2, The bit b5 in b1, b0) is a high level bit, so the third inverter 1026 will invert the second frequency division frequency Sdc2 to generate an inverted second frequency division frequency Sdc2 (that is, Sdc2_bar ), and output the inverted second frequency division frequency Sdc2 as the first output frequency Sc1. In this way, the first output frequency Sc1 with the output phase P1_(1, 1, 1, 1, 1, 1) (time point t5 relative to the time point t1) can be generated. In other words, when the second frequency Ssc2 is divided by the third frequency divider 1026, the frequency of the second frequency division Sdc2 will be 100 MHz, and according to the digital signals (b5, b4, b3, b2, b1, b0) value, the phase system of the second division frequency Sdc2 can have 32 different phase options. Similarly, since each input frequency can be processed by the third inverter 1026 to generate 32 frequencies corresponding to another 32 different phases, the first output frequency output by the third inverter 1026 The phase of Sc1 can have 64 different phase options. Please note that the frequency of the first output frequency Sc1 with 64 different phases will also be 100 MHz. It can be known from the above-disclosed operation process that when multiple frequencies with multiple different phases respectively pass through a circuit composed of a frequency divider and an inverter, it will generate double phase selection. Therefore, those skilled in the art should understand that the present invention is not limited to using only two sets of frequency dividers and inverters (that is, a set of first frequency dividers enclosed by dashed line 1022a). 1023 and the second inverter 1024, and the other group is composed of the second frequency divider 1025 and the third inverter 1026 included in the dotted line 1022b), after appropriate modification, the phase generating device 100 can also be According to a specific number of phases, any multiple of the specific number of output phases is generated.

In addition, the reference phase generating circuit 108 includes a third phase selector 1082 , a fifth frequency divider 1084 and a sixth frequency divider 1086 . The third phase selector 1082 is used to select an input frequency from the input frequencies Sin as a reference frequency Sref. The fifth frequency divider 1084 is coupled to the third phase selector 1082 for performing a frequency division operation on the reference frequency Sref to generate a fifth frequency division frequency Sdc5. The sixth frequency divider 1086 is coupled to the fifth frequency divider 1084 for performing a frequency division operation on the fifth frequency division frequency Sdc5 to generate a sixth frequency division frequency Sdc6. Please note that, in this embodiment, the fifth frequency divider 1084 and the sixth frequency divider 1086 perform a division by two operation on the reference reference frequency Sref and the fifth frequency division frequency Sdc5 respectively. In addition, for convenience, the third phase generator 1082 in this embodiment selects the first input frequency Sin1 from the input frequencies Sin as the reference frequency Sref, but the present invention is not limited thereto.

Please refer to FIG. 3 , FIG. 5 and FIG. 6 at the same time. When the phase generating device 100 receives these input frequencies Sin, since the first input frequency Sin1 is the first frequency input to the phase generating device 100 among the input frequencies Sin, the third phase selector 1082 uses the first The phase of an input frequency Sin1 (that is, the time point t1) is used as the reference point of the phase of the first frequency Ssc1. In other words, when the digital signal (b5, b4, b3, b2, b1, b0) is (0, 0, 0, 0, 0, 0) as an example, the first corresponding phase Ps1_(0 , 0, 0, 0, 0, 0) is synchronized with the phase of the reference frequency Sref (ie the time point t1). Taking the digital signal (b5, b4, b3, b2, b1, b0) as (1, 1, 1, 1, 1, 1) as an example, the first corresponding phase Ps1_(1, 1 of the first specific input frequency Ssc1 , 1, 1, 1, 1) (that is, the time point t3) has a maximum phase difference with the phase of the reference frequency Sref. Next, the fifth frequency divider 1084 divides the reference frequency Sref by one and two to generate the fifth frequency division frequency Sdc5, and at the same time, the first frequency divider 1023 and the second inverter 1024 generate according to the first frequency Ssc1 The second frequency Ssc2. Because when an input frequency with an input phase is subjected to a frequency division operation through a frequency divider, a frequency division output phase of a frequency division output frequency generated by the frequency divider may not be synchronized with the frequency division output phase of the input frequency. The input phases (for example, differ by 180°), so in order to make the first frequency division frequency Sdc1 generated by the first frequency divider 1023 have a unified reference phase, the first frequency divider 1023 will be based on the frequency generated by the fifth frequency divider 1084. The phase of the fifth frequency division frequency Sdc5 is a reference point (such as time point t1) to generate the second frequency Ssc2, so that the phase difference between the reference frequency Sref and the first frequency Ssc1 is substantially equal to the fifth frequency division frequency Sdc5 and The phase difference between the second frequencies Ssc2. Similarly, in order to make the second frequency division frequency Sdc2 generated by the second frequency divider 1025 have a unified reference reference phase, the second frequency divider 1025 will be based on the sixth frequency division frequency Sdc6 generated by the sixth frequency divider 1086 The phase is a reference point (such as time point t1) to generate the first output frequency Sc1, so that the phase difference between the fifth frequency division frequency Sdc5 and the second frequency Ssc2 is substantially equal to the sixth frequency division frequency Sdc6 and the first output frequency Phase difference between Sc1.

On the other hand, the second frequency generating device 104 of the phase generating device 100 in this embodiment will also receive the input frequencies Sin, and based on the digital signals (c5, c4, c3, c2, c1, c0) and the input frequencies Sin to generate a second output frequency Sc2 with a second output phase. Please note that since the operation of the second frequency generating device 104 is substantially similar to that of the first frequency generating device 102 , it will not be repeated here. However, in order to describe the spirit of the present invention more clearly, in this embodiment, digital signals (b5, b4, b3, b2, b1, b0)=(0, 0, 0, 0, 0, 0) and (c5, c4 , c3, c2, c1, c0)=(0, 0, 0, 0, 1, 0) is taken as an example to illustrate the operation of the selection circuit 106 . Please refer to Figure 7. 7 is a timing diagram of the first output frequency Sc1, the second output frequency Sc2, the output signal Sn5, the selection signal Sup, the control signal Se and the output frequency Sout of the selection circuit 106 of the phase generator 100. When the output frequency Sout currently output by the phase generating device 100 corresponds to (c5, c4, c3, c2, c1, c0) = (0, 0, 0, 0, 1, 0) (that is, generated by the second frequency device 104), and the output frequency Sout to be output next corresponds to (b5, b4, b3, b2, b1, b0)=(0,0,0,0,0,0) (that is, by the first When a frequency generating device 102 generates), the selection signal Sup will first switch from a low voltage level to a high voltage level at the time point te. Then, the first output frequency Sc1 corresponding to (b5, b4, b3, b2, b1, b0)=(0, 0, 0, 0, 0, 0) will be input into the multiplexer 1062 at time point tf and Door 1064a. Then, the first output frequency Sc1 and the second output frequency Sc2 are simultaneously at the high voltage level at the time point tg, so the output signal Sn5 is also switched from the low voltage level to the high voltage level at the time point tg. At this time, The control signal Se of the register 1064b is also switched from a low voltage level to a high voltage level. Therefore, at the time point tg, the output of the multiplexer 1062 will be from the second output corresponding to (c5, c4, c3, c2, c1, c0) = (0, 0, 0, 0, 1, 0) The frequency Sc2 is switched to the first output frequency Sc1 corresponding to (b5, b4, b3, b2, b1, b0)=(0, 0, 0, 0, 0, 0). Then, at the time point th, the output signal Sn5 is switched from the high voltage level to the low voltage level to maintain the control signal Se of the register 1064b at the high voltage level. In this way, after the time point tg, the output frequency Sout of the phase generating device 100 can be switched from the second output frequency Sc2 to the first output frequency Sc1. Please note that, between the time points te and tg, since the voltage of the output terminal N6 of the multiplexer 1062 remains unchanged, that is, remains at a high voltage level, it does not switch from a high voltage level to a low voltage level. The voltage level is switched from a low voltage level to a high voltage level, so the output terminal N6 does not actually change the voltage level. In other words, when the output frequency Sout of the phase generating device 100 is switched from the second output frequency Sc2 to the first output frequency Sc1 at the time point tg, the glitch (Glitch) phenomenon on the output terminal N6 of the phase generating device 100 can be It has been greatly improved.

Please note that those skilled in the art should understand that the phase generating device 100 of the present invention is not limited to using the first and second frequency generating devices 102 , 104 and the selection circuit 106 to generate the output frequency Sout. Through appropriate modifications, the phase generating device 100 can also generate a plurality of output frequencies Sout with multiple sets of the first and second frequency generating devices 102 , 104 and the selection circuit 106 . In addition, the phase generating device 100 of the present invention is not limited to using a two-to-one (Two-to-one) multiplexer 1062 in combination with the first and second frequency generating devices 102, 104 to generate the output frequency Sout. As a modification, the phase generator 100 can also combine a plurality of frequency generators (eg, three frequency generators) with multiplexers to generate the output frequency Sout. On the other hand, although the first phase generator 1021 of the phase generating device 100 uses 8 phases in a half cycle (Half cycle) to generate 16 phases in a full cycle (Full cycle) for illustration, it is not used as where the limitations of the invention lie. The phase generator 100 of the present invention can also directly generate the output frequency Sout with the input frequencies Sin having 16 phases in a full cycle, as shown in FIG. 8 .

FIG. 8 is a schematic diagram of another embodiment of a phase generating device 800 according to the present invention. In the embodiment of FIG. 8 , the phase generating device 800 includes a first and a second frequency generating device 802 , 804 , a selection circuit 806 and a reference phase generating circuit 808 . The first frequency generator 802 generates a first output frequency with a first output phase according to the input frequencies Sin' and a first digital signal Sd1' (ie (d4, d3, d2, d1, d0)). Sc1'. The second frequency generator 804 generates a second output frequency with a second output phase according to the input frequencies Sin' and a second digital signal Sd2' (ie (e4, e3, e2, e1, e0)). Sc2'. The selection circuit 806 is coupled to the first and second frequency generating devices 802 and 804, and is used to generate the first and second outputs from the first and second frequency generating devices 802 and 804 respectively according to a selection signal Sup' One of the frequencies Sc1' and Sc2' is selected as the output frequency Sout'. The reference phase generating circuit 808 is used to provide at least one reference phase to the first and second frequency generating devices 802 and 804 as reference phases of the first output phase and the second output phase. In addition, the first frequency generating device 802 includes a first phase selector 8021 and a first phase generating unit 820 . The first phase selector 8021 is used for selecting a selected input frequency Ssc1' with a corresponding phase from the input frequencies Sin' according to the first digital signal Sd1'. The first phase generating unit 820 includes a first frequency divider 8022 and a first inverter 8023 . The first frequency divider 8022 is coupled to the first phase selector 8021, and is used for performing a frequency division operation on the selected input frequency Ssc1' to generate a first frequency division frequency Sdc1'. The first inverter 8023 is coupled to the first frequency divider 8022, and is used for selectively inverting the first frequency division frequency Sdc1' according to one bit (ie d4) of the first digital signal Sd1' processed to generate a first output frequency Sc1' having a first output phase P1'. Similarly, the second frequency generating device 804 also includes a second phase selector 8041 and a second phase generating unit. The second phase generation unit includes a second frequency divider 8042 and a second inverter 8043 . In addition, the reference phase generating circuit 808 includes: a third phase selector 8082 for selecting an input frequency from the input frequencies Sin' as a reference frequency Sref'; and a third frequency divider 8084, Coupled to the third phase generator 8082, it is used to perform a frequency division operation on the reference frequency Sref' to generate a third frequency division frequency Sdc3'; wherein the first frequency divider 8022 and the second frequency divider 8042 use the third The phase of the frequency division frequency Sdc3' is a reference phase to generate the first frequency division frequency Sdc1' and the second frequency division frequency Sdc2' respectively. The selection circuit 806 is used to switch the second output frequency Sc2' currently used as the output frequency Sout' to the first output frequency Sc1' according to the selection signal Sup' to be the output frequency Sout' to be output next.

Further, in this embodiment, these input frequencies Sin' are frequencies with 16 different phases under the condition of a full cycle, therefore, the first, second, and third phases of the phase generating device 800 in this embodiment The selectors 8021, 8041, and 8082 select a phase from the 16 phases in the full period of the input frequency Sin', so that the corresponding first inverter 1022 and the fourth inverter in the phase generating device 100 can be omitted 1042. Furthermore, for the sake of simplicity, the phase generating device 800 is based on five-bit digital signals (that is, the first digital signal Sd1'(d4,d3,d2,d1,d0) and the second digital signal Sd2'(e4,e3 , e2, e1, e0)) to generate an output frequency Sout' with a corresponding phase, wherein the four bits (d3, d2, d1, d0) of the first digital signal Sd1' are provided to the first phase selector 8021 to Select an input frequency with a corresponding phase from the 16 input frequencies Sin, the bit d4 of the first digital signal Sd1' is provided to the first frequency divider 8022, and the four bits (e3, e2) of the second digital signal Sd2' , e1, e0) are provided to the second phase selector 8041 to select an input frequency with a corresponding phase from the 16 input frequencies Sin', and bit e4 of the second digital signal Sd2' is provided to the second frequency divider 8042. With reference to the technical content taught about the phase generating device 100, since the digital signal of the phase generating device 800 has 5 bits, the output frequency Sout' generated by the phase generating device 800 can have 32 different phase options, and the output frequency Sout The frequency of ' is 100MHz (the frequency of these input frequencies Sin' is 200MHz). Please note that since the operation of the phase generating device 800 is similar to that of the phase generating device 100 , the detailed operation process thereof will not be repeated here.

In summary, the embodiments disclosed in the present invention use a digital circuit to generate a phase conversion device. As mentioned above, since the implementation of the phase conversion device in the form of a digital circuit can avoid the use of a conventional current steering (current steering) circuit, the phase generating device 100, 800 of the present invention can greatly reduce the operating time of the circuit. time power consumption. On the other hand, through the selection circuit 106 and its related method disclosed in the present invention, the phase generating device 100, 800 can further improve the glitch phenomenon generated during the operation of the circuit.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (11)

1. A phase generating device for generating an output frequency with a required phase according to a digital signal, characterized in that the phase generating device includes: A phase selection unit selects one of a plurality of input frequencies according to partial bits of the digital signal to generate a reference frequency, wherein the input frequencies have different phases respectively; and a phase generating unit, used for dividing the reference frequency, and selectively performing delay processing on the divided reference frequency according to another part of the digital signal, so as to generate the output frequency; Wherein, the phase generation unit includes: a frequency divider for dividing the reference frequency; and A delay unit selectively delays the frequency-divided reference frequency according to the other part of the digital signal to generate the output frequency, and the delay unit is composed of an inverter. 2. The phase generating device according to claim 1, wherein the phase selection unit comprises: a phase selector for selecting one of the input frequencies according to the portion of the bit of the digital signal; and A delay unit selectively delays the selected input frequency according to another part of the part of the digital signal to generate the reference frequency. 3. The phase generating device according to claim 1, wherein the phase selection unit comprises a phase selector, which selects one of the input frequencies according to the part of the digital signal to become the reference frequency. 4. The phase generating device according to claim 3, further comprising: a reference phase selector for selecting one of the input frequencies as a reference frequency; and Another frequency divider is used to perform a frequency division process on the reference frequency to generate a frequency-divided reference frequency; Wherein the frequency divider generates the frequency-divided reference frequency based on the phase of the frequency-divided reference frequency. 5. The phase generating device as claimed in claim 1, further used for generating another output frequency with a desired phase according to another digital signal, characterized in that the phase generating device further comprises: Another phase selection unit selects one of the input frequencies according to some bits of the other digital signal to generate another reference frequency; Another phase generation unit is used to divide the other reference frequency, and according to another part of the digital signal, selectively delay the frequency-divided another reference frequency to generate the other output frequency; and A selection circuit selects and outputs one of the output frequency and the other output frequency according to a selection signal. 6. The phase generating device according to claim 5, wherein the selection circuit comprises: a control signal generating circuit, which generates a control signal according to the output frequency, the other output frequency and the selection signal; and A multiplexer receives the output frequency and the other output frequency, and selects and outputs one of the output frequency and the other output frequency according to the control signal. 7. A phase generating method for generating an output frequency with a required phase according to a digital signal, characterized in that the phase generating method comprises: (a) providing complex input frequencies, and selecting one of the input frequencies according to some bits of the digital signal to generate a reference frequency, wherein the input frequencies respectively have different phases; (b) dividing the reference frequency to generate a divided reference frequency: and (c) selectively delaying the divided reference frequency according to another part of the digital signal to generate the output frequency; wherein, In step (c), an inverter is used to delay the frequency-divided reference frequency. 8. phase generating method as claimed in claim 7, is characterized in that, step (a) comprises: select one of the input frequencies according to the portion of the bit of the digital signal; and The selected input frequency is selectively delayed according to another part of the part of the digital signal to generate the reference frequency. 9. The phase generation method according to claim 7, wherein in step (a), one of the input frequencies is selected according to the part of the digital signal to be the reference frequency. 10. The phase generation method according to claim 7, further comprising: select one of the input frequencies as a reference frequency; and performing a frequency-dividing process on the reference frequency to generate a frequency-divided reference frequency; Wherein step (b) is based on the phase of the frequency-divided reference frequency to generate the frequency-divided reference frequency. 11. The phase generating method as claimed in claim 7, further used for generating another output frequency with a desired phase according to another digital signal, characterized in that the phase generating method further comprises: select one of the input frequencies based on a portion of the other digital signal to generate another reference frequency; dividing the other reference frequency, and selectively delaying the divided another reference frequency according to another part of the digital signal to generate the other output frequency; and Select and output one of the output frequency and the other output frequency according to a selection signal.

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