CN102109874B - Multi-path signal generator - Google Patents

Abstract

The present invention discloses a multi-channel signal generator 2, which includes a control system 20 with a clock unit 27, and a first channel unit 28 and a second channel unit 29 that are independent of each other, and the first channel unit 28 passes through a The first isolation unit 271 is connected to the control system 20, the second channel unit 29 is connected to the control system 20 through a second isolation unit 272, and the first channel unit 28 includes a first state control terminal 287 connected to the first isolation unit 271 , the second channel unit 29 includes a second state control terminal 297 connected to the second isolation unit 272, the control system 20 includes a synchronization control terminal 261 connected to the first isolation unit 271 and the second isolation unit 272, in the first After the state control terminal 287 outputs a first state signal and the second state control terminal 297 outputs a second state signal, the synchronization control terminal 261 outputs a synchronization output signal. The electrical isolation among multiple channels of the multi-channel signal generator of the present invention can meet the requirement of high-frequency output.

Description

Multiplexer

technical field

The invention relates to a multi-channel signal generator, in particular to a multi-channel signal generator which can output independently or coupled output of a plurality of channels.

Background technique

As a common excitation source, signal generators have been widely used in scientific research and industrial engineering. When it is necessary to obtain multiple signals with the same waveform, the same frequency, and a fixed phase difference, a multiple signal generator is required.

The Chinese Patent Application Publication No. CN1831541A titled "A Multi-channel Synchronous Sinusoidal Signal Generator" discloses a multi-channel signal generator. Please refer to FIG. 1 , the multi-channel signal generator 1 disclosed in this patent includes a direct digital synthesis clock source 1 , a waveform memory 2 , an interface control circuit 3 , a controller 4 and multiple digital-to-analog conversion channels 5 . The controller 4 is respectively connected to the input end of the direct digital synthesis clock source 1 and the interface control circuit 3, and controls the direct digital synthesis clock source 1 to generate a clock signal with adjustable frequency, and the clock signal passes through the interface control circuit 3 and a plurality of digital analog The conversion channel 5 is connected, and a plurality of digital-to-analog conversion channels 5 are connected to the output end of the interface control circuit 3, and the waveform output by the waveform memory 2 is connected to a plurality of digital-to-analog conversion channels 5 through the interface control circuit 3; under the control of the controller 4 Next, the digital-to-analog converters in the multiple digital-to-analog conversion channels 5 are controlled by the interface control circuit 3 to sequentially and cyclically convert the data stored in the waveform memory 2 or the starting position of the data or the integers to extract the data in the waveform memory 2 .

Please refer to Fig. 2, the direct digital synthesis clock source 1 is made up of DDS chip 11, crystal oscillator 12, controller interface 13, low-pass filter 14 and low-pass filter 15, and DDS chip 11 can adopt the series DDS chip of ADI Company , such as AD9852, etc., AD9852 is used in the multi-channel signal generator 1, AD9852 is the core of the synthesized frequency adjustable clock source, the crystal oscillator 12 provides a reference clock for AD9852, and the controller 4 adjusts the clock frequency generated by AD9852 through the controller interface 13 , low-pass filter 14 and low-pass filter 15 are used to filter out the high-order harmonics of the output signal of AD9852, and connect the output signal to the input terminal of the comparator integrated in AD9852, and the output terminal of the comparator generates multiple signals Frequency adjustable clock signal required by generator 1. Please refer to Fig. 3, interface control circuit 3 adopts FPGA to realize, and it comprises clock distribution circuit 6, waveform data register 7 and waveform memory read-write control circuit 8, and clock distribution circuit 6 is the digital in a plurality of digital-to-analog conversion channels 5 The analog converter provides the clock signal, and the controller 4 reads and writes the data in the waveform memory 2 through the waveform memory read-write control circuit 8, and under the control of the controller 4, the data in the waveform memory 2 is output to the Multiple digital-to-analog conversion channels5.

Although this multiplex signal generator 1 can realize the output of multiplex signals, there are following problems:

1. Since multiple digital-to-analog conversion channels 5 are read from the waveform memory 2 through the waveform data buffer 7, multiple digital-to-analog conversion channels 5 can only output the same waveform, for example, they can only output sine waves at the same time;

2. Since the multi-channel signal generator 1 utilizes the direct digital synthesis clock source 1 to generate a frequency-variable clock signal, the hardware structure is complex and thus susceptible to interference;

3. Since the multi-channel signal generator 1 uses the direct digital synthesis clock source 1 to generate a frequency-variable clock signal, and then distributes it to multiple digital-to-analog conversion channels 5 through the clock distribution circuit 6, the multiple digital-to-analog conversion channels 5 can only Output waveforms at the same frequency.

4. Multiple digital-to-analog conversion channels 5 are not electrically isolated. When the output waveform frequency is high, interference between multiple digital-to-analog conversion channels 5 is likely to occur, resulting in output waveform distortion, and it is difficult to achieve high frequency Require.

Contents of the invention

In order to solve the problem of electrical non-isolation between multiple channels of the prior art multi-channel signal generator, the present invention provides a multiple channel signal generator with multiple channels isolated.

A multi-channel signal generator, including a control system with a clock unit, and a first channel unit and a second channel unit independent of each other, the first channel unit is connected to the control unit through a first isolation unit system, the second channel unit is connected to the control system through a second isolation unit, the first channel unit includes a first state control terminal connected to the first isolation unit, and the second channel unit It includes a second state control terminal connected to the second isolation unit, the control system includes a synchronization control terminal connected to the first isolation unit and the second isolation unit, and the first state control terminal outputs a first A state signal, after the second state control terminal outputs a second state signal, the synchronization control terminal of the control system outputs a synchronization output signal.

The multi-channel signal generator of the present invention has no electrical connection because the first channel unit and the second channel unit are independent of each other, the first channel unit is connected with the control system through the first isolation unit, and the second channel unit is connected with the control system. The systems are connected through the second isolation unit, so that the interference between the first channel unit and the second channel unit is small, and the interference between the channel unit and the control system is also small, so that the requirements for outputting high-frequency signals can be achieved. at the same time. Furthermore, due to the provision of the first state control terminal, the second state control terminal and the synchronization control terminal, a better synchronous output can still be achieved when the first channel unit and the second channel unit are electrically isolated.

Description of drawings

Fig. 1 is a schematic structural diagram of a signal generator in the prior art.

FIG. 2 is a schematic structural diagram of the direct digital synthesis clock source 1 of the prior art signal generator shown in FIG. 1 .

FIG. 3 is a schematic structural diagram of the interface control circuit 3 of the prior art signal generator shown in FIG. 1 .

FIG. 4 is a schematic structural diagram of a multi-channel signal generator 2 in a preferred embodiment of the present invention.

FIG. 5 is a flowchart of the working principle of the multi-channel signal generator 2 shown in FIG. 4 .

Detailed ways

A preferred embodiment of the multi-channel signal generator of the present invention is introduced below.

Please refer to FIG. 4 , the multi-channel signal generator 2 in a preferred embodiment of the present invention includes a control system 20 , two isolation units 271 , 272 , a first channel unit 28 and a second channel unit 29 that are independent from each other.

The control system 20 includes a control unit 21 , a waveform storage unit 22 , a temporary storage unit 23 , a display unit 24 , an input unit 25 , an interface unit 26 and a clock unit 27 . The control unit 21 is respectively connected to the waveform storage module 22, the temporary storage unit 23, the display unit 24, the input unit 25 and the interface unit 26,

The first channel unit 28 includes a waveform processing unit 281 , an external memory 282 and a digital-to-analog conversion unit 283 , and the waveform processing unit 281 is connected to the external memory 282 and the digital-to-analog conversion unit 283 respectively. The waveform processing unit 281 has an internal memory 285 , and the internal memory 285 and the external memory 282 together form a storage unit of the waveform processing unit 281 .

The second channel unit 29 includes a waveform processing unit 291 , an external memory 292 and a digital-to-analog conversion unit 293 , and the waveform processing unit 291 is connected to the external memory 22 and the digital-to-analog conversion unit 293 respectively. The waveform processing unit 291 has an internal memory 295 , and the internal memory 295 and the external memory 292 together constitute a storage unit of the waveform processing unit 291 .

The interface unit 26 is connected to the isolation unit 271, 272 respectively, the output end of the clock unit 27 is divided into two paths and connected to the two isolation units 271, 272 respectively, the isolation unit 271 is connected to the waveform processing unit 281, and the isolation unit 272 is connected to the waveform processing unit Unit 291. In this way, the signals between the control unit 21, the clock unit 27 and the first channel unit 28 need to be isolated by the isolation unit 271, and the signals between the control unit 21, the clock unit 27 and the second channel unit 29 need to pass through the isolation unit 272 isolation, and there is no electrical connection between the first channel unit 28 and the second channel unit 29, that is, there are no synchronous signal lines, clock signal lines, etc. other than isolation units connected between the first channel unit 28 and the second channel unit 29 271 and 272 directly connect the lines of the first channel unit 28 and the second channel unit 29 , thus realizing the mutual independence of the first channel unit 28 and the second channel unit 29 .

The first waveform processing unit 281 includes a first state control terminal 287 and a first synchronous receiving terminal 288 , and the first state control terminal 287 and the first synchronous receiving terminal 288 are respectively connected to the isolation unit 271 . The second waveform processing unit 291 includes a second state control terminal 297 and a second synchronous receiving terminal 298 . The second state control terminal 297 and the second synchronization receiving terminal 298 are respectively connected to the isolation unit 272 . The interface unit 26 includes a synchronous control terminal 261, a first state receiving terminal 263 and a second state receiving terminal 265, the synchronous controlling terminal 261 is divided into two paths and connected to the isolation units 271, 272 simultaneously, the first state receiving terminal 263 is connected to the isolation unit 271 for receiving the status signal output by the first status control terminal 287; the second status receiving terminal 265 is connected to the isolation unit 272 for receiving the status signal output by the second status control terminal 297. The first synchronization receiving end 288 and the second synchronization receiving end 298 are used for receiving the synchronization signal output by the synchronization control end 261 .

Among the present embodiment, control unit 21 is made of DSP, waveform storage unit 22 is made of flash memory (FLASH), temporary storage unit 23 is made of SDRAM, display unit 24 is made of liquid crystal display (LCD), and input unit 25 is made of keyboard, Interface unit 26 is made of FPGA, clock unit 27 is made of crystal oscillator, waveform processing unit 281, 291 is made of FPGA, external memory 282, 292 is made of DRAM, digital-to-analog conversion unit 283, 293 is made of DAC, and isolation unit 271, 272 is made of Magnetic coupler configuration.

The waveform storage unit 22 stores various programs run by the multiplex signal generator 2 and various waveform data, including built-in waveform data and arbitrary waveform data edited by users. The built-in waveform refers to the commonly used waveforms fixedly stored in the waveform storage unit 22 in advance, such as sinusoidal signals and the like. Arbitrary waveform refers to the waveform that the user edits or collects arbitrarily according to actual needs, such as simulating the waveform output by a sensor under a special condition. The temporary storage unit 23 serves as the operating environment of various programs run by the multiplex signal generator 2 and a temporary storage space for waveform data.

The control unit 21 is responsible for receiving and analyzing the instruction information input by the input unit 25, responsible for controlling the display unit 24 to display information such as channel output status, responsible for controlling the data reading and writing of the waveform storage unit 22 and the temporary storage unit 23, and responsible for converting the waveform data from data to The bus 269 is transferred to the first and second channel units 28 and 29 through the interface unit 26 and isolation units 271 and 272, and is responsible for configuring the parameters of the first and second channel units 28 and 29 according to the instruction information.

The interface unit 26 is used to transfer the control instruction issued by the control unit 21 and the transmitted waveform data to the selected output channel units 28 and 29, and is used to control the output of the first and second channel units 28 and 29, such as synchronous control etc.

The clock unit 27 is used to provide reference clock signals for the first and second channel units 28 and 29 . The isolation units 271, 272 are used to realize mutual independence and electrical isolation between the first and second channel units 28, 29, and are also used to connect the first and second channel units 28, 29 of the analog part with the control system of the digital part 20 to isolate.

The internal memory 285 and the external memory 282 are used to store the waveform data of the waveform that the first channel unit 28 will or is outputting. The waveform processing unit 281 is used to convert the frequency of the reference clock signal to generate the first clock signal and output it to the digital-to-analog conversion unit 283, and is also used to send the waveform data in the internal memory 285 or the external memory 282 to the digital-analog conversion unit 283 . The digital-to-analog conversion unit 283 is configured to perform digital-to-analog conversion on the received waveform data according to the first clock signal, and then output the waveform.

The internal memory 295 and the external memory 292 are used to store the waveform data of the waveform that the second channel unit 29 will or is outputting. The waveform processing unit 291 is used to convert the frequency of the reference clock signal to generate a second clock signal and output it to the digital-to-analog conversion unit 293, and is also used to send the waveform data in the internal memory 295 or the external memory 292 to the digital-analog conversion unit 293 . The digital-to-analog conversion unit 293 is configured to perform digital-to-analog conversion on the received waveform data according to the second clock signal, and then output the waveform.

The working principle of the multi-channel signal generator 2 will be described in detail below.

The multi-channel signal generator 2 includes four output modes: "single-channel independent output", "multi-channel independent output", "multi-channel frequency coupled output" and "multi-channel frequency and phase coupled output". Among them, the single-channel independent output means that a channel unit 28 or 29 outputs an arbitrary waveform at any frequency independently; the multi-channel independent output means that multiple channel units 28 and 29 independently and independently output the same or different frequencies with the same or different frequencies. Different waveforms; multi-channel frequency coupling output means that multiple channel units 28 and 29 output the same waveform at the same frequency and a certain phase difference; multi-channel frequency and phase coupling output means that multiple channel units 28 and 29 output the same waveform; The same frequency and the same phase output the same waveform, that is, the phase difference is fixed to zero. It can be seen that since "single-channel independent output" and "multi-channel independent output" do not involve the phase problem of the two channel elements 28 and 29, there is no need to synchronize the two channels. However, since both "multi-channel frequency coupling output" and "multi-channel frequency and phase coupling output" require channel units 28 and 29 to have a fixed phase difference, it is necessary to ensure that the two channels are output synchronously.

Please refer to Fig. 4 and Fig. 5 together, the multi-channel signal generator 2 comprises the following steps when working:

Step S1: The user sets the output mode, selects the channel, selects the waveform, sets the waveform parameters, etc.;

The user sets an output mode, selects a channel, selects a waveform, and sets waveform parameters through the input unit 25 . In this embodiment, setting the output mode is to select one of single-channel independent output, multi-channel independent output, multi-channel frequency coupled output, and multi-channel frequency and phase coupled output. To select a channel is to specify whether the output of the first channel unit 28 or the second channel unit 29 is to be specified when selecting a single channel independent output; in other output modes, both channel units 28 and 29 are output by default. To select a waveform is to specify the waveform to be output from the built-in waveform and the arbitrary waveform edited by the user. Setting waveform parameters is to set specific parameters such as the frequency and amplitude of the output waveform.

Step S2: Determine whether it is coupling output? If yes, execute step S3, otherwise execute step S13;

Steps S3-S7 are steps for controlling the output synchronization of the first channel unit 28 and the second channel unit 29. Therefore, the control unit 21 first judges whether it is a coupling output, and if it is a single-channel independent output or a multi-channel independent output, then no It is necessary to carry out synchronous control on the first channel unit 28 and the second channel unit 29, then perform step S13 to output; if it is a multi-channel frequency coupling output or a multi-channel frequency and phase coupling output, it is necessary to control the first channel unit 28 and the second channel unit When the two-channel unit 29 performs synchronous control, step S3 is executed.

Step S3: prepare for each selected channel;

The control unit 21 reads the waveform data corresponding to the waveform selected by the user from the waveform storage unit 22, caches it in the temporary storage unit 23, and sends it to the selected channel unit in the first channel unit 28 and the second channel unit 29 . That is to say, if in step S1, what the user selects is single-channel independent output, so only need to send the waveform data to the selected channel unit among the first channel unit 28 and the second channel unit 29; if the user If multi-channel independent output is selected, then the waveform data needs to be sent to the first channel unit 28 and the second channel unit 29 . And, if the wave form that first channel unit 28 and second channel unit 29 will output is identical, then the waveform data sent to first channel unit 28 and second channel unit 29 is identical; If first channel unit 28 and second channel unit If the waveforms to be output by 29 are different, the waveform data sent to the first channel unit 28 and the second channel unit 29 are different.

In this embodiment, the length of the waveform data stored in the waveform storage unit 22 is several fixed values: namely 16K, 32K, 64K... or 64M data points, where 1K=1024, 1M=1024K. Since the external memory 282, 292 has a larger capacity but a slower access speed, while the internal memory 285, 295 has a smaller capacity but a faster access speed, so in this embodiment, a predetermined length of 16K is set, which is greater than the predetermined length of 16K The waveform data of 16K data points is stored in the external memory 282, 292, and the waveform data of 16K data points equal to the predetermined length is stored in the internal memory 285, 295.

In this embodiment, the external memories 282 and 292 are composed of DRAMs, and the DRAMs need to perform operations such as refreshing when reading, so the reading speed may be inconsistent. Therefore, in order to obtain a better output effect, if the length of the waveform data to be output is greater than 16k, it is not only stored in the external memory 282, 292, but the waveform processing unit 281, 291 also buffers the first output part of the waveform data into the internal memory 285,295. In this way, when outputting waveforms, the waveform processing units 281, 291 can directly read from the internal memories 285, 295, and at the same time continuously supplement buffered waveform data from the external memories 282, 292 to the internal memories 285, 295. Since the data is directly read from the internal memory 285, 295, it can be guaranteed that the two channels read the waveform data at the same speed.

In addition, in step S3 , the control unit 21 also configures waveform parameters such as frequency and amplitude of the channel unit selected from the first channel unit 28 and the second channel unit 29 .

Step S4: notify the interface unit after each channel is ready;

Because the external memories 282 and 292 need to perform operations such as refreshing when reading, resulting in inconsistent reading speeds, the preparation time of the first channel unit 28 and the second channel unit 29 may be different. Therefore, when the first channel unit 28 is ready, the first state control terminal 287 of the waveform processing unit 281 will send a first state signal to the interface unit 26 to indicate that the preparation is completed, and the first state receiving end of the interface unit 26 263 will receive the first status signal. After the second channel unit 29 is ready, the second state control terminal 297 of the waveform processing unit 282 will send a second state signal to the interface unit 26 to indicate that the preparation is completed, and the second state receiving end 265 of the interface unit 26 will Accept the second status signal. The term "ready" means that the first channel unit 28 or the second channel unit 29 is ready to output the waveform, that is, the waveform data has been loaded into the internal memory 285, 295, and the waveform parameters have been configured. In this embodiment, the first state signal and the second state signal are high level, the first state control terminal 287 is low level during the non-first state signal period, and the second state control terminal 297 is low level during the non-first state signal period. The two-state signal period is low level.

Step S5: the interface unit judges whether all preparations are completed;

The interface unit 26 judges whether the first state receiving end 263 and the second state receiving end 265 have received the first state signal and the second state signal, if yes, execute step S6; if not, return to step S4.

Step S6: the interface unit simultaneously sends a waveform output command to all selected channels;

The synchronous control terminal 261 of the interface unit 26 outputs a synchronous output signal, and the synchronous output signal is divided into the same two paths, one path is sent to the first waveform processing unit 281 through the isolation unit 271, and the other path is sent to the second waveform processing unit 281 through the isolation unit 272. processing unit 291 . The first synchronous receiving end 288 of the first waveform processing unit 281 and the second synchronous receiving end 298 of the second waveform processing unit 291 simultaneously receive the synchronous output signal, and simultaneously start to read data from the internal memory 285, 295 and send it to the digital-analog The conversion units 283 and 293 perform digital-to-analog conversion to ensure the synchronous output of the output waveforms of the first channel unit 28 and the second channel unit 29 , that is, coupled output. In this embodiment, the synchronous output signal is at high level, and the synchronous control terminal 261 is at low level during the non-synchronous output signal period.

Step S7: The selected channels output waveforms according to their respective waveform parameters.

The waveform processing unit 281 converts the frequency of the reference clock signal provided by the clock unit 27 to generate a first clock signal, and outputs the first clock signal to the digital-to-analog conversion unit 283 . At the same time, the waveform processing unit 281 also sends the waveform data in the internal memory 285 to the digital-to-analog conversion unit 283 according to the first clock signal. The digital-to-analog conversion unit 283 performs digital-to-analog conversion on the received waveform data according to the first clock signal, and then outputs the waveform.

The waveform processing unit 282 converts the frequency of the reference clock signal provided by the clock unit 27 to generate a second clock signal, and outputs the first clock signal to the digital-to-analog conversion unit 283 . At the same time, the waveform processing unit 281 also sends the waveform data in the internal memory 285 to the digital-to-analog conversion unit 283 according to the first clock signal. The digital-to-analog conversion unit 283 performs digital-to-analog conversion on the received waveform data according to the first clock signal, and then outputs the waveform.

Step S13: each selected channel is prepared, and the prepared channel immediately outputs the waveform;

As mentioned in detail above, this is the case of single-channel independent output or multi-channel independent output, so synchronization is not required. Each selected channel is prepared according to the method of step 4, and the prepared channel can immediately output the waveform according to the method of step S7.

As another embodiment, the first state signal and the second state signal are at low level, the first state control terminal 287 is at high level during the non-first state signal period, and the second state control terminal 297 is at non-first state signal period. The two-state signal period is high level.

As another embodiment, the synchronous output signal is at low level, and the synchronous control terminal 261 is at high level during the non-synchronous output signal period.

As another embodiment, the first state signal, the second state signal, and the synchronous output signal may also be pulse signals, pulse width signals, write memory flag bit signals, and the like.

As another embodiment, the control unit 21 may also be a microprocessor such as a single-chip microcomputer, MCU, ARM, or CPU. The waveform storage unit 22 can also be a non-volatile memory such as EEPROM. The temporary storage unit 23 may also be a DRAM or the like. The display unit 24 may also be a plasma display, an LED display, an electrowetting display (EWD), and the like. The input unit 25 may also be a touch screen, a remote controller, a mouse, or a communication interface for remote control. The interface unit 26 can also be realized by programmable logic devices such as CPLD. The waveform processing units 281 and 291 can also be realized by programmable logic devices such as CPLD. The external memory 282, 292 can also be SRAM. The isolation units 271 and 272 may also be isolation devices such as optocouplers, flip-flops, and logic gates.

As another embodiment, the number of channels of the multi-channel signal generator 2 is not limited to two, and may be more than two channels. For example, the multi-channel signal generator 2 may have 4 channels, and at this time, it is only necessary to make the multi-channel signal generator 2 include four channel units.

The first channel unit 28 and the second channel unit 29 of the multi-channel signal generator 2 of the present invention are independent of each other without electrical connection, the first channel unit 28 is connected with the control system 20 by an isolation unit 271, and the second channel The isolation unit 272 is connected between the unit 29 and the control system 20, so that the interference between the first channel unit 28 and the second channel unit 29 is small, and the interference between the channel units 28, 29 and the control system 20 is also small, In turn, the requirement of outputting high-frequency signals can be achieved. And because the first state control terminal 287, the second state control terminal 297 and the synchronization control terminal 261 are provided, a better synchronous output can still be achieved when the first channel unit 28 and the second channel unit 29 are electrically isolated .

In addition, the first channel unit 28 of the multi-channel signal generator 2 of the present invention has a waveform processing unit 281 and a storage unit connected thereto, and the second channel unit 29 has a waveform processing unit 291 and a storage unit connected thereto, each The channel can store the waveform data corresponding to the waveform to be output in the storage unit, and then the waveform processing unit 281, 291 controls the readout of the waveform data for digital-to-analog conversion, so the same or different waveforms can be output on multiple channels. The waveform processing units 281 and 291 convert the frequency of the reference clock provided by the clock unit 27 to obtain the clock signal of the frequency required by each channel, so it is convenient for multiple channels to output waveforms at the same or different frequencies, and at the same time save Go to the use of direct digital synthesis clock sources.

Claims (10)

1. A multi-channel signal generator, comprising: a control system with a clock unit, and a first channel unit and a second channel unit independent of each other, It is characterized by: said first channel unit is connected to said control system via a first isolation unit, said second channel unit is connected to said control system via a second isolation unit, The first channel unit includes a first state control terminal connected to the first isolation unit, The second channel unit includes a second state control terminal connected to the second isolation unit, The control system includes a synchronous control terminal connected to the first isolation unit and the second isolation unit, After the first state control terminal outputs a first state signal and the second state control terminal outputs a second state signal, the synchronization control terminal of the control system outputs a synchronization output signal, The first channel unit and the second channel unit output waveform signals synchronously according to the synchronous output signal. 2. The multi-channel signal generator according to claim 1, characterized in that: the first channel unit outputs the first state signal after it is ready for output, and the second channel unit is ready for output Then output the second state signal. 3. The multi-channel signal generator according to claim 1, characterized in that: the first state signal and the second state signal are high level or low level, and the control signal is high level or low level flat. 4. The multi-channel signal generator according to claim 1, characterized in that: the control system comprises a control unit, a waveform storage unit connected with the control unit, a clock unit and a Unit, the interface unit connected with the clock unit, the synchronization control terminal is located in the interface unit, the first channel unit includes a first waveform processing unit, a first digital-analog unit connected to the first waveform processing unit A conversion unit and a first storage unit connected to the first waveform processing unit, the second channel unit includes a second waveform processing unit, a second digital-to-analog conversion unit connected to the second waveform processing unit and a second storage unit connected to the second waveform processing unit, the first state control terminal is located in the first waveform processing unit, and the second state control terminal is located in the second waveform processing unit. 5. The multi-channel signal generator according to claim 4, wherein the waveform storage unit is used to store waveform data corresponding to various waveforms, and the first storage unit is used to store a first waveform data , the second storage unit is used to store a second waveform data, the first waveform data and the second waveform data come from the waveform storage unit, and the first waveform processing unit and the second waveform processing unit receive synchronization After the signal is output, the first waveform processing unit outputs the first waveform data while the second waveform processing unit outputs the second waveform data. 6. The multi-channel signal generator according to claim 5, characterized in that: the clock unit generates a reference clock signal, and the first waveform processing unit obtains the first clock signal according to the frequency conversion of the reference clock signal, so The second waveform processing unit converts the frequency of the reference clock signal to obtain a second clock signal, and the first waveform processing device outputs the first clock signal and the first waveform data to the first digital-to-analog conversion unit, The second waveform processing device outputs the second clock signal and the second waveform data to the second digital-to-analog conversion unit, and the first digital-to-analog conversion unit is used to convert the The first waveform data is converted into a first waveform signal, and the second digital-to-analog conversion unit is configured to convert the second waveform data into a second waveform signal according to the second clock signal. 7. The multiplex signal generator according to claim 6, characterized in that: said first storage unit comprises a first internal memory and a first external memory, said second storage unit comprises a first internal memory and a second external memory, if the first waveform data is greater than a predetermined length, then stored in the first external memory, if the first waveform data is less than the predetermined length, then stored in the first internal memory, If the second waveform data is larger than the predetermined length, it is stored in the second external memory, and if the second waveform data is smaller than the predetermined length, it is stored in the second internal memory. 8. The multi-channel signal generator according to claim 7, characterized in that: if the first waveform data is greater than a predetermined length, the first waveform processing unit will also store the first waveform data in the first external memory A part of the waveform data is loaded into the first internal memory; and the second waveform processing unit also loads a part of the second waveform data in the second external memory into the second internal memory. 9. The multi-channel signal generator according to claim 4, characterized in that: the first waveform processing unit and the second waveform processing unit are one of FPGA and CPLD programmable logic device. 10. The multi-channel signal generator according to claim 1, wherein the first isolation unit and the second isolation unit comprise magnetic couplers.