CN102117877B - Semiconductor chip assembly - Google Patents

Abstract

A semiconductor chip assembly at least comprises a semiconductor component, a heat sink, a substrate and an adhesive layer. Wherein the semiconductor element is electrically connected to the substrate and thermally connected to the heat sink; the heat dissipation seat at least comprises a convex column and a base, wherein the convex column extends upwards to pass through an opening of the adhesion layer and enter a through hole of the substrate, and the base extends laterally and supports the substrate; the adhesive layer extends between the convex column and the substrate and between the base and the substrate; and the substrate comprises a first and a second conductive layer and a dielectric layer therebetween. Thus, the assembly can provide a vertical signal route between a pad on the first conductive layer and a terminal under the adhesion layer.

Description

Semiconductor Chipset

technical field

The invention relates to a semiconductor chip assembly body, especially a semiconductor chip assembly body which is suitable for high-power semiconductor components, especially a semiconductor chip assembly body composed of a semiconductor component, a substrate, an adhesive layer and a heat sink.

Background technique

Semiconductor components such as packaged and unpackaged semiconductor chips can provide high voltage, high frequency and high performance applications; these applications perform specific functions, so the power consumption required is very high, but the higher the power, the semiconductor components It generates more heat. In addition, after the packaging density is increased and the size is reduced, the surface area available for heat dissipation is also reduced, resulting in increased heat generation.

Semiconductor components are prone to problems such as performance degradation and shortened service life under high temperature operation, and may even fail immediately. High heat not only affects chip performance, but may also cause thermal stress on the chip and its surrounding components due to thermal expansion mismatch. Therefore, it is necessary to quickly and effectively dissipate heat from the chip to ensure its operating efficiency and reliability. A high thermal conductivity path typically conducts and dissipates thermal energy to an area with a larger surface area than the chip or die pad on which the chip resides.

Light emitting diode (Light Emitting Diode, LED) has recently become a substitute light source for incandescent light source, fluorescent light source and halogen light source. LEDs can provide long-time lighting with high energy efficiency and low cost for applications such as medical, military, signboard, signal, aviation, marine, vehicle, portable equipment, commercial and residential lighting. For example, LEDs can provide light sources for equipment such as lamps, flashlights, headlights, searchlights, traffic lights and displays.

The high-power chips in LEDs generate a lot of heat while providing high light output. However, under high-temperature operation, LEDs suffer from problems such as color shift, reduced brightness, shortened lifespan, and immediate failure. In addition, LEDs have limitations in terms of heat dissipation, which in turn affects their light output and reliability. Therefore, LEDs particularly highlight the market's demand for high-power chips with good heat dissipation.

The LED package usually includes an LED chip, a base, an electrical contact and a thermal contact. Wherein the base is thermally connected to the LED chip and used to support the LED chip; the electrical contact is electrically connected to the anode and cathode of the LED chip; and the thermal contact is thermally connected to the LED chip through the base, below The carrier can sufficiently dissipate heat to prevent the LED chip from overheating.

The industry is actively investing in the research and development of high-power chip packages and thermal pads with various design and manufacturing technologies in order to meet performance requirements in this extremely cost-competitive environment.

The plastic ball grid array (Plastic Ball Grid Array, PBGA) package is to wrap a chip and a laminated substrate in a plastic case, and then stick it on a printed circuit board (PCB) with solder balls. The laminate substrate includes a dielectric layer usually made of glass fiber, and the heat generated by the chip can be transmitted to the solder balls through the plastic and dielectric layer, and then to the printed circuit board. However, due to the low thermal conductivity of the plastic and dielectric layers, PBGAs do not dissipate heat well.

The Quad Flat No-lead (QFN) package is to place the chip on a copper die seat soldered to the printed circuit board. The heat energy generated by the chip can be transferred to the printed circuit board through the die pad. However, due to the limited routing capability of its lead frame interposer, the QFN package is not suitable for high input/output (I/O) chips or passive components.

Thermal pads provide electrical routing, thermal management, and mechanical support for semiconductor components. A thermal pad usually consists of a substrate for signal routing, a heat sink or heat sink for heat removal, a solder pad for power connection to semiconductor components, and a terminal for power connection to the next layer of assembly . Wherein the substrate can be a laminated structure with a single-layer or multi-layer routing circuit system and one or more dielectric layers; the heat sink can be a metal base, a metal block or a buried metal layer.

The thermally conductive plate joins the next layer of assembly. For example, the next layer of assembly can be a lamp holder with a printed circuit board and a heat dissipation device. In this example, an LED package is mounted on a heat conducting plate, the heat conducting plate is mounted on a heat sink, and the heat conducting plate/heat sink sub-assembly and the printed circuit board are mounted in the lamp holder. Wherein, the heat conducting plate is electrically connected to the printed circuit board via wires. In this way, the substrate can guide electrical signals from the printed circuit board to the LED packaging body, and the heat dissipation base dissipates and transmits the heat energy of the LED packaging body to the heat dissipation device. Therefore, the heat conducting plate can provide an important heat path for the LED chip.

U.S. Patent No. 6,507,102 to Juskey et al. discloses an assembly in which a composite substrate composed of fiberglass and cured thermosetting resin includes a central opening and has a heat slug similar to the central opening in a square or rectangular shape Adhering to the sidewall of the central opening and thus combining with the substrate, and respectively adhering upper and lower conductive layers on the top and bottom of the substrate, and electrically connecting each other through the electroplating via holes penetrating the substrate. Moreover, another chip is arranged on the heat dissipation block and bonded to the upper conductive layer by wire bonding, and an encapsulation material is molded on the chip, and the lower conductive layer is provided with solder balls.

When the aforementioned patent was manufactured, the substrate was originally a B-stage resin film placed on the lower conductive layer. The radiating block is inserted into the central opening, thus located on the lower conductive layer and separated from the substrate by a gap, and the upper conductive layer is arranged on the substrate. After the upper and lower conductive layers are heated and pressed together, the resin melts and flows into the aforementioned gap to solidify, and the upper and lower conductive layers form a pattern, thereby forming circuit wiring on the substrate and exposing resin overflow on the heat sink. Then remove the resin overflow, so that the heat dissipation block is exposed, and finally place the chip on the heat dissipation block for wire bonding and packaging.

Therefore, the heat energy generated by the chip can be transferred to the printed circuit board through the heat dissipation block. However, manually placing the cooling slug in the central opening is labor-intensive and expensive when mass-produced. Furthermore, due to the small lateral installation tolerance, it is not easy for the heat sink to be accurately positioned in the central opening, resulting in gaps and uneven bonding between the substrate and the heat sink. As a result, the substrate is only partially adhered to the heat slug, which cannot obtain enough supporting force from the heat slug, and is easy to delaminate. In addition, the chemical etchant used to remove part of the conductive layer to reveal the resin flash will also remove part of the heat sink that is not covered by the resin flash, resulting in uneven heat sink and difficult bonding, which will eventually lead to a low pass rate of the assembly. Reliable Insufficient degree and high cost and other shortcomings.

US Patent No. 6,528,882 to Ding et al. discloses a high heat dissipation ball grid array package, the substrate of which includes a metal core layer, and the chip is placed on the die pad area on the top surface of the metal core layer. Wherein, an insulating layer is formed on the bottom surface of the metal core layer, and a blind hole penetrates the insulating layer and leads directly to the metal core layer, and the hole is filled with heat dissipation tin balls, and on the substrate, there is also a heat dissipation tin ball. The ball corresponds to the solder ball. In this way, the heat energy generated by the chip can flow to the heat dissipation solder ball through the metal core layer, and then flow to the printed circuit board; however, the insulating layer interposed between the metal core layer and the printed circuit board flows convectively to the printed circuit board heat flow is restricted.

U.S. Patent No. 6,670,219 to Lee et al. teaches a Cavity Down Ball Grid Array (CDBGA) package in which a ground plate with a central opening is placed on a heat sink to form a heat sink substrate, and install a chip in a groove formed by the central opening of the ground plate on the heat sink, and set a substrate with a central opening on the ground plate through an adhesive layer with a central opening, and Solder balls are arranged on the substrate. However, since the solder balls are located on the substrate, the heat sink cannot contact the printed circuit board, so the heat dissipation effect of the heat sink is limited to heat convection rather than heat conduction, thus greatly limiting its heat dissipation effect.

US Patent No. 7,038,311 to Woodall et al. provides a high heat dissipation BGA package with an inverted T-shaped heat sink comprising a post and a wide base. A substrate with a window-shaped opening is placed on the wide base, and an adhesive layer adheres the post and the wide base to the substrate; a chip is placed on the post and bonded to the substrate by wire bonding, and a chip is placed on the post and bonded to the substrate. Packaging material is molded on the chip, and solder balls are arranged on the substrate. Wherein, the column portion extends through the window opening, and supports the substrate by the wide base, and the solder ball is located between the wide base and the periphery of the substrate. In this way, the heat energy generated by the above-mentioned chip can be transferred to the wide base through the column, and then to the printed circuit board; The position between the central window and the innermost solder ball protrudes below the substrate. As a result, the substrate is unbalanced during the manufacturing process, and is easy to shake and bend, which makes it very difficult to mount the chip, wire bond and mold the packaging material. In addition, the wide base may bend due to the molding of the packaging material, and once the solder balls collapse, it may prevent the package from being soldered to the next layer of assembly. Therefore, the yield of the package is low, the reliability is insufficient and the cost is too high.

U.S. Patent Application Publication No. 2007/0267642 to Erchak et al. proposes a light-emitting device assembly, wherein an inverted T-shaped base includes a substrate, a protrusion, and an insulating layer with a through hole. There are electrical contacts on the layer. A package body with a through hole and a transparent upper cover is disposed on the electrical contact; an LED chip is disposed on the protruding portion and connected to the substrate by wire bonding, and the protruding portion is adjacent to the substrate and extends through the insulating layer and the substrate. The through hole on the package enters into the package. Moreover, the insulating layer is arranged on the substrate, and the insulating layer is provided with electrical contacts, and the package is arranged on the electrical contacts and keeps a distance from the insulating layer. Thereby, the heat energy generated by the chip can be transferred to the substrate through the protruding part, and then reach a heat sink; however, the electrical contacts are not easy to be arranged on the insulating layer, and it is difficult to electrically connect with the next layer assembly, and Multi-tier routing cannot be provided.

Existing packages and thermal pads have significant disadvantages. For example, electrical insulating materials with low thermal conductivity, such as epoxy resins, limit heat dissipation; however, electrical insulating materials with higher thermal conductivity, such as epoxy resins filled with ceramic or silicon carbide, have low adhesion and Due to the high cost of mass production, the electrical insulating material may be delaminated due to heat during the manufacturing process or at the early stage of operation. If the substrate is a single-layer circuit system, the routing capability is limited, but if the substrate is a multi-layer circuit system, the over-thick dielectric layer will reduce the heat dissipation effect. In addition, the previous technology still has problems such as insufficient performance of the heat sink, too large volume, or difficult thermal connection to the next layer of assembly, and the manufacturing process of the previous technology is not suitable for low-cost batch operation.

In view of the various development situations and related limitations of the existing high-power semiconductor component packages and heat conduction plates, the general existing ones cannot meet the requirements of the industry for users in actual use. A cost-effective, reliable, suitable For mass production, multi-function, flexible adjustment of signal routing and semiconductor chip assembly with excellent heat dissipation.

Contents of the invention

The main purpose of the present invention is to overcome the above-mentioned problems encountered in the prior art and provide a semiconductor chip assembly which is cost-effective, reliable in performance, suitable for mass production, multi-functional, can flexibly adjust signal routing, and has excellent heat dissipation.

In order to achieve the above purpose, the first technical solution adopted by the present invention is: a semiconductor chip assembly for providing vertical signal routing, which includes:

An adhesive layer has at least one opening;

A heat sink, comprising at least a boss and a base, wherein the boss adjoins the base and extends above the base along an upward direction, and the base extends along a downward direction opposite to the upward direction under the stud and extending laterally from the stud in a side direction perpendicular to the upward and downward directions;

A substrate, disposed on the adhesive layer and extending above the base, at least includes a pad, a routing line, a first conductive hole and a dielectric layer, wherein the pad extends above the dielectric layer , the routing line extends below the dielectric layer and is buried in the adhesive layer, and the first conductive hole extends through the dielectric layer to the routing line, and a via hole extends through the substrate;

a second conductive hole extending through the adhesive layer to the routing line;

a terminal extending below the adhesive layer;

A semiconductor component, located above and overlapping the protrusion, or located below and overlapped by the protrusion, the semiconductor component is electrically connected to the pad and the terminal, and thermally connected to the protrusion with the base; and

The protrusion extends through the opening and enters the through hole to reach above the dielectric layer, the base extends below the adhesive layer and the substrate, and is formed by the first conductive hole, the routing line and the second conductive hole forming a conductive path between the pad and the terminal, wherein the adhesive layer is disposed on the base, and extends above the base into the through hole into a gap between the bump and the substrate, The gap extends across the dielectric layer, and is between the protrusion and the dielectric layer, and between the base and the substrate.

The semiconductor component is a semiconductor chip, which extends over the stud, overlaps the stud, and is electrically connected to the pad, thereby electrically connected to the terminal, and the semiconductor chip is thermally connected to the stud, Thereby thermally bonded to the base.

The semiconductor component is a semiconductor chip, which is arranged on the heat sink by a solid crystal material, electrically connected to the welding pad through a bonding wire, and thermally connected to the protrusion through the solid crystal material.

The adhesive layer contacts the stud and the dielectric layer in the gap, and contacts the base, the dielectric layer, the routing line, the second conductive hole and the terminal outside the gap.

The adhesive layer covers and surrounds the protrusion in the side direction.

The adhesive layer fills up the gap.

The adhesive layer fills up a space between the base and the substrate.

The adhesive layer overlaps the terminal.

The adhesive layer extends to the peripheral edge of the assembly.

The post is integrally formed with the base.

The protrusion and the adhesive layer are on the same plane above the dielectric layer.

The protrusion is in the shape of a flat top cone, and its diameter decreases upwards from the base to the flat top of the protrusion.

The base and the terminal are on the same plane below the adhesive layer.

The base covers the post from below, supports the substrate, and keeps a distance from the peripheral edge of the assembly.

The base plate is kept at a distance from the boss and the base.

The substrate is a laminated structure.

The heat sink at least includes a cover, which is located above a top of the boss, adjoins to the top of the boss and covers from above, and extends laterally from the top of the boss along the side direction.

The cover body is rectangular or square, and the top of the protrusion is round.

The heat sink at least includes a cover body, and the cover body and the welding pad are on the same plane above the dielectric layer.

The heat sink is made of copper.

To achieve the above purpose, the second technical solution adopted by the present invention is: a semiconductor chip assembly for providing vertical signal routing, which includes:

An adhesive layer has at least one opening;

A heat dissipation seat at least includes a boss, a base and a cover, wherein the boss is adjacent to the base and integrally formed with the base, and the boss extends above the base along an upward direction, and The base is thermally connected to the cover, the base extends below the post along a downward direction opposite to the upward direction, and extends from the post along a side direction perpendicular to the upward and downward directions. Extending laterally, the cover is located above a top of the boss, adjoins to the top of the boss and covers from above, and extends laterally from the top of the boss along the side direction;

A substrate, disposed on the adhesive layer and extending above the base, at least includes a first and a second conductive layer, a first conductive hole and a dielectric layer, wherein the first conductive layer contacts the dielectric layer layer and extends above the dielectric layer, the second conductive layer contacts the dielectric layer and extends below the dielectric layer and is embedded in the adhesive layer, and has a solder pad included in the first conductive layer a selected portion of the second conductive layer, the pad contacts the dielectric layer and extends over the dielectric layer, and has a routing line included in a selected portion of the second conductive layer, the routing line contacting the dielectric layer and extending over the dielectric layer Below the dielectric layer, the first conductive hole contacts and extends through the dielectric layer between the first conductive layer and the routing line, and a through hole extends through the substrate;

a second conductive hole, contacting and extending through the adhesive layer to the routing line;

a terminal contacting and extending under the adhesive layer;

A semiconductor chip is disposed on the cover, overlaps the stud, and is electrically connected to the pad, thereby electrically connected to the terminal, and the semiconductor chip is thermally connected to the cover, thereby thermally connected to the base; and

The protrusion extends through the opening and enters the through hole to reach above the dielectric layer, and the base extends below the semiconductor chip, the adhesive layer and the substrate along the downward direction, and covers the semiconductor chip and the substrate from below. The boss supports the substrate, the first conductive hole, the routing line and the second conductive hole form a conductive path between the pad and the terminal, wherein the adhesive layer is arranged on the base, and Extending above the base into the through hole is a gap between the boss and the substrate, extending across the dielectric layer in the gap, and interposed between the boss and the dielectric layer in the gap Between the base and the base plate outside the gap, the adhesive layer covers and surrounds the protrusion along the side direction, and extends to the peripheral edge of the assembly.

The semiconductor chip is arranged on the cover with a crystal-bonding material, electrically connected to the welding pad through a bonding wire, and thermally connected to the cover through the crystal-bonding material.

The substrate is kept at a distance from the boss and the base, the gap and a space between the base and the substrate are filled by the adhesive layer, and the adhesive layer is limited to a space between the heat sink and the substrate. inside the space.

The top of the protruding column is circular, and the cover on it is rectangular or square. The protruding column is in the shape of a flat-topped cone, and its diameter decreases upward from the base to the cover.

The protrusion, the adhesive layer, the cover and the welding pad are all on the same plane above the dielectric layer, and the base and the terminal are on the same plane below the adhesive layer, and the material of the heat sink is copper.

The present invention also provides a method for manufacturing a semiconductor chip assembly, which includes: providing a protrusion and a base; setting an adhesive layer on the base, and inserting the protrusion into an opening of the adhesive layer; setting a substrate on the adhesive layer, and inserting the boss into a through hole of the substrate, thereby forming a gap between the boss and the substrate in the through hole; making the adhesive layer flow upward into the gap; curing the adhesive layer; disposing a semiconductor component on a heat sink, wherein the heat sink includes at least the boss and the base; electrically connecting the semiconductor component to the substrate and a terminal located under the adhesive layer; and thermally connecting The semiconductor component is connected to the heat sink. The above-mentioned substrate at least includes a first and a second conductive layer and a dielectric layer located therebetween, so that the assembly can provide vertical signal routing.

The present invention also provides another method for manufacturing a semiconductor chip assembly, comprising the following steps:

(A1) Provide a boss, a base, an adhesive layer and a substrate, wherein the substrate at least includes a first conductive layer, a second conductive layer and a dielectric layer therebetween; the boss is adjacent to the base a seat extending above the base along an upward direction, extending through an opening of the adhesive layer, and extending into a through hole of the substrate; the base extends over the boss along a downward direction opposite to the upward direction below, and extend laterally from the post along a side direction perpendicular to the upward and downward directions; the adhesive layer is disposed on the base, extends above the base, and is located between the base and the substrate between, and uncured; the substrate is disposed on the adhesive layer, extending above the adhesive layer, wherein the first conductive layer extends above the dielectric layer, and the dielectric layer extends above the second conductive layer ; and a notch located in the through hole and between the boss and the substrate;

(B1) making the adhesive layer flow upward into the gap;

(C1) curing the adhesive layer;

(D1) disposing a semiconductor component on a heat sink including at least the protrusion and the base, wherein the semiconductor component is overlapped by the protrusion if not overlapping the protrusion. The assembly at least includes a pad, a terminal, a routing line and first and second conductive holes, wherein the pad includes a selected portion of the first conductive layer; the routing line includes a portion of the second conductive layer a selected portion; the first conductive hole contacts and extends through the dielectric layer between the first conductive layer and the routing line; the second conductive hole contacts and extends through the adhesive layer to the routing line; and the terminal contacts and extends below the adhesive layer;

(E1) electrically connecting the semiconductor component to one of the bonding pad and the terminal, thereby electrically connecting the semiconductor component to the other of the bonding pad and the terminal, one of which is located between the bonding pad and the terminal The conductive path between includes the first conductive hole, the routing line and the second conductive hole; and

(F1) Thermally bonding the semiconductor component to one of the stud and the base, thereby thermally coupling the semiconductor component to the other of the stud and the base.

The present invention also provides a third method for manufacturing a semiconductor chip assembly, comprising the following steps:

(A2) A post and a base are provided, wherein the post is adjacent to and integrally formed on the base, and extends above the base in an upward direction, and the base extends in a direction opposite to the upward direction. a downward direction extending below the boss and extending laterally from the boss in a side direction perpendicular to the upward and downward directions;

(B2) providing an adhesive layer, which includes an opening extending through the adhesive layer;

(C2) A substrate is provided, wherein the substrate includes at least a first and a second conductive layer and a dielectric layer therebetween, and includes a routing line included in a selected portion of the second conductive layer, and a through a hole extending through the substrate;

(D2) disposing the adhesive layer on the base, including inserting the boss into the opening, wherein the adhesive layer extends above the base, and the boss extends through the opening;

(E2) disposing the substrate on the adhesive layer, including inserting the boss into the through hole, wherein the substrate extends above the adhesive layer, and a first conductive layer in the substrate extends above the dielectric layer, The dielectric layer extends above the second conductive layer in the substrate, and the stud extends through the opening and enters the through hole, the adhesive layer is between the base and the substrate and is uncured, and has a gap located in the through hole and between the boss and the substrate;

(F2) heating and melting the adhesive layer;

(G2) abutting the base and the substrate against each other, whereby the boss moves upward in the through hole, and exerts pressure on the melted adhesive layer between the base and the substrate, and the pressure forces the melted adhesive layer flows upward into the notch, and the stud and the fused adhesive layer extend above the dielectric layer;

(H2) heating and solidifying the melted adhesive layer, thereby mechanically adhering the post and the base to the substrate;

(12) providing a first conductive hole, which extends from the first conductive layer through the dielectric layer to the routing line;

(J2) providing a second conductive hole extending through the adhesive layer to the routing line;

(K2) providing a pad extending over the dielectric layer, and removing selected portions of the first conductive layer;

(L2) providing a terminal extending below the adhesive layer and removing selected portions of the base;

(M2) providing a cover on the stud, the cover being located above a top of the stud, adjoining and covering the top of the stud from above, and extending laterally from the top of the stud in the side direction out;

(N2) disposing a semiconductor chip on the cover, wherein a heat sink includes at least the protrusion, the base and the cover, and the semiconductor chip overlaps the protrusion;

(O2) electrically connecting the semiconductor chip to the bonding pad, thereby electrically connecting the semiconductor chip to the terminal, wherein a conductive path between the bonding pad and the terminal sequentially includes the first conductive hole, the routing wire and the second via; and

(P2) Thermally bonding the semiconductor chip to the cover, thereby thermally bonding the semiconductor chip to the base.

The above-mentioned step (A2) of providing the protrusion and the base may include: providing a metal plate; forming a patterned etching resistance layer on the metal plate, which selectively exposes the metal plate; etching the metal plate so that forming a pattern defined by the patterned etch stop layer, thereby forming a groove in the metal plate, which extends into but not through the metal plate; and then removing the patterned etch stop layer, wherein the protrusion is An unetched portion of the metal plate protrudes above the base and is surrounded laterally by the groove, the base is also an unetched portion of the metal plate and is located between the boss and the groove below.

The above step (B2) providing the adhesive layer may include: providing a film of uncured epoxy resin, and step (G2) making the adhesive layer flow may include: melting the uncured epoxy resin; and pressing the base and The uncured epoxy resin between the substrates, and the step (H2) heating and curing the melted adhesive layer may include: curing the melted uncured epoxy resin.

The step (C2) of providing the substrate may include: providing the routing line, this step includes removing a selected portion of the second conductive layer; and then forming the through hole.

The step (K2) of providing the pad may include: grinding the bump, the adhesive layer, and the first conductive layer, so that the bump, the adhesive layer, and the first conductive layer are on an upper side facing the upward direction The surfaces are laterally flush with each other; then selected portions of the first conductive layer are removed. Wherein, the grinding may include grinding the adhesive layer without grinding the post, and then grinding the post, the adhesive layer and the first conductive layer.

The above step (K2) of providing the bonding pad may also include removing selected portions of the first conductive layer. Step (L2) of providing the terminal may comprise removing selected portions of the base. Step (I2) providing the first conductive hole may include: forming a first hole extending through the first conductive layer and the dielectric layer to the routing line; and then in the first hole and the first conductive layer Conductive metal is deposited in-line with the routing to form a third conductive layer. Step (J2) providing the second conductive hole may include: forming a second hole extending through the base and the adhesive layer to the routing line; and then depositing in-line in the second hole and the base and the routing line conductive metal to form a fourth conductive layer.

The above steps (K2, L2, I2 and J2) to provide the pad, the terminal and the first and second conductive holes may also include: forming the above-mentioned holes; depositing conductive metal in the holes to form the third and second conductive holes. Four conductive layers; then removing selected portions of the first and third conductive layers using a first patterned etch stop layer defining the pad, and removing selected portions of the first and third conductive layers using a second patterned etch stop layer defining the terminal The fourth conductive layer and selected portions of the base.

The above-mentioned step (I2) of providing the first conductive hole may include: depositing conductive metal in the first hole and on the protrusion, the first conductive layer, the adhesive layer and the routing line to form a third conductive layer. The step (J2) of providing the second conductive hole may include: depositing conductive metal in the second hole and on the base, the adhesive layer and the routing line to form a fourth conductive layer. Step (K2) of providing the bonding pad may comprise: removing selected portions of the first and third conductive layers. The step (L2) of providing the terminal may include: removing selected portions of the base and the fourth conductive layer.

Wherein providing the third and fourth conductive layers may include: coating the third and fourth conductive layers simultaneously; removing selected portions of the first, third and fourth conductive layers and the base may include: simultaneously etching the The first, third and fourth conductive layers and the base.

The above-mentioned providing the heat sink may include: after curing the adhesive layer and before disposing the semiconductor component, providing a cover on the boss, the cover is located above a top of the boss and adjacent to the top of the boss, At the same time, the top of the boss is covered from above, and extends laterally from the top of the boss along the side direction.

The above step (M2) of providing the cover may include: after grinding and removing the selected portion of the third conductive layer, depositing conductive metal on the protrusion to form a third conductive layer. For example, providing the cover may include: forming a patterned etch stop layer on the third conductive layer; etching the third conductive layer using the patterned etch stop layer to define the cover; and then removing the patterned etch stop layer. Likewise, when forming the pad, the first and third conductive layers can also be etched using the patterned etch stop layer to define the pad.

The above step (G2) making the adhesive layer flow may include: filling the gap with the adhesive layer; it may also include squeezing the adhesive layer to pass through the gap to reach above the boss and the substrate, and on the The top surface of the boss and the top surface of the substrate are adjacent to the part of the notch.

The above-mentioned step (H2) heating and curing the melted adhesive layer system may include: mechanically combining the protrusion and the base with the substrate.

The above step (N2) disposing the semiconductor chip may include: disposing the semiconductor chip above the protrusion, the opening and the through hole, so that the semiconductor chip overlaps the protrusion, the opening and the through hole. Alternatively, arranging the semiconductor chip may also include: arranging the semiconductor chip under the protrusion, the opening and the through hole, so that the semiconductor chip is overlapped by the protrusion, the opening and the through hole.

The above step (N2, O2 and P2) disposing, electrically connecting and thermally connecting the semiconductor chip may include: disposing the semiconductor chip on the stud; electrically connecting the semiconductor chip to the pad, thereby electrically connecting The semiconductor chip is connected to the terminal; and the semiconductor chip is thermally connected to the stud, thereby thermally connecting the semiconductor chip to the base. Alternatively, disposing, electrically connecting and thermally connecting the semiconductor chip may also include: disposing the semiconductor chip under the base; electrically connecting the semiconductor chip to the terminal, thereby electrically connecting the semiconductor chip to the bonding pad and thermally bonding the semiconductor chip to the base, thereby thermally bonding the semiconductor chip to the stud.

The above step (N2, O2 and P2) setting, electrically connecting and thermally connecting the semiconductor chip may include: using a solid crystal material to place a semiconductor chip on the cover; between the semiconductor chip and the pad providing a bonding wire; and providing the die-bonding material between the semiconductor chip and the cover. Alternatively, arranging, electrically connecting and thermally connecting the semiconductor chip may also include: using a die-bonding material to place a semiconductor chip on the base; providing a bonding wire between the semiconductor chip and the terminal; The crystal-bonding material is provided between the semiconductor chip and the base.

The above-mentioned adhesive layer can contact the boss, the base, the cover, the dielectric layer, the routing line, the second conductive hole and the terminal, cover and surround the boss in the side direction, and extend to the The peripheral edge formed by separating the assembly from other assemblies produced in the same batch after the assembly is manufactured.

After the assembly is manufactured and separated from other assemblies produced in the same batch, the base can cover the boss from below, extend laterally from the boss along the side direction, and support the substrate at the same time.

The present invention has several advantages. Including the heat sink can provide excellent heat dissipation effect and prevent heat energy from flowing through the adhesive layer, so the adhesive layer can be a low-cost dielectric with low thermal conductivity and is not easy to delaminate; the boss and the base can be integrally formed To improve reliability; the cover body can be tailored for the semiconductor component to enhance the effect of thermal connection; the adhesive layer can be interposed between the boss and the substrate and between the base and the substrate, so Provides a strong mechanical connection between the heat sink and the substrate; the substrate can provide complex circuitry patterns for flexible multi-layer signal routing; and the base can provide mechanical support for the substrate to prevent it from bending out of shape. In this way, the assembly can be manufactured using a low-temperature process, which can not only reduce stress, but also improve reliability. In addition, this assembly can also use the high-control process that can be easily implemented by circuit boards, lead frames, and tape-and-reel substrate manufacturers. To be manufactured.

Description of drawings

FIG. 1A is a schematic cross-sectional view of a structure for making a boss and a base in a preferred embodiment of the present invention.

FIG. 1B is a schematic cross-sectional view of the structure for making the boss and the base in a preferred embodiment of the present invention.

FIG. 1C is a three-sectional schematic diagram of the structure for making the boss and the base in a preferred embodiment of the present invention.

FIG. 1D is a four-sectional schematic view of the structure for making the boss and the base in a preferred embodiment of the present invention.

FIG. 1E is a schematic top view of FIG. 1D .

Fig. 1F is a schematic bottom view of Fig. 1D.

FIG. 2A is a schematic cross-sectional view of a structure for making an adhesive layer in a preferred embodiment of the present invention.

FIG. 2B is a schematic cross-sectional view of a second structure for making an adhesive layer in a preferred embodiment of the present invention.

FIG. 2C is a schematic top view of FIG. 2B .

Fig. 2D is a schematic bottom view of Fig. 2B.

FIG. 3A is a schematic cross-sectional view of a structure for fabricating a substrate in a preferred embodiment of the present invention.

FIG. 3B is a schematic cross-sectional view of the second structure of the substrate in a preferred embodiment of the present invention.

FIG. 3C is a schematic three-sectional schematic view of the substrate structure in a preferred embodiment of the present invention.

FIG. 3D is a schematic four-sectional schematic view of a structure for fabricating a substrate in a preferred embodiment of the present invention.

FIG. 3E is a schematic cross-sectional view of a five-sectional structure of a substrate fabricated in a preferred embodiment of the present invention.

Fig. 3F is a schematic top view of Fig. 3E.

Fig. 3G is a schematic bottom view of Fig. 3E.

Fig. 4A is a schematic cross-sectional view of a structure for making a heat conducting plate in a preferred embodiment of the present invention.

Fig. 4B is a schematic cross-sectional view of the second structure of the heat conducting plate in a preferred embodiment of the present invention.

Fig. 4C is a three-sectional schematic diagram of the structure for making a heat conducting plate in a preferred embodiment of the present invention.

FIG. 4D is a schematic cross-sectional view of a structure for making a heat conducting plate in a preferred embodiment of the present invention.

FIG. 4E is a schematic cross-sectional view of a structure for making a heat conducting plate in a preferred embodiment of the present invention.

FIG. 4F is a six-sectional schematic diagram of the structure for making a heat conducting plate in a preferred embodiment of the present invention.

FIG. 4G is a schematic cross-sectional view of a structure for making a heat conducting plate in a preferred embodiment of the present invention.

FIG. 4H is a schematic cross-sectional view of the eighth structure of the heat conducting plate in a preferred embodiment of the present invention.

FIG. 4I is a schematic cross-sectional view of nine structures for making a heat conducting plate in a preferred embodiment of the present invention.

Fig. 4J is a schematic cross-sectional view of the structure for making a heat conducting plate in a preferred embodiment of the present invention.

FIG. 4K is a schematic cross-sectional view of the eleventh structure of the heat conducting plate in a preferred embodiment of the present invention.

FIG. 4L is a schematic cross-sectional view of a structure for making a heat conducting plate in a preferred embodiment of the present invention.

FIG. 4M is a schematic cross-sectional view of a structure for making a heat conducting plate in a preferred embodiment of the present invention.

FIG. 4N is a schematic top view of FIG. 4M.

Fig. 4O is a schematic bottom view of Fig. 4M.

FIG. 5A is a schematic cross-sectional view of a semiconductor chip assembly according to a preferred embodiment of the present invention.

FIG. 5B is a schematic top view of a semiconductor chip assembly according to a preferred embodiment of the present invention.

FIG. 5C is a schematic bottom view of a semiconductor chip assembly according to a preferred embodiment of the present invention.

FIG. 6A is a schematic cross-sectional view of a semiconductor chip assembly according to another preferred embodiment of the present invention.

FIG. 6B is a schematic top view of a semiconductor chip assembly according to another preferred embodiment of the present invention.

FIG. 6C is a schematic bottom view of a semiconductor chip assembly according to another preferred embodiment of the present invention.

Label description

sheet metal 10

Surface 12, 14

Patterned Etch Stop 16, 40, 60, 62

Full coverage etch stop 18, 38

Groove 20

Boss 22

Base 24

Adhesive layer 26

opening 28

Substrate 30

First conductive layer 32

Dielectric layer 34

Second conductive layer 36

Routing lines 42, 66

Through hole 44

Gap 46

Holes 48, 50

The third conductive layer 52

The fourth conductive layer 54

The first conductive hole 56

Second conductive hole 58

Pad 64

Cover 68

Terminal 70

Wire 72

Heat sink 74

The first solder resist green paint 76

The second solder mask green paint 78

Covered contacts 80

Heat conduction plate 82

Semiconductor chipsets 100, 200

Semiconductor chip 102, 202

Line 104, 204

Die-bonding material 106, 206

Packaging material 108, 208

Top 110, 210

Bottom 112, 212

Bonding pad 114, 214

Detailed ways

The above and other features and advantages of the present invention will be further illustrated by various embodiments below.

Please refer to Figures 1A to 1F, which are respectively a cross-sectional schematic diagram of a structure for making a boss and a base in a preferred embodiment of the present invention, and a structure for making a boss and a base in a preferred embodiment of the present invention. Schematic cross-sectional view, a schematic three-sectional schematic view of the structure for making a boss and a base in a preferred embodiment of the present invention, a schematic cross-sectional view for a four-sectional view of a structure for making a boss and a base in a preferred embodiment of the present invention, and FIG. 1D Top view schematic diagram, bottom view schematic diagram in Figure 1D. As shown in the figure: the present invention is a semiconductor chip assembly. First, a metal plate 10 is provided, which includes opposite main surfaces (12, 14), as shown in FIG. 1A. The metal plate 10 can be made of various metals, such as copper, aluminum, iron-nickel alloy 42, iron, nickel, silver, gold and alloys thereof. Among them, copper has the advantages of high thermal conductivity, good bonding, and low cost. Therefore, the metal plate 10 of this embodiment uses a copper plate with a thickness of 300 microns.

A patterned etch stop layer 16 and a fully covered etch stop layer 18 are formed on the metal plate 10 , as shown in FIG. 1B . The patterned etch resist layer 16 and the fully covered etch resist layer 18 are photoresist layers deposited on the metal plate 10, which are produced by pressing the photoresist layers on the metal plate 10 at the same time with a hot roller using a compression molding technique. The surfaces (12, 14) where wet spin coating and curtain coating are also suitable photoresist formation techniques. Then, a photomask (not shown in the figure) is attached to the photoresist layer, and then light is selectively passed through the photomask according to known techniques, and then the soluble part of the photoresist layer is removed with a developer to make the light The resist layer is patterned, that is, the patterned etch resist layer 16 is formed. Therefore, the photoresist layer on the surface 12 has a selectively exposed pattern to form a patterned etch stop layer 16, and the photoresist layer on the surface 14 is unpatterned and maintains coverage to form a full coverage. etch stop layer 18 .

A groove 20 dug into but not penetrating the metal plate 10 is formed on the metal plate 10 , as shown in FIG. 1C . The groove 20 is formed by etching the metal plate 10 so that the metal plate 10 forms a pattern defined by the patterned etch stop layer 16 . In this embodiment, the etching method is wet chemical etching, and a top nozzle (not shown in the figure) can be used to spray chemical etching solution on the metal plate 10; or, an etching stopper layer 18 covering the entire surface can be used to provide backside protection , immersing the structure in a chemical etching solution to form the groove 20 . Among other things, the chemical etchant can be highly specific to copper and can carve into the metal plate 10 up to 270 microns. Therefore, the groove 20 extends from the surface 12 into but does not penetrate the metal plate 10, can be 30 microns away from the surface 14, and has a depth of 270 microns; in addition, the chemical etching solution is also resistant to the patterned etch stop layer. The metal plate 10 below 16 causes lateral erosion. Accordingly, the applicable chemical etching solution may be a solution containing alkaline ammonia or a diluted mixture of nitric acid and hydrochloric acid. In other words, the chemical etching solution may be acidic or alkaline. Wherein, the ideal etching time sufficient to form the groove 20 without excessively exposing the metal plate 10 to the chemical etching solution can be determined by trial and error.

The metal plate 10 after removing the patterned etch stop layer 16 and the fully covered etch stop layer 18 is shown in FIG. 1D , FIG. 1E and FIG. 1F . Wherein the photoresist layers have been removed by solvent treatment, and the solvent used may be a sodium hydroxide/potassium hydroxide solution with a pH of 14. As such, the etched metal plate 10 thus includes a protrusion 22 and a base 24 .

The protrusion 22 is an unetched portion protected by the patterned etch stop layer 16 on the metal plate 10 . The protrusion 22 is adjacent to the base 24 , integrally formed with the base 24 , protrudes above the base 24 , and is surrounded by the groove 20 laterally. Wherein the height of the boss 22 is equal to the depth of the groove 20, which is 270 microns, the diameter of the top surface is equal to the diameter of the circular part of the surface 12, which is 1000 microns, and the diameter of the bottom is equal to the diameter adjacent to the base 24 The diameter of the circular part is 1100 microns. Therefore, the protruding post 22 is similar to a frustum in the shape of a flat-topped conical column, its sidewalls are tapered, and its diameter gradually decreases from the base 24 toward its flat circular top surface. Therein, the tapered sidewall is formed by lateral etching of the chemical etchant under the patterned etch stop layer 16 , so the circumference of the top surface and the bottom are concentric, as shown in FIG. 1E .

The base 24 is an unetched portion of the metal plate 10 below the protrusion 22 , extending laterally from the protrusion 22 along a lateral plane, such as left and right sides, with a thickness of 30 μm.

The protrusion 22 and the base 24 can be processed to enhance the bonding with epoxy and solder. For example, the post 22 and the base 24 can be chemically oxidized or micro-etched to produce a rougher surface.

In this embodiment, the protrusion 22 and the base 24 are a single metal (copper) body formed by a subtractive method. Among them, the metal plate 10 can also be stamped with a contact piece having a groove or a hole, and the groove or hole is used to define the position of the boss 22, so that the boss 22 and the base 24 can be formed by stamping. A single metal body; or, the protrusion 22 is formed by an additive method, such as electroplating, chemical vapor deposition (Chemical Vapor Deposition, CVD), physical vapor deposition (Physical Vapor Deposition, PVD) and other techniques, the protrusion 22 is deposited on the base 24; or, the protrusion 22 is formed by a semi-additive method, for example, the upper part of the protrusion 22 can be deposited above the lower part of the protrusion 22 formed by etching; or, the protrusion 22 It can also be sintered on the base 24 . In addition, the post 22 and the base 24 can also be a multi-piece metal body, for example, the solder post 22 is electroplated on the copper base 24; in this case, the post 22 and the base 24 are combined The metallurgical interfaces meet and adjoin each other but are not integrally formed.

Please refer to Figures 2A to 2D, which are respectively a schematic cross-sectional view of a structure for making an adhesive layer in a preferred embodiment of the present invention, a schematic cross-sectional view of a structure for making an adhesive layer in a preferred embodiment of the present invention, and Fig. 2B is a top view schematic diagram, and FIG. 2B is a bottom view schematic diagram. As shown in the figure: provide a B-stage (B-stage) film of uncured epoxy resin as an adhesive layer 26 with a thickness of 150 microns, as shown in FIG. 2A .

The above-mentioned adhesive layer 26 can be various dielectric films or films made of various organic or inorganic electrical insulators. For example, the adhesive layer 26 may initially be a film that is partially cured to a medium-term stage when a thermosetting epoxy resin in resin form is dipped into a reinforcing material. Wherein, the epoxy resin may be FR-4, and other epoxy resins such as multifunctional and bismaleimide-triazine (BT) resins may also be used. Cyanate esters, polyimides, and polytetrafluoroethylene (PTFE) are also useful epoxy resins in certain applications. In addition, the reinforcing material can be electronic-grade glass, or other reinforcing materials, such as high-strength glass, low-dielectric glass, quartz, Kevlar Aramid and paper; moreover, the reinforcing material can also be Can be woven, non-woven or non-directional microfibers. In this way, fillers such as silicon (powdered fused silica) can be added to the film to improve thermal conductivity, thermal shock resistance and thermal expansion matching. Among them, commercially available prepregs can be used, such as the SPEEDBOARD C film of W.L. Gore & Associates in Oakley, Wisconsin, USA, as an example.

The adhesive layer 26 has at least one opening 28 , as shown in FIG. 2B , FIG. 2C and FIG. 2D . The opening 28 is a central window penetrating the adhesive layer 26 and is formed by mechanically drilling through the film, with a diameter of 1150 microns. Wherein, the opening 28 can also be made by other techniques, such as stamping and punching.

Please refer to Figures 3A to 3G, which are respectively a schematic cross-sectional view of a structure for making a substrate in a preferred embodiment of the present invention, a schematic cross-sectional view of a structure for making a substrate in a preferred embodiment of the present invention, and a schematic cross-sectional view of a structure for making a substrate in a preferred embodiment of the present invention. The three-sectional schematic diagram of the structure of the substrate in the preferred embodiment, the four-sectional schematic diagram of the structure of the substrate in a preferred embodiment of the present invention, the five-sectional schematic diagram of the structure of the substrate in a preferred embodiment of the present invention, and FIG. 3E The schematic top view of Fig. 3E and the bottom view schematic diagram of Fig. 3E. As shown in the figure: a substrate 30 is provided, which includes a first conductive layer 32 , a dielectric layer 34 and a second conductive layer 36 , as shown in FIG. 3A . The first conductive layer 32 contacts the dielectric layer 34 and extends above it, the second conductive layer 36 contacts the dielectric layer 34 and extends below it, and the dielectric layer 34 contacts the first and second conductive layers ( 32, 36) and fit in between. The first and second conductive layers (32, 36) are electrical conductors, while the dielectric layer 34 is an electrical insulator. For example, the first and second conductive layers (32, 36) are copper plates with a thickness of 40 microns and no pattern, and after successive steps of removing the photoresist layer and cleaning, the thickness will be reduced to 30 microns, and the dielectric Layer 34 is 120 microns thick epoxy.

A fully covered etch stop layer 38 and a patterned etch stop layer 40 are respectively formed on the first and second conductive layers ( 32 , 36 ) of the substrate 30 , as shown in FIG. 3B . The full coverage etch stop layer 38 and the patterned etch stop layer 40 are both photoresist layers and are similar to the aforementioned etch stop layers 18 and 16 respectively. The etch stop layer 38 has no pattern and covers the first conductive layer 32 , while the etch stop layer 40 has a pattern that can selectively expose the second conductive layer 36 .

In FIG. 3C , selected portions of the second conductive layer 36 of the substrate 30 have been removed by etching, thereby forming a patterned wiring layer defined by the patterned etch stop layer 40 . Wherein, the etching is backside wet chemical etching, which is similar to the etching method used for the metal plate. At this time, the first conductive layer 32 is still a copper plate without a pattern, and the second conductive layer 36 is etched to cause the dielectric layer 34 to be exposed, so that the second conductive layer 36 is converted from a patternless layer to a pattern layer. In this embodiment, in order to facilitate the comparison of various figures, the second conductive layer 36 is generally located below the dielectric layer 34 in the figure, but in this step, the structure can be turned upside down to enhance the etching effect by gravity.

In the substrate 30 of FIG. 3D , the full-covered etch stop layer 38 and the patterned etch stop layer 40 have been removed. The method of stripping the etch stop layers 38 and 40 may be the same as the method of stripping the etch stop layers 16 and 18 . The etched second conductive layer 36 includes routing lines 42 . Therefore, the routing line 42 is the unetched portion of the second conductive layer 36 protected by the patterned etch stop layer 40 . In addition, the routing line 42 is a copper line contacting the dielectric layer 34 and extending below it.

The substrate 30 has a through hole 44 , as shown in FIG. 3E , FIG. 3F and FIG. 3G . The through hole 44 is a central window that penetrates the substrate 30, and is formed by mechanically drilling the first conductive layer 32 and the dielectric layer 34 (but the second conductive layer 36 is not included, because this layer has been penetrated. Wet chemical etch removed from this area), the diameter of the via 44 is 1150 microns. Therein, the through hole 44 can also be formed by other techniques, such as stamping and stamping. Preferably, the opening 28 (as shown in FIG. 2B ) has the same diameter as the through hole 44 and is formed in the same manner with the same drill bit on the same drill floor.

The above-mentioned substrate 30 is shown here as a laminated structure, but the substrate 30 can also be other multi-layer electrical connected objects, such as a ceramic board or a printed circuit board. Likewise, the substrate 30 may additionally include several layers embedded with circuits.

Please refer to Figures 4A to 4O, which are respectively a schematic cross-sectional view of a structure for making a heat conducting plate in a preferred embodiment of the present invention, a schematic cross-sectional view of a structure for making a heat conducting plate in a preferred embodiment of the present invention, and a schematic cross-sectional view of the structure of the present invention. A schematic diagram of three cross-sections of the structure for making a heat conduction plate in a preferred embodiment, a schematic diagram of four cross-sections of a structure for making a heat conduction plate in a preferred embodiment of the present invention, a schematic cross-section of a structure for making a heat conduction plate in a preferred embodiment of the present invention Schematic diagram, six sectional schematic diagrams of the structure of making heat conducting plate in a preferred embodiment of the present invention, seven sectional schematic diagrams of making the structure of heat conducting plate in a preferred embodiment of the present invention, making the structure of heat conducting plate in a preferred embodiment of the present invention Structure eight cross-sectional schematic diagrams, structure nine cross-sectional schematic diagrams of making heat conducting plates in a preferred embodiment of the present invention, structure ten cross-sectional schematic diagrams of making heat conducting plates in a preferred embodiment of the present invention, in a preferred embodiment of the present invention A schematic cross-sectional view of an eleven-section structure for making a heat-conducting plate, a schematic cross-sectional view of a structure twelve for making a heat-conducting plate in a preferred embodiment of the present invention, a schematic cross-sectional view of a structure thirteen for making a heat-conducting plate in a preferred embodiment of the present invention, and FIG. 4M is a schematic top view, and FIG. 4M is a schematic bottom view. As shown in the figure: the heat conducting plate of the present invention includes the protrusion 22 , the base 24 , the adhesive layer 26 and the substrate 30 . Wherein the adhesive layer 26 is arranged on the base 24, as shown in FIG. contact and position on the base 24 . Preferably, the post 22 is located at the center of the opening 28 after being inserted and penetrated through the opening 28 without touching the adhesive layer 26 .

The substrate 30 is disposed on the adhesive layer 26 , as shown in FIG. 4B . The substrate 30 descends onto the adhesive layer 26 , so that the protrusion 22 is inserted upwards and passes through the through hole 44 , and the substrate 30 contacts and is positioned on the adhesive layer 26 . Preferably, the protrusion 22 is located in the center of the through hole 44 after being inserted into the through hole 44 without contacting the substrate 30 . Therefore, a gap 46 is formed in the through hole 44 and between the protrusion 22 and the substrate 30 . The notch 46 laterally surrounds the protrusion 22 and is laterally surrounded by the base plate 30 . In addition, the opening 28 and the through hole 44 are aligned with each other and have the same diameter.

At this time, the substrate 30 is placed on and in contact with the adhesive layer 26 , and extends above the adhesive layer 26 . The protrusion 22 extends through the opening 28 into the through hole 44 and reaches the dielectric layer 34 . The protrusion 22 is 60 microns lower than the top surface of the first conductive layer 32 and exposed in an upward direction through the through hole 44 . The adhesive layer 26 is in contact with and interposed between the base 24 and the substrate 30 , but keeps a distance from the dielectric layer 34 . At this stage, the adhesive layer 26 is still a film of B-stage uncured epoxy resin, and there is air in the gap 46 .

The adhesive layer 26 flows into the gap 46 after heating and pressing, as shown in FIG. 4C . The method of forcing the adhesive layer 26 to flow into the notch 46 is to apply downward pressure to the first conductive layer 32 and/or apply upward pressure to the base 24, that is, to press the base 24 and the substrate 30 relative to each other. , so as to apply pressure to the adhesive layer 26; at the same time, the adhesive layer 26 is also heated. The heated adhesive layer 26 can be shaped arbitrarily under pressure. Therefore, after the adhesive layer 26 between the base 24 and the substrate 30 is squeezed, it changes its original shape and flows upward into the gap 46 . Therein, the base 24 and the substrate 30 continue to be pressed against each other until the adhesive layer 26 fills the gap 46 . In addition, after the gap between the base 24 and the substrate 30 is narrowed, the adhesive layer 26 still fills up the narrowed gap. For example, the base 24 and the first conductive layer 32 can be arranged between the upper and lower press tables (not shown) of a press machine, and an upper baffle plate and upper buffer paper (shown in the figure) can be placed (not shown in the figure) is sandwiched between the first conductive layer 32 and the upper pressing table, and the lower baffle plate and the lower buffer paper (not shown in the figure) are sandwiched between the base 24 and the lower pressing table. From top to bottom, the composite body thus constituted is an upper pressing table, an upper baffle, an upper buffer paper, a substrate 30, an adhesive layer 26, a base 24, a lower buffer paper, a lower baffle, and a lower pressing table. Additionally, the laminate can be positioned on the hold down table using tooling feet (not shown) extending upwardly from the hold down table and through alignment holes (not shown) in the base 24 .

Then, the upper and lower pressing tables are heated and pushed together, thereby heating and pressing the adhesive layer 26 . The baffle plate is used to disperse the heat of the press table, so that the heat is evenly applied to the base 24 , the substrate 30 and even the adhesive layer 26 . The buffer paper distributes the pressure of the pressing table, so that the pressure is evenly applied to the base 24 , the substrate 30 and even the adhesive layer 26 . Initially, the second conductive layer 36 protrudes into the adhesive layer 26 and is embedded therein, causing the dielectric layer 34 to contact and press against the adhesive layer 26 . As the pressing table continues to operate and continue to heat, the adhesive layer 26 between the base 24 and the substrate 30 is squeezed and begins to melt, thus flowing upward into the gap 46, passing through the dielectric layer 34, and finally reaching the first conductive layer. Layer 32. For example, after the uncured epoxy resin is heated and melted, it is pressed into the gap 46 , but the reinforcing material and the filler remain between the base 24 and the substrate 30 . The adhesive layer 26 rises faster than the protrusion 22 in the through hole 44 , and finally fills up the gap 46 . The adhesive layer 26 also rises to a position slightly higher than the notch 46 , and overflows to the top surface of the protrusion 22 and the top surface of the first conductive layer 32 adjoining the notch 46 before the pressing platform stops. This can happen if the film thickness is slightly larger than necessary. In this way, the adhesive layer 26 forms a covering thin layer on the top surface of the protrusion 22 . The pressing table stops moving after touching the protrusion 22 , but still continues to heat the adhesive layer 26 .

The adhesive layer 26 flows upward in the gap 46 (shown by the upward thick arrow), the protrusion 22 and the base 24 move upward relative to the substrate 30 as shown by the upward thin arrow, and the The downward movement of the substrate 30 relative to the protrusion 22 and the base 24 is shown by the downward thin arrow.

Adhesive layer 26 in FIG. 4D has cured. For example, after the pressing table stops moving, it still continues to clamp the boss 22 and the base 24 and supply heat, thereby converting the melted B-stage epoxy resin into C-stage (C-stage) cured or hardened epoxy. resin. Thus, the epoxy cures in a manner similar to known multilayer laminations. After the epoxy resin has cured, the press table is separated so that the structure can be removed from the press machine. The cured adhesive layer 26 provides strong mechanical connection between the protrusion 22 and the substrate 30 and between the base 24 and the substrate 30 . The adhesive layer 26 can withstand general operating pressure without deformation and damage, and only temporarily distorts when it encounters excessive pressure; moreover, the adhesive layer 26 can also absorb between the boss 22 and the substrate 30 The thermal expansion mismatch between the substrates 30 .

At this stage, the protrusion 22 is substantially coplanar with the first conductive layer 32 , and the adhesive layer 26 and the first conductive layer 32 extend to a top surface facing the upward direction. For example, the thickness of the adhesive layer 26 between the base 24 and the second conductive layer 36 is 90 microns, which is 60 microns less than its initial thickness of 150 microns; 30 is lowered by 60 microns relative to the protrusion 22 . The protrusion 22 has a height of 270 microns which is substantially equal to the first conductive layer 32 (30 microns), the dielectric layer 34 (150 microns), the second conductive layer 36 (30 microns) and the adhesive layer 26 (90 microns) below. μm) binding height. In addition, the boss 22 is still located at the center of the opening 28 and the through hole 44 and keeps a distance from the substrate 30 , and the adhesive layer 26 fills the space between the base 24 and the substrate 30 and fills up the gap. 46. For example, the gap 46 (and the adhesive layer 26 between the protrusion 22 and the substrate 30 ) is 75 microns wide at the top surface of the protrusion 22 ((1150-1000)/2). The adhesive layer 26 extends across the dielectric layer 34 in the gap 46 . In other words, the adhesive layer 26 in the notch 46 extends along the upward direction and a downward direction and spans the thickness of the dielectric layer 34 on the outer sidewall of the notch 46 . The adhesive layer 26 also includes a thin top portion above the notch 46 that contacts the stud 22 and the top surface of the first conductive layer 32 and extends 10 μm above the stud 22 .

The protrusion 22 , the adhesive layer 26 and the top of the first conductive layer 32 are removed, as shown in FIG. 4E . The tops of the protrusions 22 , the adhesive layer 26 and the first conductive layer 32 are removed by grinding, for example, using a rotating diamond grinding wheel and distilled water to treat the top of the structure. At first, the diamond grinding wheel only grinds away the adhesive layer 26; as the grinding continues, the adhesive layer 26 becomes thinner due to the downward movement of the ground surface. The diamond grinding wheel will eventually contact the boss 22 and the first conductive layer 32 (not necessarily at the same time), thus starting to grind the boss 22 and the first conductive layer 32; after continuous grinding, the boss 22, the adhesive layer 26 And the first conductive layer 32 becomes thinner due to the downward movement of the worn surface. After grinding continues until the desired thickness is removed, rinse the structure with distilled water to remove dirt.

The grinding step above grinds off the top of the adhesive layer 26 by 25 microns, the top of the stud 22 by 15 microns, and the top of the first conductive layer 32 by 15 microns. Wherein, the reduction in thickness has little effect on the protrusion 22 or the adhesive layer 26 , but the thickness of the first conductive layer 32 is greatly reduced from 30 microns to 15 microns. So far, the protrusion 22 , the adhesive layer 26 and the first conductive layer 32 are located on the top surface of the dielectric layer 34 facing the upward direction and facing the smooth splicing side.

The structure shown in FIG. 4F has holes 48 and 50 . The hole 48 is a blind hole extending through the first conductive layer 32 and the dielectric layer 34 to the routing line 42 , but keeping a distance from the adhesive layer 26 . The hole 50 is also a blind hole, which extends through the base 24 and the adhesive layer 26 to the routing line 42 , but keeps a distance from the dielectric layer 34 . The holes (48, 50) are formed by laser drilling, but other techniques such as mechanical drilling and plasma etching can also be used. Wherein, the holes (48, 50) may have tapered sidewalls and a diameter that decreases with depth, but for ease of illustration, the holes (48, 50) in the drawings all have vertical sidewalls and fixed diameter.

As shown in FIG. 4G , the structure has a third conductive layer 52 , a fourth conductive layer 54 , a first conductive hole 56 and a second conductive hole 58 . The third conductive layer 52 is deposited on and in contact with the aforementioned side top surfaces of the protrusion 22 , the adhesive layer 26 and the first conductive layer 32 . At the same time, the protrusion 22 , the adhesive layer 26 and the first conductive layer 32 are covered from above. Wherein, the third conductive layer 52 is a patternless copper layer with a thickness of 15 microns, and is integrally formed with the first conductive hole 56 .

The fourth conductive layer 54 is deposited on the bottom surface of the base 24 and is in contact with it, while covering the base 24 from below. Wherein, the fourth conductive layer 54 is an unpatterned copper layer with a thickness of 15 microns, and is integrally formed with the second conductive hole 58 .

The first conductive hole 56 extends from the first conductive layer 32 into the hole 48 . The first conductive hole 56 is deposited on and in contact with the dielectric layer 34 and the routing line 42 in the hole 48 . Wherein, the first conductive hole 56 is a coated through hole, which can electrically connect the first and third conductive layers ( 32 , 52 ) to the routing line 42 .

The second conductive hole 58 extends from the base 24 into the hole 50 . The second conductive hole 58 is deposited on and in contact with the adhesive layer 26 and the routing line 42 in the hole 50 . Wherein, the second conductive hole 58 is a coated through hole, which can electrically connect the base 24 and the fourth conductive layer 54 to the routing line 42 .

For example, the structure may be immersed in an activator solution, thereby causing the dielectric layer 34 and the adhesive layer 26 on the sidewalls of the holes (48, 50), respectively, to catalyze the electroless copper plating, followed by a first The copper layer is provided on the protrusion 22, the base 24, the adhesive layer 26, the first conductive layer 32, the routing line 42 (located on the opposite side of the structure) and the holes (48, 50) in an electroless plating manner. On the sidewall, a second copper layer is then electroplated on the first copper layer. The thickness of the first copper layer is about 2 microns, and the thickness of the second copper layer is about 13 microns, so the total thickness of the coated copper layer is about 15 microns. In this way, the thickness of the first conductive layer 32 is increased to about 40 microns (25+15), wherein, after successive steps of removing the photoresist layer and cleaning, the thickness of the first conductive layer 32 will decrease. to about 30 microns; similarly, the thickness of the base 24 is increased to about 55 microns (30+25), but after successive steps of removing the photoresist layer and cleaning, the thickness will also be reduced to about 45 microns.

The third conductive layer 52 serves as a cover layer of the protrusion 22 and a thickened layer of the first conductive layer 32 , and the fourth conductive layer 54 is a thickened layer of the base 24 . In addition, the first and second conductive holes (56, 58) are respectively formed in the holes (48, 50). For ease of illustration, the base 24 , the first to fourth conductive layers ( 32 , 36 , 52 , 54 ) and the first and second conductive holes ( 56 , 58 ) are all shown as a single layer. Due to the homogeneous coating of copper, the boundary between the protrusion 22 and the third conductive layer 52, the boundary between the base 24 and the fourth conductive layer 54, and the boundary between the first conductive layer 32 and the third conductive layer The boundaries between the 52 (both shown in dashed lines) may be imperceptible or even imperceptible. However, the boundary between the adhesive layer 26 and the third conductive layer 52 adjacent to the protrusion 22 is clearly visible. Likewise, the boundary between the dielectric layer 34 and the first conductive hole 56 in the hole 48 and the boundary between the adhesive layer 26 and the second conductive hole 58 in the hole 50 are also clearly visible. In addition, for ease of illustration, the first and second conductive holes ( 56 , 58 ) are shown as pillars filling the holes ( 48 , 50 ) instead of hollow tubes.

Patterned etch stop layers 60 and 62 are respectively provided on the upper and lower surfaces of the structure shown in FIG. 4H . The patterned etch stop layers 60 and 62 as shown are similar to the photoresist layers of the etch stop layers 16 and 40 . The etch stop layer 60 has a pattern that can selectively expose the third conductive layer 52 , and the etch stop layer 62 has a pattern that can selectively expose the fourth conductive layer 54 .

In the structure shown in FIG. 4I, the first and third conductive layers (32, 52) have been removed by etching to form a pattern defined by a patterned etch stop layer 60; the base 24 and the Selected portions of the fourth conductive layer 54 are also etched away to form a pattern defined by the patterned etch stop layer 62 . The etching was similar to wet chemical etching applied to the front and back of the metal plate. For example, an upper nozzle and a lower nozzle (both not shown in the figure) can be used to spray the chemical etching solution on the top surface and the bottom surface of the structure, or the structure can be immersed in the chemical etching solution. The first and third conductive layers (32, 52) are etched and penetrated by the above-mentioned chemical etching solution to expose the adhesive layer 26 and the dielectric layer 34, so that the original patternless first and third conductive layers (32, 52) Convert to pattern layer. Wherein, the chemical etchant also etches through the base 24 and the fourth conductive layer 54 to expose the adhesive layer 26 .

In FIG. 4J , the patterned etch stop layers 60 and 62 on the structure have been removed, and the removal method can be the same as that of the etch stop layers 16 and 18 .

The etched first and third conductive layers ( 32 , 52 ) include a pad 64 and a routing line 66 , and the etched third conductive layer 52 includes a cover 68 . Wherein the welding pad 64 and the routing line 66 are the unetched parts of the first and third conductive layers (32, 52) protected by the patterned etch stop layer 60, and the cover 68 is the third conductive layer 52 is protected by the patterned etch stop layer 60 from being etched. Therefore, the first and third conductive layers ( 32 , 52 ) become a pattern layer, which includes the pad 64 and the routing line 66 but does not include the cover 68 . In addition, the routing line 66 is a copper wire, which contacts the dielectric layer 34 and extends above it, and is adjacent to and electrically connected to the first conductive hole 56 and the pad 64 .

The etched base 24 and the fourth conductive layer 54 include a central portion of the base 24 and a terminal 70, wherein the central portion of the base 24 is covered by the fourth conductive layer 54 from below (hereinafter collectively referred to as the base 24 /54). The pedestal 24 / 54 is the portion of the pedestal 24 and the fourth conductive layer 54 protected by the patterned etch stop layer 62 from being etched, and extends laterally beyond the protrusion 22 by 1000 μm. The terminal 70 is an unetched portion of the base 24 and the fourth conductive layer 54 protected by the patterned etch stop layer 62 , which contacts the adhesive layer 26 and extends below it. The base 24 / 54 itself is still a non-patterned layer, but a patterned layer including the terminals 70 and maintaining a lateral distance from the base 24 is formed outside the periphery of the base 24 . Therefore, the terminal 70 and the base 24 are separated from each other, and the terminal 70 is no longer a part of the base 24 . In addition, the second conductive hole 58 is adjacent to the terminal 70 and forms an electrical connection between the routing line 42 and the terminal 70 .

The routing lines 42 and 66 , the first and second conductive holes 56 and 58 , the pad 64 and the terminal 70 together form a wire 72 . Likewise, a conductive path between the pad 64 and the terminal 70 sequentially passes through the routing line 66 , the first conductive hole 56 , the routing line 42 and the second conductive hole 58 (and vice versa). The wire 72 provides a vertical (from top to bottom) route from the pad 64 to the terminal 70, and the wire 72 is not limited to this configuration, for example, the pad 64 can also be directly formed on the first conductive hole 56 , thereby saving the routing line 66 ; and the second conductive hole 58 is electrically connected to the terminal 70 through a routing line defined by the patterned etching resist layer 62 under the adhesive layer 26 . Furthermore, the aforementioned conductive paths may include other conductive vias and routing lines (which are located in the first, second and/or other conductive layers) and passive components, such as resistors and capacitors disposed on other pads.

The heat sink 74 is formed by the protrusion 22 , the base 24 / 54 and the cover 68 . Wherein the boss 22 is integrally formed with the base 24/54, and the cover 68 is located above the top of the boss 22, adjoins the top of the boss 22, and covers the top of the boss 22 from above, and is formed by The top of the protrusion 22 extends laterally. After the cover 68 is installed, the protrusion 22 is located in the central area of the circumference of the cover 68, and the cover 68 also contacts and covers a part of the adhesive layer 26 below it from above, and this part of the adhesive layer 26 Coplanar with the boss 22, adjacent to the boss 2

2, while surrounding the protrusion 22 laterally.

The above-mentioned heat sink 74 is essentially an inverted T-shaped heat sink, which includes a column (ie, the boss 22), a wing (ie, the part of the base 24/54 extending laterally from the column), and a heat conduction pad (ie, Cover 68).

In the structure shown in FIG. 4K, a first solder resist green paint 76 is provided on the dielectric layer 34, the third conductive layer 52 and the cover 68, and on the base 24/54, the adhesive A second solder resist green paint 78 is also provided on the layer 26 and the terminal 70 . Wherein, the first solder resist green paint 76 is an electrical insulation layer, which can be patterned according to our choice to expose the solder pad 64 and the cover 68, and cover the exposed portion of the dielectric layer 34 and the cover body 68 from above. The route is line 66. wherein the thickness of the first solder resist green paint 76 above the pad 64 is 25 microns, and the first solder resist green paint 76 extends 55 microns (30+25) above the dielectric layer 34; and the first solder resist green paint 76 extends above the dielectric layer 34; The second solder resist green paint 78 is also an electrical insulating layer, which can be patterned to expose the base 24 / 54 and the terminal 70 according to our choice, and cover the exposed part of the adhesive layer 26 from below. The thickness of the second solder resist green paint 78 below the terminal 70 is 25 microns, and the second solder resist green paint 78 extends 70 microns (45+25) below the adhesive layer 26 .

The above-mentioned first and second solder resist green paints (76, 78) are initially a light-developing liquid resin coated on the structure, and then formed on the first and second solder resist green paints (76, 78) patterns, which make the light selectively pass through the mask (not shown in the figure), and then use a developing solution to remove the soluble parts of the first and second solder resist green paints (76, 78), and finally perform hard baking. The above steps are known techniques.

In the structure shown in FIG. 4L , covered contacts 80 are provided on the base 24 / 54 , the pad 64 , the cover 68 and the terminal 70 . The covered contact 80 is a multi-layer metal plating, which contacts the solder pad 64 and the cover 68 from above while covering its exposed portion, and contacts the base 24 / 54 and the terminal 70 from below while covering its exposed portion. For example, a nickel layer is disposed on the base 24/54, the welding pad 64, the cover 68 and the terminal 70 by electroless plating, and then a gold layer is disposed on the nickel layer by electroless plating. , wherein the inner nickel layer is about 3 microns thick, and the surface gold layer is about 0.5 microns thick, so the thickness of the covered contact 80 is about 3.5 microns.

The surface treatment of the base 24/54, the solder pad 64, the cover 68, and the terminal 70 with the covered contact 80 described above has several advantages, including: the inner nickel layer provides the primary mechanical and electrical connection and / or heat connection, and the surface gold layer then provides a wettable surface to facilitate solder reflow; the covered contact 80 also protects the base 24/54, the solder pad 64, the cover 68 and the terminal 70 from corrosion ; and the covered contact 80 may contain various metals to meet the needs of the external connection medium. For example, a silver layer over a nickel layer can be used with solder or wire bonding. Wherein, for the convenience of description, the base 24/54, the welding pad 64, the cover 68 and the terminal 70 provided with the covered contact 80 are all shown in a single layer, and the covered contact 80 and the base 24/54, The boundary (not shown) between the pad 64 , the cover 68 and the terminal 70 is a copper/nickel interface. So far, the fabrication of a heat conducting plate 82 is completed.

The edge of the heat conducting plate 82 has been separated from the supporting frame and/or the adjacent heat conducting plate produced in the same batch along the cutting line, as shown in FIG. 4M , FIG. 4N and FIG. 4O . The heat conducting plate 82 includes the base 24/54, the adhesive layer 26, the substrate 30, the terminal 70, the heat sink 74, and the first and second solder resist green paints (76, 78). Wherein, the substrate 30 includes the dielectric layer 34, the routing lines (42, 66), the first conductive hole 56 and the pad 64; the heat sink 74 includes the bump 22, the base 24/54 and The cover body 68 . Wherein, the wire 72 is composed of the routing line ( 42 , 66 ), the first and second conductive holes ( 56 , 58 ), the welding pad 64 and the terminal 70 .

After the protrusion 22 extends through the opening 28 and enters the through hole 44 , it is still located at the center of the opening 28 and the through hole 44 , and is located at an adjacent portion of the adhesive layer 26 above the dielectric layer 34 . Coplanar. The post 22 maintains a flat-topped cone shape with tapered sidewalls such that its diameter decreases upward from the base 24 / 54 toward the flat dome adjacent to the cover 68 . The base 24 / 54 covers the protrusion 22 from below and keeps a distance from the peripheral edge of the heat conducting plate 82 . The cover 68 is located above the protruding post 22 , adjacent thereto and thermally connected. The cover 68 also covers the top of the protruding post 22 from above and extends laterally from the top of the protruding post 22 . The cover 68 also touches and covers a portion of the adhesive layer 26 from above. The portion of the adhesive layer 26 adjoins the protrusion 22 , is coplanar with the protrusion 22 , and surrounds the protrusion 22 laterally. The cover 68 is also coplanar with the pad 64 .

The adhesive layer 26 is disposed on and extends over the base 24/54. The adhesive layer 26 is in contact with and interposed between the protrusion 22 and the dielectric layer 34 for filling the space between the protrusion 22 and the dielectric layer 34 . In addition, the adhesive layer 26 is also in contact with and interposed between the base 24 / 54 and the substrate 30 to fill the space therebetween. The adhesive layer 26 covers and surrounds the protrusion 22 along the side direction, and the adhesive layer 26 has been cured.

The substrate 30 is disposed on and in contact with the adhesive layer 26 and also extends above the lower adhesive layer 26 and the base 24 / 54 . Wherein, the first conductive layer 32 (and the pad 64 and the routing line 66) contact the dielectric layer 34 and extend above it; the dielectric layer 34 contacts the second conductive layer 36 (including the routing line 42 ) and extend above it, and the dielectric layer 34 is interposed between the first and second conductive layers 32, 36; the second conductive layer 36 (including the routing line 42) is in contact with the adhesive layer 26 and embedded set it.

The protrusions 22 , the base 24 / 54 and the cover 68 all keep a distance from the substrate 30 . Therefore, the substrate 30 is mechanically connected to the heat sink 74 and electrically isolated from each other.

After the heat conduction plate 82 produced in the same batch is cut, the adhesive layer 26, the dielectric layer 34 and the first and second solder resist green paints (76, 78) all extend to the vertical edge formed by cutting.

The pad 64 is an electrical interface tailored for semiconductor components such as semiconductor chips, which will be disposed on the cover 68 in subsequent manufacturing processes. The terminal 70 is an electrical interface tailor-made for the next layer of assembly. For example, the next layer of assembly can be a printed circuit board, and the heat conducting plate 82 is arranged on the printed circuit board in the subsequent process. superior. The cover 68 is a thermal interface tailor-made for the semiconductor component. The base 24/54 is a thermal interface tailored for the printed circuit board. In addition, the cover 68 is thermally connected to the base 24 / 54 via the boss 22 .

The pads 64 and the terminals 70 are offset from each other in the vertical direction and are respectively exposed on the top surface and the bottom surface of the heat conducting plate 82 , thereby providing vertical routing between the semiconductor device and the next layer assembly. And the top surfaces of the solder pad 64 and the cover 68 located above the dielectric layer 34 are coplanar with each other, and the bottom surfaces of the base 24 / 54 and the terminals 70 located below the adhesive layer 26 are also coplanar with each other. Wherein, for ease of illustration, the wire 72 is shown as a continuous circuit trace in the cross-sectional view; however, the wire 72 generally provides horizontal signal routing in the X and Y directions at the same time, that is, the pad 64 and the terminal 70 are connected to each other. Lateral dislocations are formed in the X and Y directions, and the routing lines 42 and 66 respectively or jointly form paths in the X and Y directions.

The heat sink 74 can dissipate the heat energy generated by the semiconductor components subsequently disposed on the cover 68 to the next layer of assembly connected to the base 24 / 54 . The heat energy generated by the semiconductor component flows into the cover 68 , enters the protrusion 22 from the cover 68 , and enters the base 24 / 54 through the protrusion 22 . Thermal energy is dissipated from the base 24/54 in the downward direction, for example to a heat sink below. Similarly, the heat sink 74 can also dissipate the heat energy generated by the semiconductor components subsequently disposed on the base 24 / 54 to the next layer of assembly connected to the cover 68 .

The protrusions 22 of the heat conducting plate 82 , the first and second conductive holes 56 and 58 or the routing lines 42 and 66 are not exposed. The boss 22 is covered by the cover 68, and the first and second conductive holes (56, 58) and the routing lines 42 and 66 are covered by the first solder resist green paint 76. As for the top of the adhesive layer 26 The surface is covered by the cover 68 and the first solder resist green paint 76 at the same time. For ease of illustration, the protrusion 22 , the adhesive layer 26 , the first and second conductive holes ( 56 , 58 ) and the routing lines 42 and 66 are shown in dotted lines in FIG. 4N .

The heat conduction plate 82 also includes other wires 72, which are basically composed of the first and second conductive holes (56, 58), the routing lines 42 and 66, the pads 64 and the terminals 70, and There is a multi-layer conductive path between the pad 64 and the terminal 70 . For ease of description, only a single wire 72 is illustrated and illustrated here. In the wire 72, the first and second conductive holes (56, 58), the solder pad 64 and the terminal 70 generally have the same shape and size, while the routing lines 42 and 66 usually adopt different routing configurations . For example, some wires 72 are spaced, separated from each other, and electrically isolated, while some wires 72 cross each other or lead to the same pad 64 , routing line ( 42 , 66 ) or terminal 70 and are electrically connected to each other. Likewise, some of the pads 64 can be used to receive independent signals, while some of the pads 64 share a signal, power or ground terminal. In addition, part of the wire 72 may include the routing line 42 and the first and second conductive holes (56, 58) to provide multi-layer routing, while part of the wire 72 does not contain the routing line 42 and the first and second conductive holes ( 56, 58), and only provide single-layer routing on the first conductive layer 32.

The structure of the heat conducting plate 82 can be adjusted to be used with multiple chips, so that each input/output signal is directed to a respective terminal 70 from a respective pad 64 , and each pad 64 is directed to the same ground terminal 70 when grounded.

Oxides and residues on exposed metal can be removed at various stages of fabrication by a simple cleaning step, such as a short oxygen plasma cleaning step that can be performed on the structure of the present invention. Alternatively, the structures of the invention may be subjected to a brief wet chemical cleaning step using a potassium permanganate solution. Likewise, distilled water can also be used to rinse the structure of the present invention to remove dirt. This cleaning step cleans the desired surface without significantly affecting or damaging the structure.

An advantage of the present invention is that the conductor 72 does not need to be separated or diced therefrom for the sink or associated circuitry after it is formed. The junction can be separated during the wet chemical etching step that forms the pad 64 , the routing line 66 , the cover 68 and the terminal 70 .

The heat conducting plate 82 may include alignment holes (not shown) drilled or cut through the adhesive layer 26 , the substrate 30 and the first and second solder resist green paints ( 76 , 78 ). In this way, when the heat conduction plate 80 needs to be arranged on a lower carrier in the subsequent process, the pins of the tool can be inserted into the alignment holes, so as to place the heat conduction plate 82 in position.

The heat conducting plate 82 can omit the cover 68 . To achieve this purpose, the patterned etch stop layer 60 can be adjusted so that the entire third conductive layer 52 above the through hole 44 is exposed to the chemical etching solution used to form the pad 64 and the routing line 66 .

The heat conducting plate 82 can accommodate multiple semiconductor components instead of only a single semiconductor component. To achieve this, the patterned etch stop layer 16 can be adjusted to define more posts 22, the adhesive layer 26 can be adjusted to include more openings 28, the substrate 30 can be adjusted to include more vias 44, the patterned The etch resist layer 40 is used to define more routing lines 42, the patterned etch resist layers 60 and 62 are adjusted to define more pads 64, routing lines 66, lids 68 and terminals 70, and the first and second anti- Weld green paint (76, 78) to include more openings. Likewise, the substrate 30 may also include more routing lines 42 and conductive holes 56 and 58 . Components other than the terminals 70 can be shifted laterally to provide a 2x2 array of four semiconductor components. In addition, the cross-sectional shape and height (ie, side shape) of some but not all components can also be adjusted. For example, the solder pad 64 , the cover 68 and the terminal 70 can maintain the same side profile, while the routing lines 42 and 66 have different routing configurations.

Please refer to FIG. 5A-FIG. 5C, which are respectively a cross-sectional schematic view of a semiconductor chip assembly in a preferred embodiment of the present invention, a schematic top view of a semiconductor chip assembly in a preferred embodiment of the present invention, and a preferred implementation of the present invention. A schematic bottom view of the semiconductor chip assembly of the example. As shown in the figure: the semiconductor component in this embodiment is a chip disposed on the cover. The chip is overlapped on the protrusion and is electrically connected to the welding pad, and then electrically connected to the terminal. The chip is also thermally connected to the cover, thereby forming a thermal connection with the base.

The semiconductor chip assembly body 100 of the present embodiment comprises a heat conducting plate 82, a semiconductor chip 102, a bonding wire 104, a die-bonding material 106 and a package material 108, and the semiconductor chip 102 comprises a top surface 110, a The bottom surface 112 and a bonding pad 114, wherein the top surface 110 is an active surface and includes the bonding pad 114, and the bottom surface 112 is a thermal contact surface.

The semiconductor chip 102 is disposed on the heat sink 74 , electrically connected to the substrate 30 , and thermally connected to the heat sink 74 . In detail, the semiconductor chip 102 is disposed on the cover 68 , located within the periphery of the cover 68 , overlapping the protrusion 22 but not overlapping the substrate 30 . In addition, the semiconductor chip 102 is electrically connected to the substrate 30 through the bonding wire 104 , and is thermally connected and mechanically adhered to the heat sink 74 through the die-bonding material 106 . For example, the bonding wire 104 is connected and electrically connected to the bonding pad 64 and the bonding pad 114 , thereby electrically connecting the semiconductor chip 102 to the terminal 70 . Likewise, the die-bonding material 106 contacts and is located between the cover 68 and the thermal contact surface 112, and is thermally connected and mechanically adhered to the cover 68 and the thermal contact surface 112, thereby the semiconductor chip 102 thermally connected to the base 24 . The bonding pad 64 is provided with a nickel/silver covered metal pad to facilitate a firm combination with the bonding wire 104 , thereby improving signal transmission from the substrate 30 to the semiconductor chip 102 . In addition, the shape and size of the cover 68 is matched to the thermal contact surface 112 , thereby improving heat transfer from the semiconductor chip 102 to the heat sink 74 .

The encapsulation material 108 is a solid compressible protective plastic covering, which can provide environmental protection for the semiconductor chip 102 and the bonding wire 104 against moisture and particles. Wherein, the semiconductor chip 102 and the bonding wire 104 are embedded in the packaging material 108 . Moreover, if the semiconductor chip 102 is an optical chip such as an LED, the encapsulation material 108 may be transparent, wherein the encapsulation material 108 is transparent in FIG. 5B for illustration purposes.

If it is desired to manufacture the above-mentioned semiconductor chip assembly body 100, the semiconductor chip 102 can be arranged on the cover body 68 by using the die-bonding material 106, and then the bonding pad 64 is bonded to the wire bonding pad 114 by wire bonding, and then The encapsulation material 108 is formed.

For example, the die-bonding material 106 is originally a silver-containing epoxy resin paste with high thermal conductivity, and is selectively printed on the cover 68 by screen printing. Then utilize a grabbing head and an automatic pattern recognition system to place the semiconductor chip 102 on the epoxy resin silver paste in a step-and-repeat manner; then heat the epoxy resin silver paste to make it at a relatively low temperature (such as 190 ℃) to complete the solidification. The bonding wire 104 is a gold wire, which is then thermosonically connected to the bonding pad 64 and the bonding pad 114 ; and, finally, the encapsulation material 108 is transfer-molded on the structure.

The semiconductor chip 102 can be electrically connected to the pad 64 through various connection media, thermally connected or mechanically adhered to the heat sink 74 by various thermal adhesives, and packaged with various packaging materials.

So far, the semiconductor chip assembly 100 is a first level single crystal package.

Please refer to FIG. 6A-FIG. 6C, which are respectively a cross-sectional schematic diagram of a semiconductor chip group body in another preferred embodiment of the present invention, a schematic top view of a semiconductor chip group body in another preferred embodiment of the present invention, and another schematic diagram of a semiconductor chip group body in another preferred embodiment of the present invention. A schematic bottom view of the semiconductor chip assembly of the preferred embodiment. As shown in the figure: the semiconductor chip in this embodiment is disposed on the aforementioned base instead of the aforementioned cover. The chip is overlapped by the bumps, and is electrically connected to the terminal so as to be electrically connected to the pad, and is thermally connected to the base so as to be thermally connected to the cover.

For the sake of brevity, all descriptions related to the assembly 100 (shown in FIGS. 5A-5C ) applicable to this embodiment are incorporated here, and the same descriptions will not be repeated. Similarly, the components of the assembly in this embodiment are similar to the components of the assembly 100, all adopting the corresponding reference numerals, but the base number of the encoding is changed from 100 to 200. For example, the semiconductor chip 202 corresponds to the semiconductor chip 102 , the bonding wire 204 corresponds to the bonding wire 104 , and so on.

The semiconductor chip assembly body 200 of the present embodiment comprises a heat conducting plate 82, a semiconductor chip 202, a bonding wire 204, a die-bonding material 206 and a packaging material 208, and the semiconductor chip 202 is inverted here and includes (in When not inverted) a top surface 210 , a bottom surface 212 and a bonding pad 214 , wherein the top surface 210 is an active surface and includes the bonding pad 214 , and the bottom surface 212 is a thermal contact surface.

The semiconductor chip 202 is disposed on the heat sink 74 , electrically connected to the substrate 30 , and thermally connected to the heat sink 74 . In detail, the semiconductor chip 202 is disposed on the base 24 , located within the periphery of the base 24 , overlapped by the bumps 22 but not overlapped by the substrate 30 . In addition, the semiconductor chip 202 is electrically connected to the terminal 70 through the bonding wire 204 , and is thermally connected and mechanically adhered to the heat sink 74 through the die-bonding material 206 . For example, the bonding wire 204 is connected and electrically connected to the bonding pad 214 and the terminal 70 , thereby electrically connecting the semiconductor chip 202 to the bonding pad 64 . Likewise, the die-bonding material 206 is located between the base 24 and the thermal contact surface 212, and is thermally connected and mechanically adhered to the base 24 and the thermal contact surface 212, thereby thermally bonding the semiconductor chip 202. on the cover 68 . Herein, the encapsulation material 208 is transparent in FIG. 6C for illustrative purposes.

If it is desired to manufacture the above-mentioned semiconductor chip assembly body 200, the semiconductor chip 202 can be placed on the base 24 by using the die-bonding material 206, and then the wire bonding pad 214 is bonded to the terminal 70 by wire bonding, and then formed The encapsulation material 208 .

So far, the semiconductor chip assembly 200 is a first level single crystal package.

The above-mentioned semiconductor chip assembly and heat conduction plate are only illustrative examples, and the present invention can be realized through other various embodiments. In addition, the above-mentioned embodiments can be mixed and matched with each other or used with other embodiments according to design and reliability considerations. For example, a heat conduction plate having a plurality of protrusions to cooperate with a plurality of semiconductor chips, some of the wires 72 may include the routing lines 42 and 66, the first and second conductive holes 56 and 58, and the terminal 70, while the other part of the wires 72 does not contain the routing lines 42 and 66 and the first and second conductive holes 56 and 58 , and does not extend through the adhesive layer 26 or the dielectric layer 34 . Likewise, the semiconductor component and the cover can overlap the substrate and the underlying adhesive layer, and the semiconductor component can also be overlapped by the substrate.

The semiconductor component can use the heat sink alone or share the heat sink with other semiconductor components. For example, a single semiconductor component can be disposed on the heat sink, or multiple semiconductor components can be disposed on the heat sink. For example, four small chips arranged in a 2x2 array can be attached to the bumps, and the substrate can include additional wires for electrical connection of the chips. This approach is far more economical than providing a tiny bump for each chip.

The semiconductor chip can be optical or non-optical. For example, the chip can be an LED, a solar cell, a power chip or a controller chip. In addition, various connection media can be used to mechanically, electrically and thermally connect the semiconductor device to the thermally conductive plate, including soldering and using conductive and/or thermally conductive adhesives.

The heat dissipation seat can quickly, effectively and evenly dissipate the heat energy generated by the semiconductor component to the next layer of assembly without passing the heat flow through the adhesive layer, the substrate or other parts of the heat conducting plate. This allows the use of an adhesive layer with lower thermal conductivity, which significantly reduces costs. The heat sink can be made of copper, and includes an integrally formed boss and base, and a cover that is metallurgically bonded and thermally bonded to the boss, thereby improving reliability and reducing cost. The cover can be coplanar with the pad so as to form electrical, thermal and mechanical connection with the semiconductor device. In addition, if it is desired to place the semiconductor component above the heat sink, the cover can be customized according to the semiconductor component, and the base can be customized according to the next layer of assembly, thereby strengthening the self-contained structure. The thermal connection of semiconductor components to the next level of assembly. For example, the boss can be circular on a lateral plane, the cover can be square or rectangular on a lateral plane, and the side shape of the cover is the same or similar to the side shape of the thermal contact of the semiconductor component. . Similarly, if it is desired to place the semiconductor component under the heat sink, the base can also be customized according to the semiconductor component, and the cover body can be customized according to the next layer of assembly.

The heat sink can be electrically connected to or electrically isolated from the semiconductor component and the substrate. For example, a routing line of the third conductive layer can extend through the adhesive layer between the substrate and the cover, so as to electrically connect the semiconductor device to the heat sink. Then, the heat sink can be electrically grounded, so as to electrically ground the semiconductor component.

The post can be deposited on the base or integrally formed with the base. For example, the post can be integrally formed with the base to form a single metal body, or the post and the base can include a single metal body at the interface and other metals at other parts. The post can include a flat top surface or top. For example, the post can be coplanar with the adhesive layer, or the post can be etched after the adhesive layer has cured, thereby forming a cavity in the adhesive layer above the post. The stud can also be selectively etched, thereby forming a cavity in the stud extending below the top surface thereof. In any of the above cases, the semiconductor component can be arranged on the boss and located in the cavity, and the bonding wire can extend to the semiconductor component located in the cavity, and then leave the cavity and extend to the solder pad. In this example, the semiconductor component can be an LED chip, and the cavity can focus the LED light toward the upward direction.

The base can provide mechanical support for the substrate. For example, the pedestal prevents the substrate from warping during metal grinding, chip placement, wire bonding, and molding packaging materials. Additionally, the back of the base may include fins protruding in the downward direction. For example, a drill can be used to cut the bottom surface of the base to form lateral grooves, and these lateral grooves are fins. In this example, the thickness of the base is 500 microns, the depth of the grooves is 300 microns, that is, the height of the fins is 300 microns. The fins increase the surface area of the base, and if the fins are exposed to the air rather than being disposed on a heat sink, improve the thermal conductivity of the base via convection.

After the adhesive layer is cured, before, during or after the formation of the pads and/or terminals, the cover can be formed by a variety of deposition techniques, including electroplating, electroless coating, evaporation and sputtering. layer or multilayer structure. The cover body can be made of the same metal material as the boss. Additionally, the cover can extend across the through hole and reach the substrate, or remain within the circumference of the through hole. Thus, the cover can contact the substrate or keep a distance from the substrate. In any of the above situations, the cover extends laterally from the top of the boss along the side direction.

The adhesive layer can provide a strong mechanical connection between the heat sink and the substrate. For example, the adhesive layer can fill the space between the heat sink and the substrate, the adhesive layer can be located in the space, and the adhesive layer can be a non-hole structure with evenly distributed bonding lines. The adhesive layer can also absorb the mismatch between the heat sink and the substrate due to thermal expansion. In addition, the adhesive layer can be a low cost dielectric and does not need to have high thermal conductivity. Furthermore, the adhesive layer is not easy to delaminate.

The thickness of the adhesive layer can be adjusted so that the adhesive layer substantially fills the gap, and all the adhesive is substantially located within the structure after curing and/or grinding. For example, the ideal film thickness can be determined by trial and error.

The substrate can provide flexible multi-layer signal routing in X and Y directions to provide complex routing patterns. The welding pad and the terminal can adopt various packaging forms according to the needs of the semiconductor component and the next layer assembly. Additionally, the substrate can be a low cost laminate structure and does not need to have high thermal conductivity.

The welding pad and the top surface of the cover can be coplanar, so that the soldering between the semiconductor component and the heat conducting plate can be strengthened by controlling the collapse degree of the solder balls.

The pads and the routing lines above the dielectric layer can be formed by a variety of deposition techniques before or after the substrate is placed on the adhesive layer, including electroplating, electroless coating, evaporation and sputtering to form a single layer or multi-layer structure. For example, the first and second conductive layers can be formed on the substrate before the substrate is placed on the adhesive layer.

The process of surface treatment with the covered contact can be performed before or after the formation of the solder pad and the terminal. For example, the coating layer can be deposited on the third and fourth conductive layers, and then a patterned etch stop layer is used to define the pad and the terminal and etched to pattern the coating layer.

The wires may include additional pads, terminals, routing lines and vias, and passive components, and may be of various configurations. The wire can serve as a signal layer, a power layer or a ground layer, depending on the purpose of its corresponding semiconductor component pad. The wires may also include various conductive metals such as copper, gold, nickel, silver, palladium, tin and alloys thereof. The ideal composition depends both on the nature of the external link medium and on design and reliability considerations. In addition, those skilled in the art should understand that the copper used in the semiconductor chip assembly can be pure copper, but usually copper-based alloys, such as copper-zirconium (99.9% copper), copper-silver- Phosphorus-magnesium (99.7% copper) and copper-tin-iron-phosphorus (99.7% copper) to improve mechanical properties such as tensile strength and ductility.

In general, it is preferable to provide the cover, the solder resist green paint, the covered contacts, and the third and fourth conductive layers, but in some embodiments they can be omitted.

The operating format of the heat conduction plate can be single or multiple heat conduction plates, depending on the manufacturing design. For example, a single heat conducting plate can be fabricated separately. Alternatively, a single metal plate, a single adhesive layer, a single substrate, a single top solder mask green paint and a single bottom solder mask green paint can be used to manufacture multiple heat conducting plates in batches at the same time, and then separated. Similarly, for each heat conduction plate in the same batch, it is also possible to use a single metal plate, a single adhesive layer, a single substrate, a single top solder mask green paint and a single bottom solder mask green paint to manufacture multiple groups at the same time. Heat sinks and wires used in semiconductor components.

For example, a plurality of grooves can be etched on a metal plate to form the base and a plurality of protrusions; then an uncured adhesive layer with openings corresponding to the protrusions is placed on the base, so that Each protrusion extends through a corresponding opening; then a substrate (which has a single first conductive layer, a single dielectric layer, a plurality of through holes corresponding to the protrusions, and a plurality of The lower routing line of the through hole) is arranged on the adhesive layer, so that each protrusion extends through a corresponding opening and enters a corresponding through hole; the adhesive layer enters the gap between the protrusions and the substrate in the through holes; then the adhesive layer is cured, and then the protrusions, the adhesive layer and the first conductive layer are ground to form a top surface ; then forming a plurality of first holes and a plurality of second holes, wherein the first holes penetrate the first conductive layer and the dielectric layer to the routing lines, and the second holes penetrate the base and the Adhesive layer to the routing lines; then the third conductive layer is coated on the protrusions, the adhesive layer and the first conductive layer, the fourth conductive layer is coated on the base, and multiple A first conductive hole is respectively covered and arranged in the first holes, and a plurality of second conductive holes are respectively covered and arranged in the second holes; then etching the first and third conductive layers to form a plurality of respectively Corresponding to the welding pads of the bumps, etching the third conductive layer to form a plurality of covers corresponding to the bumps, and etching the base and the fourth conductive layer to form a plurality of bumps corresponding to the bumps The terminals; then place the first solder resist green paint on the structure, and make the first solder resist green paint pattern, so as to expose the solder pads and the covers, and the second solder resist green The paint is placed on the structure, so that the second solder resist green paint produces a pattern, thereby exposing the bases and the terminals; and then covering the base, the solder pads, the terminals and the covers Finally, cut or split the substrate, the adhesive layer and the solder resist green paint at appropriate positions on the peripheral edges of the heat conduction plates, so that individual heat conduction plates are separated from each other.

The operating format of the semiconductor chip assembly can be a single assembly or multiple assemblies, depending on the manufacturing design. For example, a single assembly can be fabricated separately. Alternatively, multiple assemblies can be batch-manufactured at the same time, and then the heat conduction plates are separated one by one; similarly, multiple semiconductor components can also be electrically connected, thermally connected, and mechanically connected to each batch in mass production. a heat conducting plate.

For example, a plurality of die-bonding materials can be deposited on a plurality of lids respectively, and then a plurality of chips are respectively placed on the die-bonding materials, and then the die-bonding materials are heated simultaneously to harden and form a plurality of die-bonding materials. Die bonding, then wire bonding the chips to corresponding pads, then forming corresponding packaging materials on the chips and wire bonding, and finally separating the heat conducting plates one by one.

The heat conducting plates can be separated from each other through a single step or multiple steps. For example, a plurality of heat conduction plates can be made into a flat plate in batches, and then a plurality of semiconductor components are arranged on the flat plate, and then the plurality of semiconductor chip assemblies formed by the flat plate are separated one by one. Alternatively, a plurality of heat conduction plates can be made into a flat plate in batches, and then the plurality of heat conduction plates formed by the plate are cut into a plurality of heat conduction strips, and then a plurality of semiconductor components are respectively arranged on the heat conduction strips , and finally separate the plurality of semiconductor chip assemblies formed by the heat-conducting strips into individual units. Additionally, mechanical cutting, laser cutting, cleaving, or other suitable techniques may be utilized in dividing the thermally conductive plate.

Therefore, the manufacturing process of the present invention has high applicability, and combines various mature electrical connection, thermal connection and mechanical connection technologies in a unique and progressive manner. In addition, the manufacturing process of the present invention can be implemented without expensive tools. Therefore, this manufacturing process can greatly improve the yield, yield, performance and cost-effectiveness of conventional packaging technologies. Furthermore, the assembly in this case is very suitable for copper chips and lead-free environmental protection requirements.

As used herein, the term "adjacent" means that the components are integrally formed, ie form a single body, or contact each other, ie, are not spaced or separated from each other. For example, the stud abuts the base regardless of whether addition or subtraction is used to form the stud.

The term "overlapping" means overlying and extending within the perimeter of an underlying component. "Overlapping" includes extending inside, outside, or within the perimeter. For example, the semiconductor component overlaps the bump, because an imaginary vertical line can run through the semiconductor component and the bump at the same time, regardless of whether there is another component between the semiconductor component and the bump that is also penetrated by the imaginary vertical line (such as the cover), and regardless of whether there is another imaginary vertical line that only runs through the semiconductor component but not through the stud (that is, is located outside the periphery of the stud). Likewise, the adhesive layer overlaps the base and the terminal and is overlapped by the pad, and the base is overlapped by the bump. Likewise, the post overlaps the base and is located within its periphery. Also, "overlapping" is synonymous with "on top", and "overlapped" is synonymous with "below".

The term "contact" means direct contact. For example, the dielectric layer contacts the first and second conductive layers but does not contact the stud or the base.

The term "covering" means completely covering from above, from below and/or from the sides. For example, the base covers the post from below, but the post does not cover the base from above.

The word "layer" includes a layer with a pattern or without a pattern. For example, when the substrate is placed on the adhesive layer, the first conductive layer can be a blank plate without pattern and the second conductive layer can be a circuit pattern with spaced wires; When seated, the first conductive layer can be a patterned circuit. Additionally, a "layer" may include multiple overlapping layers.

The term "pad" when used in conjunction with the substrate refers to a connection area for connecting and/or joining an external connection medium (such as solder or bonding wire); when the semiconductor device is located above the heat sink, the external connection medium The bonding pad can be electrically connected with the semiconductor component.

The term "terminal" when used in conjunction with this assembly refers to a connection area that can contact and/or engage an external connection medium (such as solder or wire bonding); when the semiconductor device is located above the heat sink, the external connection The medium can electrically connect the terminal to an external device (such as a printed circuit board or a wire connected thereto).

The term "cover" when used in conjunction with the heat sink refers to a contact area for connecting and/or engaging an external connection medium (such as solder or thermally conductive adhesive); when the semiconductor device is positioned above the heat sink, the The external connection medium enables the cover to achieve thermal connection with the semiconductor device.

The terms "opening" and "through hole" mean a through hole. For example, when the protrusion is inserted into the opening of the adhesive layer, it is exposed to the adhesive layer in an upward direction. Likewise, when the protrusion is inserted into the through hole of the substrate, the protrusion is exposed to the substrate along an upward direction.

The term "interposition" refers to relative movement between components. For example, "insert the boss into the through hole" includes: the boss is fixed and moves from the substrate to the base; the substrate is fixed and the boss moves to the substrate; and the boss and the substrate are in close contact with each other. For another example, "insert (or extend) the boss into the through hole" includes: the boss penetrates (into and out of) the through hole; and the boss is inserted but not penetrated (into but not through) out) the via.

The phrase "together" also refers to relative movement between components. For example, "the base and the substrate are in close contact with each other" includes: the base is fixed and moved from the substrate to the base; the substrate is fixed and moved from the base to the substrate; and the base close to the substrate.

The term "disposed on" includes both contact and non-contact with a single or multiple support elements. For example, the semiconductor component is disposed on the heat sink, no matter whether the semiconductor component actually touches the heat sink or is separated from the heat sink by a die-bonding material. Likewise, the semiconductor component is disposed on the heat sink, whether the semiconductor component is only disposed on the heat sink or simultaneously disposed on the heat sink and the substrate.

The phrase "adhesive layer...in the notch" means the adhesive layer located in the notch. For example, "the adhesive layer extends across the dielectric layer in the gap" means that the adhesive layer in the gap extends across the dielectric layer. Similarly, "the adhesive layer is in contact with the notch and between the protrusion and the dielectric layer" means that the adhesive layer in the notch is in contact with and between the protrusion and the notch on the inner wall of the notch. between the dielectric layers on the outer sidewalls.

The term "above" means extending upward and includes adjoining and non-adjacent elements as well as overlapping and non-overlapping elements. For example, the post extends above the base, and at the same time adjoins, overlaps and protrudes from the base. Likewise, the protrusion extends above the dielectric layer, even though the protrusion is not adjacent to or overlapping the dielectric layer.

The term "beneath" means extending downward and encompasses adjoining and non-adjacent elements as well as overlapping and non-overlapping elements. For example, the base extends below the boss, adjoins the boss, is overlapped by the boss, and protrudes from the boss. Likewise, the protrusion extends below the dielectric layer even though the protrusion is not adjacent to or overlapped by the dielectric layer.

The so-called "upward" and "downward" vertical directions do not depend on the orientation of the semiconductor chip assembly body (or the heat conducting plate), and those familiar with the art can easily understand the actual directions. For example, the protrusion extends vertically above the base in the upward direction, and the adhesive layer extends vertically below the pad in the downward direction, which is related to whether the assembly is inverted and/or whether it is arranged on a heat sink irrelevant. Likewise, the base extends "laterally" from the post along a lateral plane, regardless of whether the assembly is inverted, rotated or tilted. Thus, the upward and downward directions are opposite to each other and perpendicular to the side directions, and furthermore, laterally aligned components are coplanar with each other in a lateral plane perpendicular to the upward and downward directions.

The semiconductor chip assembly of the present invention has several advantages. This group has high reliability, low price and is very suitable for mass production. The assembly is especially suitable for high-power semiconductor components such as large semiconductor chips that are prone to high heat and require excellent heat dissipation to operate effectively and reliably.

The embodiments described herein are for illustration purposes, and the components or steps involved in the art are either simplified or omitted to avoid obscuring the characteristics of the present invention. Likewise, components and reference numerals that are repeated or not necessary in the drawings may be omitted for clarity of the drawings.

Variations and modifications to the embodiments described herein will readily occur to those skilled in the art. For example, the aforementioned raw materials, dimensions, shapes, sizes, steps and steps are just examples. Such changes, adjustments and equivalents can be made by the above-mentioned persons without departing from the spirit and scope of the present invention, wherein the scope of the present invention is defined by the claims.

To sum up, the present invention is a semiconductor chip assembly, which can effectively improve the various shortcomings of the existing ones. High-power semiconductor components with high heat and excellent heat dissipation effect can be effectively and reliably operated, which can greatly improve yield, yield, performance and cost-effectiveness, and meet environmental protection requirements, thereby making the production of the present invention more advanced, more practical, and more Meet the needs of users, and indeed meet the requirements for patent application for inventions, and file patent applications according to law.

Claims (25)

1. A semiconductor chip assembly for providing vertical signal routing, characterized in that it comprises: An adhesive layer has at least one opening; A heat sink, comprising at least a boss and a base, wherein the boss adjoins the base and extends above the base along an upward direction, and the base extends along a downward direction opposite to the upward direction under the stud and extending laterally from the stud in a side direction perpendicular to the upward and downward directions; A substrate, disposed on the adhesive layer and extending above the base, at least includes a pad, a routing line, a first conductive hole and a dielectric layer, wherein the pad extends above the dielectric layer , the routing line extends below the dielectric layer and is buried in the adhesive layer, and the first conductive hole extends through the dielectric layer to the routing line, and a via hole extends through the substrate; a second conductive hole extending through the adhesive layer to the routing line; a terminal extending below the adhesive layer; A semiconductor component is located above and overlaps the stud, or is located below the stud and overlaps the stud, the semiconductor component is electrically connected to the pad and the terminal, and is thermally connected to the stud with the base; and The protrusion extends through the opening and enters the through hole to reach above the dielectric layer, the base extends below the adhesive layer and the substrate, and is formed by the first conductive hole, the routing line and the second conductive hole forming a conductive path between the pad and the terminal, wherein the adhesive layer is disposed on the base, and extends above the base into the through hole into a gap between the bump and the substrate, The gap extends across the dielectric layer, and is between the protrusion and the dielectric layer, and between the base and the substrate. 2. The semiconductor chip assembly according to claim 1, wherein the semiconductor component is a semiconductor chip, which extends above the bump, overlaps the bump, and is electrically connected to the pad, so that Electrically connected to the terminal, and the semiconductor chip is thermally connected to the stud, thereby thermally connected to the base. 3. The semiconductor chip assembly according to claim 1 , wherein the semiconductor component is a semiconductor chip, which is disposed on the heat sink by a die-bonding material, and is electrically connected to the soldering pad via a bonding wire, and thermally connected to the protrusion via the crystal-bonding material. 4. The semiconductor chip set according to claim 1, wherein the adhesive layer contacts the protrusion and the dielectric layer in the gap, and contacts the base and the dielectric layer outside the gap. , the routing line, the second conductive hole and the terminal. 5 . The semiconductor chip assembly according to claim 1 , wherein the adhesive layer covers and surrounds the protrusion in the side direction. 6 . 6. The semiconductor chip assembly as claimed in claim 1, wherein the adhesive layer fills up the gap. 7. The semiconductor chip assembly according to claim 1, wherein the adhesive layer fills up a space between the base and the substrate. 8. The semiconductor chip assembly according to claim 1, wherein the adhesive layer overlaps the terminals. 9. The semiconductor chip assembly as claimed in claim 1, wherein the adhesive layer extends to a peripheral edge of the assembly. 10 . The semiconductor chip assembly according to claim 1 , wherein the protrusion is integrally formed with the base. 11 . 11 . The semiconductor chip assembly according to claim 1 , wherein the protrusion and the adhesive layer are on the same plane above the dielectric layer. 12 . The semiconductor chip assembly according to claim 1 , wherein the protrusion is in the shape of a flat-topped cone, and its diameter decreases upward from the base to the flat top of the protrusion. 13 . 13. The semiconductor chip assembly according to claim 1, wherein the base and the terminals are in the same plane below the adhesive layer. 14 . The semiconductor chip assembly according to claim 1 , wherein the base covers the protrusion from below, supports the substrate, and maintains a distance from the peripheral edge of the assembly. 15 . 15. The semiconductor chip assembly as claimed in claim 1, wherein the substrate maintains a distance from the protrusion and the base. 16. The semiconductor chip assembly according to claim 1, wherein the substrate is a laminated structure. 17. The semiconductor chip assembly according to claim 1, wherein the heat sink comprises at least a cover, which is located above a top of the boss, adjoins to the top of the boss and covers from above, and at the same time along the top of the boss. The side direction extends laterally from the top of the boss. 18. The semiconductor chip assembly according to claim 17, wherein the cover is rectangular or square, and the top of the protrusion is circular. 19 . The semiconductor chip assembly according to claim 1 , wherein the heat sink comprises at least one cover, and the cover and the solder pad are on the same plane above the dielectric layer. 20. The semiconductor chip assembly according to claim 1, wherein the heat sink is made of copper. 21. A semiconductor chip assembly for providing vertical signal routing, characterized by comprising: An adhesive layer has at least one opening; A heat dissipation seat at least includes a boss, a base and a cover, wherein the boss is adjacent to the base and integrally formed with the base, and the boss extends above the base along an upward direction, and The base is thermally connected to the cover, the base extends below the post along a downward direction opposite to the upward direction, and extends from the post along a side direction perpendicular to the upward and downward directions. Extending laterally, the cover is located above a top of the boss, adjoins to the top of the boss and covers from above, and extends laterally from the top of the boss along the side direction; A substrate, disposed on the adhesive layer and extending above the base, at least includes a first and a second conductive layer, a first conductive hole and a dielectric layer, wherein the first conductive layer contacts the dielectric layer layer and extends above the dielectric layer, the second conductive layer contacts the dielectric layer and extends below the dielectric layer and is embedded in the adhesive layer, and has a solder pad included in the first conductive layer a selected portion of the second conductive layer, the pad contacts the dielectric layer and extends over the dielectric layer, and has a routing line included in a selected portion of the second conductive layer, the routing line contacting the dielectric layer and extending over the dielectric layer Below the dielectric layer, the first conductive hole contacts and extends through the dielectric layer between the first conductive layer and the routing line, and a through hole extends through the substrate; a second conductive hole, contacting and extending through the adhesive layer to the routing line; a terminal contacting and extending under the adhesive layer; A semiconductor chip is disposed on the cover, overlaps the stud, and is electrically connected to the pad, thereby electrically connected to the terminal, and the semiconductor chip is thermally connected to the cover, thereby thermally connected to the base; and The protrusion extends through the opening and enters the through hole to reach above the dielectric layer, and the base extends below the semiconductor chip, the adhesive layer and the substrate along the downward direction, and covers the semiconductor chip and the substrate from below. The boss supports the substrate, the first conductive hole, the routing line and the second conductive hole form a conductive path between the pad and the terminal, wherein the adhesive layer is arranged on the base, and Extending above the base into the through hole is a gap between the boss and the substrate, extending across the dielectric layer in the gap, and interposed between the boss and the dielectric layer in the gap Between the base and the base plate outside the gap, the adhesive layer covers and surrounds the protrusion along the side direction, and extends to the peripheral edge of the assembly. 22. The semiconductor chip assembly according to claim 21, wherein the semiconductor chip is disposed on the cover with a die-bonding material, is electrically connected to the pad through a bonding wire, and is connected to the bonding pad through the die-bonding material. The material is thermally bonded to the cover. 23. The semiconductor chip assembly according to claim 21, wherein the substrate is kept at a distance from the boss and the base, and the gap and a space between the base and the substrate are filled by the adhesive layer , and make the adhesive layer limited in a space between the heat sink and the substrate. 24. The semiconductor chip set according to claim 21, wherein the top of the protruding post is circular, and the cover on it is rectangular or square, and the protruding post is in the shape of a flat-topped cone with a diameter of From the base to the cover, it decreases upwards. 25. The semiconductor chip assembly according to claim 21, wherein the protrusion, the adhesive layer, the cover, and the solder pad are all on the same plane above the dielectric layer, and the base and the base The terminals are co-located on the same plane under the adhesive layer, and the heat sink is made of copper.

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