CN102118217B - A kind of method for parallel processing of rate-matched and device - Google Patents

Abstract

The invention discloses a parallel processing method and device for code rate matching, and relates to channel coding technology in a mobile communication system. The method of the present invention includes: receiving a systematic bit data stream, a check 1 data stream and a check 2 data stream, performing interleaving processing on N systematic bit data in the systematic bit data stream, and parallelizing the N systematic bit data Buffering in the memory for storing system bit data, interleaving the N corresponding data groups in the check 1 data stream and the check 2 data stream, and buffering the N corresponding data groups in parallel for In the memory for storing the verification data, where N is equal to the parallel degree set in advance; effective data is read from the memory to realize rate matching. The technical scheme of the invention improves the processing capacity of the system and is very beneficial to subsequent processing.

Description

A parallel processing method and device for rate matching

technical field

The invention relates to a channel coding part in a mobile communication system, in particular to a parallel processing method and device for code rate matching.

Background technique

In a mobile communication system, part of the redundant data is generated after the data transmitted in the channel is channel coded. These redundant information are used to provide more decoding information for the decoder and improve the success rate of decoding. However, if all the redundant information is transmission, resulting in a decrease in transmission efficiency. Therefore, at present, a better method is to select the amount of information to be transmitted according to the quality of the channel. For example, when the channel quality is relatively good, only the original information is transmitted; otherwise, more parity bits are transmitted in addition to the original information bits. That is, the data generated by the channel encoder needs to be selectively transmitted, and the rate matching is a function of realizing the selective transmission of encoded data.

Now, the LTE (LongTermEvolution, Long Term Evolution) system adopts a rate matching method completely different from that of R6—circular buffer rate matching. The advantage of this algorithm is that repetition and puncturing can be realized conveniently, that is, the rate matching implementation for any data rate is very simple. Among them, the main manners for implementing rate matching include software implementation and hardware implementation. Since the data traffic in the LTE system is very large, the processing time left for rate matching is very short. If software processing is used, the requirements for the processor are very high, and the cost also increases sharply. According to the steps described in the protocol for hardware processing, the encoded data is interleaved and stored in the three memories, and then cut, especially when processing the data in the verification 1 memory and the verification 2 memory, interleaved reading is required, which is very troublesome , and a large amount of power consumption will be generated during the continuous conversion of addresses. However, the serial implementation method still cannot meet the processing requirements of LTE high throughput.

Therefore, the existing implementation technology has been further improved.

For example, in the prior art, according to the flow direction shown in Figure 1, the system bit, parity 1 and parity 2 are interleaved respectively at first, and stored in 3 buffers, and then according to the starting position and the soft buffer (NCB ) reads data from these three buffers. When the read data is in the system bit buffer, it is read sequentially. When the read data is in the parity buffer, it is interleaved. Check the bit buffer, and judge whether the read data is valid data, if it is not valid data, ignore and continue to read, otherwise output valid data. Since the serial processing method is adopted, this processing method is very time-consuming, and cannot meet the processing requirement of the large throughput of the LTE.

Contents of the invention

The technical problem to be solved by the present invention is to provide a parallel processing method and device for code rate matching, thereby improving the throughput rate of the system.

In order to solve the above problems, the present invention discloses a parallel processing method for code rate matching, including:

Receiving the systematic bit data stream, the check 1 data stream and the check 2 data stream, interleaving the N systematic bit data in the systematic bit data stream, and buffering the N systematic bit data in parallel for storage In the memory of the system bit data, the N corresponding data groups in the verification 1 data stream and the verification 2 data stream are interleaved, and the N corresponding data groups are buffered in parallel in the memory for storing the verification data. In the memory, N is equal to the preset parallelism;

Read valid data from the memory to implement rate matching.

Further, in the above method, the corresponding data groups in the verification 1 data stream and the verification 2 data stream refer to:

The first to penultimate data in the verification 1 data stream and the second to the last data in the verification 2 data stream respectively form a corresponding data group, and the last data in the verification 1 data stream is the same as the verification data. The null values filled in the verification 2 data stream constitute a corresponding data group, and the first data in the verification 2 data stream and the null values filled in the verification 1 data stream constitute a corresponding data group.

Wherein, interleaving the N corresponding data groups in the verification 1 data stream and the verification 2 data stream refers to:

According to the receiving order of each data in the verification 1 data stream, each data in the verification 1 data stream is respectively formed with each data in the verification 2 data stream to form a corresponding data group, and N of all the corresponding data groups formed are corresponding The data groups are interleaved until all corresponding data groups are processed, wherein each corresponding data group is treated as one data to be interleaved.

The process of reading valid data from the memory is as follows:

According to the set address and output data length, read effective system bit data in parallel from the memory for storing system bit data, and read effective verification data in parallel from the memory for storing verification data data.

When the memory for storing system bit data is a single-port memory, the number of memory for storing system bit data is equal to the set degree of parallelism;

When the memory for storing system bit data is a dual-port memory, the number of memory for storing system bit data is half of the set parallelism.

When the memory for storing verification data is a single-port memory, the number of memory for storing verification data is equal to the set degree of parallelism;

When the memory for storing verification data is a dual-port memory, the number of memories for storing verification data is one-half of the set parallelism.

The present invention also discloses a rate matching device, which at least includes a control module, N interleaving address calculation modules and a punching module, wherein N is equal to the preset parallelism:

The control module is configured to control the N interleaving address calculation modules to perform interleaving processing on the N systematic bit data in the received systematic bit data stream, and buffer the interleaved N systematic bit data in parallel for use in memory for storing system bit data;

And it is used to control the N interleaving address calculation modules to perform interleaving processing on N corresponding data groups in the received verification 1 data stream and verification 2 data stream, and cache the N corresponding data groups that have undergone interleaving processing in parallel in memory for storing calibration data;

The interleaving address calculation module is used to perform interleaving processing on the system bit data according to the control of the control module, and perform interleaving processing on the corresponding data groups in the verification 1 data stream and the verification 2 data stream;

The puncturing module is used to read valid data from the memory for storing system bit data and the memory for storing verification data, so as to realize rate matching.

Further, in the above device, the corresponding data groups in the verification 1 data stream and the verification 2 data stream refer to:

The first to penultimate data in the verification 1 data stream and the second to the last data in the verification 2 data stream respectively form a corresponding data group, and the last data in the verification 1 data stream is the same as the verification data. The null values filled in the verification 2 data stream constitute a corresponding data group, and the first data in the verification 2 data stream and the null values filled in the verification 1 data stream constitute a corresponding data group.

Wherein, the control module forms corresponding data groups with each data in the verification 1 data stream and each data in the verification 2 data stream according to the receiving sequence of the data in the verification 1 data stream, and forms all corresponding N corresponding data groups in the data group are input to N interleaving address calculation modules for interleaving processing until all corresponding data groups are processed;

The interleaving address calculation module is configured to perform interleaving processing on each corresponding data group input by the control module as one data.

The process of the punching module reading valid data from the memory for storing system bit data and the memory for storing verification data is as follows:

Reading valid systematic bit data in parallel from the memory for storing systematic bit data, and reading valid checking data in parallel from the memory for storing checking data.

When the memory for storing system bit data is a single-port memory, the number of memory for storing system bit data is equal to the set degree of parallelism;

When the memory for storing system bit data is a dual-port memory, the number of memory for storing system bit data is half of the set parallelism.

When the memory for storing verification data is a single-port memory, the number of memory for storing verification data is equal to the set degree of parallelism;

When the memory for storing verification data is a dual-port memory, the number of memories for storing verification data is one-half of the set parallelism.

Compared with the prior art, the technical solution of the present invention can process data in parallel, which improves the system processing capability, and the operation of uniformly storing check bits 1 and 2 adopted in the technical solution of the present invention realizes bit collection and soft buffer, Very good for follow-up processing.

Description of drawings

Fig. 1 is a functional block diagram of rate matching in the prior art;

Fig. 2 is the structural representation of the device provided in the present invention;

Fig. 3 is a block diagram of an interleaving address calculation module in the device shown in Fig. 2;

Fig. 4 is a flow chart of implementing rate matching by the device shown in Fig. 2 .

detailed description

The main idea of the present invention is that in the existing rate matching technology, the interleaving address generation method of the system bit data stream and the check 1 data stream is the same, as shown in formula 1, and the interleaving address generation formula of the check 2 data stream is as follows Formula 2 shows:

Formula 1)

Formula (2)

Comparing these two interleaving formulas, it can be seen that formula (2) is shifted to the right by one position in the input data matrix than formula (1), therefore, the present invention considers that the input data of verification 2 data flow is shifted to the left by one position (to be corrected) In this way, the interleaving address generation method of the verification 2 data stream is exactly the same as the interleaving address generation method of the system bit data stream and the verification 1 data stream, so that One interleaving address generation device can be shared. Moreover, the interleaving addresses of the verification 1 data and the verification 2 data are exactly the same each time, and the interleaved storage of verification 1 and verification 2 can be realized during the storage process. When reading data, only the verification data needs to be read sequentially That's it.

The technical solutions of the present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

A device for code rate matching processing, as shown in Figure 2, at least including N parallel interleaving address calculation modules, a storage module for storing system bit data, a storage module for storing check data, and punching modules and control modules. Among them, N is equal to the preset parallelism. The functions of each module are introduced below.

The control module is mainly used to control the working status of the interleaving address calculation module, the storage module for storing system bit data, the storage module for storing verification data, and the punching module, wherein the control module converts the received system bit N data in the data stream (in the present embodiment, N data is the system bit data stream 0, 1, 2 and 3 shown in Figure 2) is simultaneously input to parallel N interleaving address calculation modules, and the control parallel The N interleaving address calculation modules simultaneously interleave the input system bit data (that is, control the interleaving address calculation module to generate an address for the input system bit data), and the control module also controls the N system bit data that have been interleaved at the same time according to their respective The address generated by the interleaving address calculation module is stored in parallel in the memory for storing system bit data; and N corresponding data groups in the received parity 1 data stream and parity 2 data stream are simultaneously input to Parallel N interleaving address calculation modules, control the parallel N interleaving address calculation modules to perform interleaving processing on the corresponding input data group at the same time (that is, control the interleaving address calculation module to generate addresses for the input system bit data), and perform interleaving at the same time The processed N corresponding data groups are stored in parallel in the memory for storing verification data, wherein the first to penultimate data in the verification 1 data stream are respectively the same as the second data in the verification 2 data stream Data to the last data form the corresponding data group, the last data in the verification 1 data stream and the null value filled in the verification 2 data stream constitute the corresponding data group, the first data in the verification 2 data stream and the verification 1 The null values filled in the data stream form the corresponding data group, and the control module stores each corresponding data group as a data in the order that the verification 1 data comes first and the verification 2 data follows. The interleaving address calculation module is mainly used to calculate the interleaving address for the data input by the control module, wherein the interleaving address calculation module uses the corresponding data groups in the verification 1 data stream and the verification 2 data stream input by the control module as a data set perform interleaving;

Specifically, the interleaving address calculation module, as shown in Figure 3, can first convert the column number according to the protocol interleaving transformation table according to the row and column information corresponding to each input data, and then compare the result of the column interleaving transformation with the total number of rows of the matrix Multiply, and finally add the result of multiplying the result of the column interleaving transformation with the total number of rows of the matrix and the number of rows where the data is located to obtain the interleaving address.

In this embodiment, according to the degree of parallelism, at least an interleaving address calculation module equal to the degree of parallelism N is required to calculate the interleaving address of each data input in parallel, wherein the degree of parallelism refers to dk(i) in Fig. 1 each time The number of data input to the interleaving address calculation module in parallel.

The storage module used to store system bit data is mainly used to store system bit data according to the control of the control module. When the storage module uses single-port memory, the number of single-port memory used to store system bit data is the same as the set parallelism , when the storage module uses a true dual-port memory, the number of true dual-port memories used to store system bit data is one-half of the set parallelism;

The storage module used to store verification data is mainly used to store system bit data according to the control of the control module. When the storage module uses a single-port memory, the number of single-port memories used to store verification data is the same as the set parallelism , when the storage module adopts true dual-port memory, the number of true dual-port memory is one-half of the set parallelism.

The punching module is mainly used to read data from the memory according to the start parameter, end parameter, and take out parameter configuration, and judge whether the read data is invalid data. If it is, remove the invalid data, and if not, output it. If there is not enough data when reading the end parameter position, then continue to read from the first position of the memory until the required data is fetched;

In other embodiments, the above-mentioned system can also have 2N parallel interleaving address calculation modules. At this time, the N interleaving address calculation modules are dedicated to parallel processing of input N system bit data, and the N interleaving address calculation modules are dedicated to The input N corresponding data sets are processed in parallel.

The specific process of parallel processing of code rate matching implemented by the above-mentioned device is illustrated below with a set parallelism of 4, as shown in Figure 4, including the following steps:

Step 401: The rate matching device receives the systematic bit data stream in parallel, and after verifying the 1 data stream and the verifying 2 data stream, simultaneously performs interleaving processing on the N systematic bit data in the received systematic bit data stream, and converts the received The N corresponding data groups in the verification 1 data stream and the verification 2 data stream are simultaneously interleaved;

In this step, the corresponding data groups in the verification 1 data stream and the verification 2 data stream refer to the first to penultimate data in the verification 1 data stream and the second data in the verification 2 data stream respectively. Data to the last data form the corresponding data group, the last data in the verification 1 data stream and the null value filled in the verification 2 data stream constitute the corresponding data group, the first data in the verification 2 data stream and the verification 1. Null values filled in the data stream form corresponding data groups; wherein, each corresponding data group can be interleaved as one data.

In this embodiment, the received and input check 1 data stream and check 2 data stream can be buffered separately, that is, buffer 1 and buffer 2 are allocated for the check 1 data stream, and temporary storage is allocated for the check 2 data stream The received verification 1 data first enters the buffer 1 and then enters the buffer 2, and the verification 2 data enters the buffer 1, wherein the first data of the received verification 2 is temporarily stored in the temporary register, and then The data in the buffer 1 of the verification 2 data stream and the data in the buffer 2 of the verification 1 data stream form a corresponding data group. When all the data of the verification 2 data stream has been received), start to fill the set number of NULLs for the verification 2 data stream, so that the data in the buffer 1 of the verification 1 data stream (that is, the received verification 1 data The last data in the stream) and the NULL filled in the verification 2 data stream form the corresponding data group. When the last data of the verification 1 data stream and the NULL filled in the verification 2 data stream form the corresponding data group, Start to fill the set number of NULLs for the check 1 data stream. At this time, when the number of NULLs filled in the check 1 data stream reaches the set value (that is, fill the last NULL), it will be temporarily stored in the temporary register The data (that is, the first data in the received verification 2 data stream) and the NULL filled in the verification 1 data stream form a corresponding data group, and the N corresponding data in all corresponding data groups formed Groups perform interleaving processing according to the interleaving formula at the same time until all corresponding data groups are processed. When performing interleaving processing on each corresponding data group, the corresponding data group can be treated as one data for processing.

Step 402: The rate matching device stores N systematic bit data of the interleaved systematic bit data stream in parallel in the memory for storing systematic bit data according to the set parallelism degree N, and stores the interleaved checksum and The N corresponding data groups in the check 2 data stream are stored in parallel in the memory for storing the check bit data, wherein the memory for storing the system bit data is a memory with a data bit width for storing the check bit The memory of the data is a memory with a width of two data bits;

In this embodiment, according to the law of the interleaving function in the protocol, the degree of parallelism is 4: transform the interleaving function in the protocol into the following 4x8 matrix form

0, 16, 8, 24, 4, 20, 12, 28,

2, 18, 10, 26, 6, 22, 14, 30,

1, 17, 9, 25, 5, 21, 13, 29,

3, 19, 11, 27, 7, 23, 15, 31

Since the degree of parallelism is 4, when four data come at the same time, the number of NULLs added in the rate matching is an integer multiple of 4, so it must start from the first row of the interleaving matrix, the second data is in the third row, and the third The data is in the second row, the last data is in the fourth row, and so on, then the data can be stored in four memories, and each memory stores 8 columns of data. Specifically, first write according to the degree of parallelism The pattern is stored, and the continuous column numbers are placed in different memories according to the column interleaving method provided in Table 1 according to the requirement of parallelism, wherein each memory stores a column of continuous column numbers.

Step 403: the rate matching device sequentially reads the system data from the storage for storing the system bit data, sequentially reads the check bit data from the storage for storing the check bit data, and performs clipping.

Of course, the memory for storing system bit data may also be a true dual-port memory. In this case, the number of true dual-port memory is 1/2 of the set parallelism. Moreover, since the interleaving address of each data is different, there will be no address conflict in the true dual-port memory.

In other application scenarios, the set parallelism can be any value from 2 to 32 bits. When the parallelism is 2, the storage pattern determined by the rate matching device is as follows:

0, 16, 8, 24, 4, 20, 12, 28, 2, 18, 10, 26, 6, 22, 14, 30,

1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31

When the degree of parallelism is 3, the storage pattern determined by the rate matching device is as follows:

0, 16, 8, 24, 4, 20, 12, 28,

2, 18, 10, 26, 6, 22, 14, 30,

1, 17, 9, 25, 5, 21, 13, 29, 3, 19, 11, 27, 7, 23, 15, 31

It can be seen from the above embodiments that the technical solution of the present invention uniformly stores the input data according to the required degree of parallelism, thereby increasing the system throughput. At the same time, the technical solution of the present invention realizes interleaved storage when storing the verification 1 and the verification 2, thereby simplifying the storage structure and reducing the complexity of the system.

Of course, the present invention can also have other various embodiments, and those skilled in the art can make various corresponding changes and deformations according to the present invention without departing from the spirit and essence of the present invention. All changes and deformations should belong to the protection scope of the appended claims of the present invention.

Claims (8)

1. A parallel processing method for code rate matching, characterized in that the method comprises: Receiving the systematic bit data stream, the check 1 data stream and the check 2 data stream, performing interleaving processing on N systematic bit data in the systematic bit data stream in parallel, and buffering the N systematic bit data in N parallel In the memory for storing system bit data, the N corresponding data groups in the verification 1 data stream and the verification 2 data stream are interleaved in parallel, and the N corresponding data groups are cached in parallel in N usage In the memory for storing the verification data, wherein, N is equal to the parallelism set in advance; Reading valid data from the memory for storing system bit data and the memory for storing verification data to realize rate matching; The corresponding data groups in the verification 1 data stream and the verification 2 data stream refer to: The first to penultimate data in the verification 1 data stream and the second to the last data in the verification 2 data stream respectively form a corresponding data group, and the last data in the verification 1 data stream is the same as the verification data. The null values filled in the verification 2 data stream constitute the corresponding data group, and the first data in the verification 2 data stream and the null values filled in the verification 1 data stream constitute the corresponding data group; Interleaving the N corresponding data groups in the verification 1 data stream and the verification 2 data stream refers to: According to the receiving order of each data in the verification 1 data stream, each data in the verification 1 data stream is respectively formed with each data in the verification 2 data stream to form a corresponding data group, and N of all the corresponding data groups formed are corresponding The data groups are interleaved until all corresponding data groups are processed, wherein each corresponding data group is treated as one data to be interleaved. 2. The method of claim 1, wherein The process of reading valid data from the memory for storing system bit data and the memory for storing verification data is as follows: According to the set address and output data length, read effective system bit data in parallel from the memory for storing system bit data, and read effective verification data in parallel from the memory for storing verification data data. 3. The method of claim 2, wherein When the memory for storing system bit data is a single-port memory, the number of memory for storing system bit data is equal to the set degree of parallelism; When the memory for storing system bit data is a dual-port memory, the number of memory for storing system bit data is half of the set parallelism. 4. The method of claim 2, wherein, When the memory for storing verification data is a single-port memory, the number of memory for storing verification data is equal to the set degree of parallelism; When the memory for storing verification data is a dual-port memory, the number of memories for storing verification data is one-half of the set parallelism. 5. A rate matching device, characterized in that the device at least includes a control module, N interleaving address calculation modules and a punching module, wherein, N is equal to the preset degree of parallelism: The control module is configured to control the N interleaving address calculation modules to perform interleaving processing on the N systematic bit data in the received systematic bit data stream in parallel, and cache the N systematic bit data that have undergone interleaving processing in parallel in In N memories for storing system bit data; And it is used to control the N interleaving address calculation modules to perform interleaving processing on N corresponding data groups in the received verification 1 data stream and verification 2 data stream in parallel, and parallelize the N corresponding data groups that have undergone interleaving processing Cached in N memories for storing verification data; The interleaving address calculation module is used to perform interleaving processing on the system bit data according to the control of the control module, and perform interleaving processing on the corresponding data groups in the verification 1 data stream and the verification 2 data stream; The punching module is used to read valid data from the memory for storing system bit data and the memory for storing verification data, so as to realize rate matching; The corresponding data groups in the verification 1 data stream and the verification 2 data stream refer to: The first to penultimate data in the verification 1 data stream and the second to the last data in the verification 2 data stream respectively form a corresponding data group, and the last data in the verification 1 data stream is the same as the verification data. The null values filled in the verification 2 data stream constitute the corresponding data group, and the first data in the verification 2 data stream and the null values filled in the verification 1 data stream constitute the corresponding data group; The control module, according to the receiving order of the data in the verification 1 data stream, forms corresponding data groups for each data in the verification 1 data stream and each data in the verification 2 data stream, and forms all corresponding data groups The N corresponding data groups are input to N interleaving address calculation modules for interleaving processing until all corresponding data groups are processed; The interleaving address calculation module is configured to perform interleaving processing on each corresponding data group input by the control module as one data. 6. The apparatus of claim 5, wherein The process of the punching module reading valid data from the memory for storing system bit data and the memory for storing verification data is as follows: Reading valid systematic bit data in parallel from the memory for storing systematic bit data, and reading valid checking data in parallel from the memory for storing checking data. 7. The apparatus of claim 6, wherein When the memory for storing system bit data is a single-port memory, the number of memory for storing system bit data is equal to the set degree of parallelism; When the memory for storing system bit data is a dual-port memory, the number of memory for storing system bit data is half of the set parallelism. 8. The apparatus of claim 6, wherein When the memory for storing verification data is a single-port memory, the number of memory for storing verification data is equal to the set degree of parallelism; When the memory for storing verification data is a dual-port memory, the number of memories for storing verification data is one-half of the set parallelism.