CN102122525B - Readout amplifying circuit for resistive random access memory (RRAM) cell - Google Patents

Abstract

The invention discloses a readout amplifier circuit of a resistive variable memory unit, and aims to provide a novel readout amplifier circuit of a resistive variable memory unit, reduce the influence of interference current on the read operation, reduce the overall DC power consumption, and improve the reference voltage generating circuit the accuracy. The present invention is composed of a comparison readout stage and a reference voltage generation circuit, the comparison readout stage is composed of N readout bits, and the N readout bits correspond to the bit lines of the resistive memory cell array one by one, and the reference voltage generation circuit consists of M Composed of a voltage dividing element and an operational amplifier; each readout bit is composed of a sensitive amplifier, a feedback resistor, and a voltage comparator; each voltage dividing element in the reference voltage generating circuit is a capacitor, and the capacitor is connected in series. The non-inverting input of the op amp is connected to a voltage divider. By adopting the invention, the misreading rate can be reduced, the overall DC power consumption can be reduced, and the precision of the reference voltage output by the reference voltage generating circuit can be improved.

Description

A sense amplifier circuit of a resistive memory cell

technical field

The invention relates to a readout amplifier circuit on the periphery of a resistive variable memory unit array in the field of integrated circuit design, in particular to a readout amplifier circuit which uses a DC gain change to sample resistance value changes and uses a controllable capacitor voltage divider to generate a reference voltage.

Background technique

Non-volatile memory is a kind of memory that can retain the original stored information after power failure, and is widely used in modern electronic systems. There are many types of non-volatile memory, and resistive random access memory (RRAM) is one of them. Due to the characteristics of ultra-high storage density, simple structure, high speed and non-volatility of RRAM, the application prospect is very broad.

The resistive memory cell array is the core of the resistive memory, and is composed of a large number of resistive memory cells according to a certain spatial structure. The interdigitated electrode structure is a typical resistive memory cell array structure, which has a high degree of integration and is compatible with mainstream microelectronics processes. The cross-electrode structure is two layers of parallel nanowires perpendicularly intersecting each other to form a grid. A resistive memory cell is formed at each intersection, and the resistive memory cell represents logic "0" and "1" in a high-resistance state and a low-resistance state, respectively. FIG. 1 is a schematic diagram of the physical structure of a resistive memory cell array with an interdigitated electrode structure. The resistive memory cell is composed of a top electrode, a bottom electrode and a resistive material inserted in the middle, and FIG. 2 is a schematic cross-sectional view thereof. 3 is a schematic diagram of the relationship between voltage and current of a resistive memory cell, wherein the dotted line is the I-V curve of the memory cell in the high resistance state, and the solid line is the I-V curve of the memory cell in the low resistance state. When the voltage at both ends of the resistive memory unit reaches or exceeds the voltage value at point A of the high-resistance transition potential, the resistive memory unit turns into a high-impedance state, and the voltage at both ends of the resistive memory unit reaches or exceeds the voltage value at point B of the low-resistance transition potential , transitions to a low-impedance state. When the voltage at both ends of the resistive memory cell is between the voltage value of point A and the voltage value of point B, the resistance state does not change. Utilizing this characteristic of the resistive memory cell, the resistance state of the resistive memory cell is changed by changing the applied voltage to realize writing of information; when reading data, a read voltage is applied to the two electrodes of the resistive memory cell, Information reading is realized by detecting the resistance state of the resistive memory unit. In order to detect and distinguish the resistance state of the resistive memory unit, it is an effective way to convert the current signal flowing through the resistive memory unit into a voltage signal for read amplification.

Figure 4 is a typical read amplifier structure, WL ₁ is the first word line of the resistive memory array, WL ₂ is the second word line of the resistive memory array, ..., WL _j is the first word line of the resistive memory array j word line, ..., WL _P is the Pth word line of the resistive memory array, BL ₁ is the first bit line of the resistive memory array, BL ₂ is the second bit line of the resistive memory array, ..., BL _i is the i-th bit line of the resistive memory array, ..., BL _N is the Nth bit line of the resistive memory array, N is the number of bit lines of the resistive memory cell array, and P is the number of word lines of the resistive memory array , P and N are both positive integers. The sense amplification structure is composed of two parts: a comparison readout stage and a reference voltage generating circuit. The comparison readout stage is composed of N readout bits, which respectively correspond to N bitlines of the resistive memory cell array, that is, the first readout bit corresponds to the first bitline, and the second readout bit corresponds to the second bitline, so that And so on. Each readout bit is composed of a load resistor and a voltage comparator, and one end of the load resistor of the first readout bit is connected to the first bit line of the resistive memory cell array and the positive input terminal of the sensitive amplifier of the first readout bit , the other end is grounded, the inverting input terminal of the sensitive amplifier in the first readout position is connected to the output terminal V _ref of the reference voltage generation circuit, the output V _out1 of the first readout position is connected to the external output; the second readout position is connected to The connection mode of the load resistor and the sensitive amplifier in the Nth read bit is similar to that of the first read bit, that is, one end of the load resistor of each read bit is connected to the bit line corresponding to the read bit and the sensitive amplifier in the read bit. The positive input terminal of the amplifier is connected, and the other terminal is grounded, the inverting input terminal of the sensitive amplifier of each readout bit is connected to the output terminal V _ref of the reference voltage generating circuit, and the output terminal of each readout bit is connected to the external output. The reference voltage generation circuit is composed of M voltage dividing elements and operational amplifiers, M is a positive integer, each voltage dividing element is a resistor, and the M voltage dividing elements are connected in series, and the junction of each two voltage dividing elements forms A voltage division point, the potential of the voltage division point can be calculated, according to the needs of the circuit, select the appropriate voltage division point (indicated by point A in the figure). The positive input terminal of the operational amplifier is connected to a voltage dividing point such as point A, and the output terminal V _ref of the operational amplifier is connected to its inverting input terminal to form a voltage follower to improve the driving capability. The output terminal V _ref of the reference voltage generation circuit is connected to the inverting input terminal of the sense amplifier of each readout bit in the comparison readout stage to provide a reference voltage.

When this typical sense amplifier circuit reads the resistive memory cell _rm0 , the read voltage is applied to the first word line _WL1 , the first bit line _BL1 is grounded, and the voltage comparator of the first read bit Compare the divided voltage on the load resistance of the first read bit with the output voltage V _ref of the reference voltage generating circuit, when the divided voltage on the load resistance is greater than V _ref , amplify and generate a binary output signal 1, that is, V _out1 is 1 , when the divided voltage on the load resistor is less than V _ref , amplified to generate a binary output signal 0, that is, V _out1 is 0, so as to realize the reading of the resistance state of the resistive memory unit rm ₀ . The readout method of other memory cells is the same. However, for the sense amplifier circuit in Figure 4, there are several deficiencies that will seriously affect the performance of the sense amplifier circuit:

1. The influence of the interference current generated by the interdigitated electrode structure shown in FIG. 1 cannot be eliminated, and the increase of the capacity of the resistive memory cell array is limited. Due to the electrical characteristics of the resistive memory cell itself and the characteristics of the cross electrode structure, it is impossible to eliminate the interference current between the bit lines of the resistive memory cell array when the sense amplifier circuit shown in Figure 4 is used. When the number of word lines and bit lines increases, the interference current will increase accordingly, thus limiting the increase of the capacity of the resistive memory cell array. The specific reason for this is shown in Figure 6. If unit rm ₀ is in a high-impedance state, and the three units rm ₁ , rm ₂ , and rm ₃ are in a low-impedance state, the read voltage is applied to the first word line WL ₁ , and the second One bit line BL ₁ is grounded. When reading the value of rm ₀ unit, the path indicated by the dotted line indicates the current flowing through rm ₀ , the path indicated by the solid line is the sneak path, and the interference current flows through the sneak path. As the capacity of the resistive memory cell array increases, the number of sneak paths increases, and the interference current will gradually become more serious, resulting in the sense amplifier circuit not being able to correctly identify the resistance state of the resistive memory cell.

2. The DC power consumption of the sense amplifier circuit is large. Since the load resistance is used as the element for detecting the resistance state of the resistive memory cell in each readout bit of the comparison readout stage, there is a direct current path from the word line of the resistive memory cell array to the ground, when the resistive memory cell array When the number of bit lines increases, the DC power consumption of the read operation increases accordingly. At the same time, since the reference voltage generation circuit uses resistors as voltage dividing elements, there is a DC path between the input voltage V _input and the ground, resulting in large DC power consumption. The above reasons result in relatively large DC power consumption of the sense amplifier circuit as a whole.

3. The accuracy of the reference voltage generating circuit is affected. The accuracy of the output voltage V _ref of the reference voltage generation circuit has a strong dependence on the matching accuracy of the voltage divider components. In the manufacturing process of integrated circuits, it is not easy to achieve accurate matching of resistors. The resistor is used as a voltage dividing element, thereby reducing the accuracy of the reference voltage generating circuit.

Due to the existence of the above shortcomings, it is necessary to improve the original readout amplifier circuit of the resistive memory unit to reduce the influence of the interference current caused by the cross electrode structure and the electrical characteristics of the resistive memory unit itself, and further reduce the original readout. Amplifies the DC power consumption of the circuit while improving the accuracy of the reference voltage generation circuit.

Contents of the invention

The problem to be solved by the present invention is to provide a new type of readout amplifier circuit for resistive memory cells, which can reduce the influence of the interference current on the read operation caused by the electrical characteristics of the cross-electrode structure resistive memory cell array itself, and reduce the readout amplification. The overall DC power consumption of the circuit is improved, and the accuracy of the reference voltage generation circuit is improved.

Technical scheme of the present invention is:

The sense amplifier circuit of the resistive memory unit of the present invention is also composed of a comparison read stage and a reference voltage generating circuit. The comparison readout stage is composed of N (N is the number of bit lines of the resistive memory cell array) readout bits, which correspond to the bit lines of the resistive memory cell array one by one, that is, the i-th readout bit corresponds to the i-th bit line BL _i , 1≤i≤N,. Each read bit consists of a sense amplifier, a feedback resistor, and a voltage comparator. In the i-th read bit, the positive input terminal of the sensitive amplifier is grounded, the inverting input terminal is connected to the i-th bit line BL _i , and the output terminal V _oi of the sensitive amplifier is connected to the inverting input terminal of the sensitive amplifier through a feedback resistor , the inverting input terminal of the voltage comparator is connected with the output terminal V _oi of the sensitive amplifier, the positive input terminal of the voltage comparator is connected with the output terminal V _ref of the reference voltage generating circuit, and the output terminal V _outi of the voltage comparator is used as the ith The output of the read bit is connected to an external output.

The reference voltage generating circuit is composed of M (M is a positive integer) voltage dividing elements and an operational amplifier, and each voltage dividing element is a capacitor. M voltage-dividing elements are connected in series as follows: the input terminal IN ₁ of the first voltage-dividing element is grounded, the output terminal OUT ₁ of the first voltage-dividing element is connected to the input terminal IN ₂ of the second voltage-dividing element, and the second voltage-dividing element The output terminal OUT ₂ of the element is connected to the input terminal IN ₃ of the third voltage dividing element, and so on, and the output terminal OUT _k of the kth (1≤k≤M-1) voltage dividing element is connected to the k+1th voltage dividing element The input terminal IN _k+1 of the element, and the output terminal of the Mth voltage dividing element are connected to the reference voltage source V _input . The first voltage dividing point is generated at the junction of the output terminal OUT ₁ of the first voltage dividing element and the input terminal IN ₂ of the second voltage dividing element, and so on, the output terminal OUT _k of the kth voltage dividing element and the k+th The input terminal IN _k+1 of a voltage dividing element generates a kth voltage dividing point, that is, a voltage dividing point is generated at the junction of every two voltage dividing elements. These voltage dividing elements divide the voltage V _input of the reference voltage source, and the potential V _k of the kth voltage dividing point satisfies:

$V_k=\left(\frac{k}{m}\right)\·V_{\mathrm{input}}$ formula one

Record the voltage value corresponding to the output terminal _{V oi} of the sensitive amplifier in the read bit when the resistance variable memory unit is in the high resistance state, and read the voltage corresponding to the output terminal V _oi of the sensitive amplifier in the bit when the resistance variable memory unit is in the low resistance state The value is V _L . For a given voltage resolution accuracy T, the voltage resolution accuracy refers to the minimum voltage divided by a voltage dividing element (for example, when V _input is 4V, the voltage resolution accuracy of 1V can be achieved by using 4 voltage dividing elements), there are:

$m=\left(\frac{1}{T}\right)\·V_{\mathrm{input}}$ formula two

In order to make the voltage comparator in each read-out bit can effectively distinguish the voltage value corresponding to the high-impedance state and the low-impedance state of the resistive memory cell output by the sensitive amplifier in the read-out bit, the selected voltage division point The potential V _j should satisfy:

$V_j=\frac{V_h+V_L}{2}$ formula three

From formula 1, formula 2 and formula 3:

$j=\frac{V_h+V_l}{2T}$ formula four

The positive input terminal of the operational amplifier in the reference voltage generation circuit is connected to the selected jth voltage division point, and the output terminal V _ref of the operational amplifier is connected to the inverting input terminal of the operational amplifier to form a voltage follower. The output terminal V _ref serves as the output terminal of the reference voltage generating circuit and is connected to the positive input terminal of the voltage comparator in each readout bit in the comparison readout stage.

The sampling process of resistive memory cells rm ₀ and rm ₁ can be represented by the equivalent circuit in Figure 9, R _Q represents the equivalent resistance on the sneak path, SA ₁ represents the sensitive amplifier of the first readout bit, and SA ₂ represents The sensitive amplifier of the second readout bit, V _i1 represents the potential of the inverting input terminal of the sensitive amplifier SA ₁ , V _i2 represents the potential of the inverting input terminal of the sensitive amplifier SA ₂ , and I ₁ represents the voltage on the feedback resistor of SA ₁ during the read operation Current, I ₂ represents the current on the feedback resistor of SA ₂ during the read operation, I ₃ represents the current on the equivalent resistance R _Q of the sneak path during the read operation, and I ₄ represents the current flowing through the resistive memory unit rm ₀ during the read operation , I ₅ represents the current flowing through the resistive memory cell rm ₁ during the read operation.

In each readout bit, the feedback structure composed of the sensitive amplifier and the feedback resistor realizes the sampling of the resistance state of the resistive memory unit, and the voltage comparator in each readout bit compares the sampled signal with the reference voltage and then amplifies it. , forming a binary digital signal output.

The following technical effects can be achieved by adopting the present invention:

1. Use the sensitive amplifier to sample the resistance state of the resistive memory unit, and use the zero-current characteristic of the input terminal of the sensitive amplifier to reduce the influence of the interference current between the bit lines, thereby achieving a lower misread rate.

2. The characteristic of zero input current of the sensitive amplifier is utilized in the comparison readout stage, and the voltage dividing element in the reference voltage generating circuit adopts a capacitor, which reduces the overall DC power consumption of the circuit.

3. Because in the manufacturing process of integrated circuits, capacitors are easier to achieve precise matching than resistors, and the use of capacitors in the voltage dividing element improves the accuracy of the reference voltage output by the reference voltage generating circuit.

Description of drawings

Fig. 1 is the physical structure of a typical cross-electrode structure resistive memory cell array described in the background technology;

Fig. 2 is a schematic cross-sectional view of the cross-electrode structure resistive memory cell shown in Fig. 1;

Fig. 3 is a schematic diagram of the I-V characteristics of the resistive memory cell in the cross-electrode structure resistive memory cell array shown in Fig. 1;

FIG. 4 is a structural diagram of a readout amplifier circuit of a typical cross-electrode structure resistive memory cell described in the background art;

Fig. 5 is a structural diagram of the reference voltage generation circuit in Fig. 4;

Fig. 6 is a schematic diagram of the interference current in the readout amplifier circuit structure of the interdigitated electrode structure resistive memory cell in Fig. 4;

Fig. 7 is a structure diagram of a read amplifier circuit of a resistive memory cell of the present invention;

Fig. 8 is a structural diagram of the reference voltage generation circuit in Fig. 7;

Fig. 9 is an equivalent circuit diagram of the signal sampling process of the sensitive amplifier in the comparative readout stage of the present invention.

Detailed ways

The structure and working process of the sense amplifier circuit of the resistive memory cell of the present invention will be described in detail below in conjunction with the accompanying drawings.

Fig. 7 is a structure diagram of the sense amplifier circuit of the resistive memory cell of the present invention, and the present invention is composed of a comparison readout stage and a reference voltage generating circuit. The comparison readout stage is composed of N readout bits, which correspond to the bit lines of the resistive memory cell array one by one, that is, the first readout bit corresponds to the first bitline _BL1 , and the second readout bit corresponds to the second bitline BL ₂ , and so on, the Nth read bit corresponds to the Nth bit line BL _N . Each read bit consists of a sense amplifier, a feedback resistor, and a voltage comparator. In the i-th read bit, the positive input terminal of the sensitive amplifier is grounded, the inverting input terminal is connected to the i-th bit line BL _i , and the output terminal (V _oi ) of the sensitive amplifier is connected to the inverting terminal of the sensitive amplifier through a feedback resistor The input terminal, the inverting input terminal of the voltage comparator is connected with the output terminal of the sensitive amplifier, the positive input terminal of the voltage comparator is connected with the output terminal V _ref of the reference voltage generation circuit, and the output terminal V _outi of the voltage comparator is used as the first The output of the read bit is connected to an external output.

The reference voltage generating circuit in FIG. 8 is composed of M (M is a positive integer) voltage dividing elements and an operational amplifier, and each voltage dividing element is composed of a capacitor. M voltage-dividing elements are connected in series as follows: the input terminal IN ₁ of the first voltage-dividing element is grounded, the output terminal OUT ₁ of the first voltage-dividing element is connected to the input terminal IN ₂ of the second voltage-dividing element, and the second voltage-dividing element The output terminal OUT ₂ of the element is connected to the input terminal IN ₃ of the third voltage dividing element, and so on, the output terminal OUT _k of the kth (1≤k≤M) voltage dividing element is connected to the k+1th voltage dividing element The input terminal IN _k+1 , the output terminal of the Mth voltage dividing element is connected to the reference voltage source V _input . The first voltage dividing point is generated at the junction of the output terminal OUT ₁ of the first voltage dividing element and the input terminal IN ₂ of the second voltage dividing element, and so on, the output of the kth (1≤k≤M) voltage dividing element The terminal OUT _k and the input terminal IN _k+1 of the k+1th voltage dividing element generate a kth voltage dividing point, that is, a voltage dividing point is generated at the junction of every two voltage dividing elements. The potential of the jth voltage division point satisfies:

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; h</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; L</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; ,</span>$

The number M of voltage dividing elements satisfies:

$\mathrm{<span\; class="notranslate">\; m</span>}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{\mathrm{<span\; class="notranslate">\; T</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; input</span>}}$

The positive input terminal of the operational amplifier in the reference voltage generation circuit is connected to the selected voltage dividing point, and the output terminal V _ref of the operational amplifier is connected to the inverting input terminal of the operational amplifier to form a voltage follower. The output terminal of the operational amplifier V _ref is used as the output terminal of the reference voltage generation circuit and is connected to the positive input terminal of the voltage comparator in each readout bit in the comparison readout stage.

When performing a read operation, a read voltage is applied to a corresponding word line, and the data of the resistive memory cells on a row of word lines are read at a time. Since the composition of each read-out bit is exactly the same, record the resistance value of the feedback resistor in each read-out bit as R _f , when the resistive memory cell on the word line is read, the sensitive The DC gain of the amplifier is determined by the ratio of the feedback resistor and the resistance of the resistive memory unit. Take the reading of the resistive memory cell on the first word line WL ₁ as an example for illustration: the read voltage V _r is applied on the first word line WL ₁ , and the first bit line BL ₁ is in phase with the inverting input terminal of the sensitive amplifier. Connect, record the resistance value of unit rm ₀ as R _m0 , when the unit rm ₀ is read, it can be obtained from the closed-loop characteristics of the inverting amplifier, and the DC gain of the sensitive amplifier in the corresponding first readout bit is determined by the feedback resistance and resistance The ratio R _f /R _m0 of the variable memory cell resistance is determined, and the relationship between the output and input voltage is:

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V\; o"\; filenames="HDA0000055368550000051.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="1"\; label="V\; o"\; filenames="HDA0000055368550000051.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; -</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; \&CenterDot;</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}$

When in different resistance states, the resistive memory unit rm ₀ has different resistance values, which causes the output voltage V _o1 to vary with the resistance of the sampling unit, and convert the resistance change of the resistive memory unit into the output of the sensitive amplifier The change of the voltage is used to sample the resistance value of the resistive memory unit. The output of V _o1 is connected to the inverting input terminal of the voltage comparator in the first sense bit, and the voltage comparator generates an output signal by comparing the reference voltage with the output signal of the sense amplifier.

In each readout bit, the sensitive amplifier and the feedback resistor realize the sampling function of the readout bit for the resistance value of the resistive memory unit. The following is an analysis of the working process of the sense amplifier circuit, taking the sampling process of the resistive memory cells rm ₀ and rm ₁ on the first word line WL ₁ as an example, because R _Q can be regarded as any two memory cells The equivalent resistance between the bit lines, and because the principle of the read operation is the same, this analysis is also applicable to any two resistive memory cells on the same word line. The equivalent sampling circuit for rm ₀ and rm ₁ is shown in Figure 9: one end of rm ₀ and rm ₁ is connected to the word line WL ₁ , and the other end of rm ₀ is connected to the first readout bit through the first bit line. The inverting input terminal of the sensitive amplifier SA ₁ is connected, the output terminal V _o1 of SA ₁ is connected with its inverting input terminal through the feedback resistor, and the non-inverting input terminal of SA ₁ is grounded; the other end of rm ₁ is connected with the second bit line The inverting input terminal of the sensitive amplifier SA ₁ in the second readout position is connected, the output terminal V _o2 of SA ₁ is connected with its inverting input terminal through the feedback resistor, the non-inverting input terminal of SA ₁ is grounded, and all sneak paths The resistance of _RQ is equivalently represented. Sensitive amplifiers SA ₁ and rm ₀ of the first readout, and feedback resistors form an inverting amplifier; sensitive amplifiers SA ₂ and rm ₁ of the second readout, and feedback resistors form another inverting amplifier. Note that the resistance value of rm ₀ is R _m0 , the resistance value of rm ₁ is R _m1 , and the resistance value of the feedback resistor in each readout bit is equal to the constant R _f . The following equation follows from Kirchhoff's laws:

$\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>$

$\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; r</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R\; m"\; filenames="HDA0000055368550000051.png"\; state="\{\{state\}\}">R</figure-callout></span><figure-callout\; id="1"\; label="R\; m"\; filenames="HDA0000055368550000051.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; 0</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 2</span>}<span\; class="notranslate">\; )</span>$

$\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; R</span>}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 3</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 3</span>}<span\; class="notranslate">\; )</span>$

$\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}}{<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 4</span>}<span\; class="notranslate">\; )</span>$

$\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}}<span\; class="notranslate">\; =</span>{\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 5</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="V\; o"\; filenames="HDA0000055368550000051.png"\; state="\{\{state\}\}">V</figure-callout></span><figure-callout\; id="1"\; label="V\; o"\; filenames="HDA0000055368550000051.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; a</span>}{<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 6</span>}<span\; class="notranslate">\; )</span>$

${\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\mathrm{<span\; class="notranslate">\; a</span>}{<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 7</span>}<span\; class="notranslate">\; )</span>$

Among them, a represents the open-loop gain of the sensitive amplifier in the signal sampling amplification stage, the read voltage of V _r is applied on the word line, R represents the resistance value of the equivalent resistance R _Q of the sneak path between the two bit lines, and _I3 represents the potential Path interference current. Arranging from the above equations, we can get

$\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R\; m"\; filenames="HDA0000055368550000051.png"\; state="\{\{state\}\}">R</figure-callout></span><figure-callout\; id="1"\; label="R\; m"\; filenames="HDA0000055368550000051.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; R</span>}{<span\; class="notranslate">\; \&Center\; Dot;</span>\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; f</span>}}<span\; class="notranslate">\; \&Center\; Dot;</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="1"\; label="R\; m"\; filenames="HDA0000055368550000051.png"\; state="\{\{state\}\}">R</figure-callout></span><figure-callout\; id="1"\; label="R\; m"\; filenames="HDA0000055368550000051.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; R</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>\mathrm{<span\; class="notranslate">\; R</span>}{<span\; class="notranslate">\; \&CenterDot;</span>\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 8</span>}<span\; class="notranslate">\; )</span>$

It can be obtained from equation (8) that when the open-loop gain a of the sensitive amplifier tends to infinity (ideal situation), the influence of the interference current between the bit lines can be ignored, and the output voltage ratio is only related to the high-resistance state resistance of the resistive memory cell The value is related to the ratio of the resistance value of the low resistance state, that is:

$\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; o</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}}{{\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}\mathrm{<span\; class="notranslate">\; 0</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 9</span>}<span\; class="notranslate">\; )</span>$

From the formula (9), the ratio of the output voltage depends on the ratio of the resistance value of the high-resistance state and the resistance value of the low-resistance state of the resistive memory cell, and has nothing to do with the equivalent resistance R _Q on the sneak path, thus indicating that the readout The amplifying circuit can reduce the influence of the interference current on the sneak path, and effectively sample the resistance state of the resistive memory unit.

The voltage dividing element in the reference voltage generation circuit uses capacitors to divide the voltage. In the process of integrated circuits, capacitors are easier to achieve precise matching than resistors. When the temperature changes, the capacitance of the capacitors changes, but the ratio between them The relationship can still be kept constant, so the generated reference voltage changes little with temperature, and because the capacitor has an inhibitory effect on the DC signal, the DC power consumption of the reference voltage generating circuit can be reduced to zero theoretically. The input reference voltage V _input of the reference voltage generation circuit can be generated by a general reference voltage generation circuit.

The reference voltage V _ref output by the reference voltage generation circuit is connected to the voltage comparator in each readout position, and the voltage comparator of each readout position realizes the sampling output of the reference voltage V _ref and the sense amplifier of the readout position The voltage is compared and amplified, so that the low-swing sampling voltage of the resistive memory unit is amplified to a voltage that can be recognized by the digital circuit, and then the readout result is output to the external circuit.

Claims (1)

1. amplifying circuit is read in a resistance-change memory unit, and it is formed by relatively reading level and generating circuit from reference voltage, relatively reads level and is made up of the individual position of reading of N, and the individual position of reading of N is corresponding one by one with resistance-change memory cell array bit line, and namely i reads the corresponding i bit line BL in position _i, 1≤i≤N, N are the number of resistance-change memory cell array bit line; Generating circuit from reference voltage is made up of M sectional pressure element and an operational amplifier, and M is positive integer; It is characterized in that:

Described each of relatively reading in the level read the position and is made up of a sense amplifier, a feedback resistance, a voltage comparator; Read in the position positive input ground connection of sense amplifier, inverting input and i bit line BL at i _iLink to each other the output terminal V of sense amplifier _OiBe connected to the inverting input of this sense amplifier, the output terminal V of the inverting input of voltage comparator and sense amplifier by feedback resistance _OiLink to each other the output terminal V of the positive input of voltage comparator and generating circuit from reference voltage _RefLink to each other the output terminal V of voltage comparator _OutiThe output terminal of reading the position as i is connected to outside output;

Each sectional pressure element in the described generating circuit from reference voltage is electric capacity, and M sectional pressure element contacted in the following manner: the input end IN of first sectional pressure element ₁Ground connection, the output terminal OUT of k sectional pressure element _kBe connected to the input end IN of k+1 sectional pressure element _K+1, the output terminal of M sectional pressure element and reference voltage source V _InputLink to each other, 1≤k≤M-1 produces a dividing point at the junction surface of per two sectional pressure elements, namely at the output terminal OUT of k sectional pressure element _kInput end IN with the k+1 sectional pressure element _K+1Produce the k dividing point;

The positive input of the operational amplifier in the described generating circuit from reference voltage links to each other with the j dividing point, the output terminal V of operational amplifier _RefBe connected to the inverting input of this operational amplifier, constitute a voltage follower, the output terminal V of operational amplifier _RefRead with relatively reading in the level each that the positive input of voltage comparator links to each other in the position as the output terminal of reference voltage generation circuit, dividing point j satisfies in the generating circuit from reference voltage

$j=\frac{V_H+V_L}{2T}$

V _HRead position sense amplifier output terminal V when being arranged in high-impedance state for the resistance-change memory unit _OiCorresponding voltage value, V _LRead position sense amplifier output terminal V when being arranged in low resistance state for the resistance-change memory unit _OiCorresponding voltage value, T is the voltage resolving accuracy, the voltage resolving accuracy refers to the minimum voltage that a sectional pressure element divides;

The number M of sectional pressure element satisfies in the described generating circuit from reference voltage

$M=\left(\frac{1}{T}\right)\&CenterDot;V_{\mathrm{input}}$

V _InputBe the voltage of reference voltage source, T is the voltage resolving accuracy, and the voltage resolving accuracy refers to the minimum voltage that a sectional pressure element divides.

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