CN102136491B - Electrostatic Discharge Protection Components for Gate Insulated Double Junction Transistors - Google Patents

Abstract

The invention provides a gate-insulated double-junction transistor electrostatic discharge protection element, which comprises a semiconductor substrate; a high-voltage N-type well in the semiconductor substrate; a patterned isolation region arranged on the high-voltage N-type well to define a first active region and a second active region; an N-type double diffusion region arranged in the first active region of the high-voltage N-type well; a P-type densely doped drain region arranged in the N-type double diffusion region; a P-type body doping region in the second active region of the high-voltage N-type well, wherein the N-type double diffusion region and the P-type body doping region are separated by a specific distance to expose the high-voltage N-type well; a pair of adjacent N-type and P-type densely doped source regions arranged in the P-type body doping region; and a gate structure on the high-voltage N-type well, one end of which is connected to the N-type densely doped source region and the other end of which extends to the patterned isolation region.

Description

Electrostatic Discharge Protection Components for Gate Insulated Double Junction Transistors

This application is a divisional application, the original application date is November 3, 2008, the application number is 200810174775.5, and the invention name is: gate insulating double junction transistor electrostatic discharge protection element.

technical field

The present invention relates to an electrostatic discharge protection device, in particular to an electrostatic discharge protection element for a gate insulating double-junction transistor (IGBT).

Background technique

Traditional high-voltage electrostatic discharge (ESD) protection components include laterally diffused metal oxide semi-power transistors (LDMOS Power Transistor), metal oxide semi-transistors (MOSFET), silicon-controlled rectifiers (SCR), bicarrier transistors ( BJT), diode (Diode) and field oxide transistor (Field Oxide Device, FOD). In the protection of high-voltage electrostatic discharge, due to its high trigger voltage (trigger voltage) and low holding voltage (holding voltage), either the internal circuit will be damaged first or the latch-up effect (latch-up) will occur, so it is necessary to add Add an additional drive circuit or adjust the layout parameters to reduce the trigger voltage and make the holding voltage exceed the operation voltage of the device, so that it can be used as a high-voltage electrostatic discharge protection device.

In traditional ultra-HV devices, silicon-on-insulator (SOI) substrates and related processes are often used to isolate individual components to reduce parasitic effects between components due to high-voltage operation. However, the use of a silicon-on-insulator (SOI) substrate and related processes will adversely affect the heat dissipation of the ESD device, so the industry urgently needs to effectively deal with the problem of heat dissipation of the ESD device. In particular, in the process of ultra-high voltage components, the concentration of wells is low, so that the relative impedance is also high, which is not conducive to a more uniform turn-on of ESD components.

Contents of the invention

In view of this, in order to overcome the shortcomings of the above-mentioned background technology, the gate insulated double-junction transistor (IGBT) element is used as an electrostatic discharge protection element, and the layout of the drain region of the IGBT element is improved so that it can be started more uniformly , to improve the protection performance of ESD.

Another embodiment of the present invention provides an electrostatic discharge protection device for an insulated gate double junction transistor (IGBT), comprising: a semiconductor substrate; a high voltage N-type well in the semiconductor substrate; a patterned isolation region disposed in the semiconductor substrate On the high-voltage N-type well, a first active region and a second active region are defined; an N-type double diffusion region is set in the first active region of the high-voltage N-type well; a P-type heavily doped The drain region is set in the N-type double diffusion region; a P-type body doped region is in the second active region of the high voltage N-type well, wherein the N-type double diffusion region and the P-type The body doped regions are separated by a specific distance, exposing the high-voltage N-type well; a pair of adjacent N-type and P-type heavily doped source regions are arranged in the P-type body doped region; and A gate structure is on the high voltage N-type well, one end of which is in contact with the N-type heavily doped source region, and the other end extends to the patterned isolation region.

Yet another embodiment of the present invention provides an electrostatic discharge protection device for an insulated gate double-junction transistor (IGBT), comprising: a semiconductor substrate; a high-voltage N-type well in the semiconductor substrate; a patterned isolation region disposed in the semiconductor substrate On the high-voltage N-type well, a first active region and a second active region are defined; a P-type double diffusion region is set in the first active region of the high-voltage N-type well; a P-type heavily doped The drain region is set in the P-type double diffusion region; a P-type body doped region is in the second active region of the high voltage N-type well, wherein the P-type double diffusion region and the P-type The body doped regions are separated by a specific distance, exposing the high-voltage N-type well; a pair of adjacent N-type and P-type heavily doped source regions are arranged in the P-type body doped region; and A gate structure is on the high voltage N-type well, one end of which is in contact with the N-type heavily doped source region, and the other end extends to the patterned isolation region.

Yet another embodiment of the present invention provides an electrostatic discharge protection device for an insulated gate double junction transistor (IGBT), comprising: a semiconductor substrate; a high voltage P-type well in the semiconductor substrate; a high voltage N-type well in the semiconductor substrate In the substrate; a patterned isolation region is disposed on the semiconductor substrate, defining a first active region in the high-voltage N-type well, a second active region and a third active region in the high-voltage P-type well; A P-type heavily doped drain region is disposed in the first active region; an N-type heavily doped source region is disposed in the second active region, and a P-type heavily doped source region is disposed in the second active region In the third active region; and a gate structure on the high voltage P-type well, one end of which is connected to the N-type heavily doped source region, and the other end extends to the patterned isolation region.

Yet another embodiment of the present invention provides an electrostatic discharge protection device for an insulated gate double-junction transistor (IGBT), comprising: a semiconductor substrate; a patterned isolation region disposed on the semiconductor substrate, defining a first active region and a The second active region; a gate structure is disposed on the first active region of the semiconductor substrate; an N-type double diffusion region is located on one side of the gate structure, and is disposed in the first active region of the semiconductor substrate ; An N-type well is arranged in the N-type double diffusion region, and its bottom extends to the semiconductor substrate; a P-type heavily doped drain region is arranged in the N-type well; an N-type heavily doped The impurity source region is disposed in the semiconductor substrate on the other side of the gate structure; and a P-type dense diffusion region is disposed in the second active region of the semiconductor substrate.

Description of drawings

1A is a schematic cross-sectional view showing an electrostatic discharge protection device for an insulated gate double-junction transistor (IGBT) according to an embodiment of the present invention;

Figure 1B is a planar layout showing the first active region of the IGBT-ESD element of Figure 1A;

2A is a schematic cross-sectional view showing an IGBT-ESD device according to another embodiment of the present invention;

2B and 2C respectively show the planar layouts of different embodiments of the first active region of the IGBT-ESD element of FIG. 2A;

3A is a schematic cross-sectional view showing an IGBT-ESD device according to yet another embodiment of the present invention;

3B is a schematic cross-sectional view showing an IGBT-ESD device according to yet another embodiment of the present invention;

4A is a schematic cross-sectional view showing an IGBT-ESD device according to yet another embodiment of the present invention;

4B is a schematic cross-sectional view showing an IGBT-ESD device according to yet another embodiment of the present invention; and

FIG. 5 is a schematic cross-sectional view showing an IGBT-ESD device according to yet another embodiment of the present invention.

Figure number:

100a, 100b, 300a, 300b, 400a, 400b, 500～IGBT-ESD components;

101, 401～P-type silicon substrate;

102～buried oxide layer;

402～N-type buried layer;

103, 403～P-type epitaxial layer;

105～isolated area;

110, 310, 410, 510～semiconductor substrate;

115, 315, 415b, 415d, 515～high voltage N-type well;

415a, 415c, 415e～high voltage P-type well;

316a, 516～N-type double diffusion region;

316b～P-type double diffusion region;

416～an extra P-type heavily doped region;

117, 217a, 217b, 317, 417, 517～P-type densely doped drain region;

120, 320～P-type body doping region;

122, 322, 422, 522～P-type dense diffusion zone;

124, 324, 424, 524～N-type heavily doped source regions;

524'～N-type lightly doped (NLDD) region;

426～an additional P-type heavily doped region;

130a-130c, 330a-330c, 430a-430f, 530a-530c - patterned isolation regions;

135a, 135b ~ source electrodes;

140, 340, 440, 540～gate structure;

145a, 145b ~ drain electrodes;

OD1 ~ the first active zone;

OD2 ~ the second active zone.

Detailed ways

In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and understandable, the preferred embodiments are specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Hereinafter, each embodiment is described in detail and examples accompanied by drawings are used as a reference basis of the present invention. In the drawings or descriptions in the specification, the same figure numbers are used for similar or identical parts. And in the drawings, the shape or thickness of the embodiments may be enlarged, and marked for simplicity or convenience. Furthermore, the parts of the components in the drawings will be described separately. In addition, the specific embodiments are only used to disclose the specific methods used in the present invention, and are not intended to limit the present invention.

FIG. 1A is a schematic cross-sectional view showing an electrostatic discharge protection device for an insulated gate double-junction transistor (IGBT) according to an embodiment of the present invention. In FIG. 1A, a gate insulated double junction transistor (IGBT) electrostatic discharge protection (ESD) device 100a includes a semiconductor substrate 110 and a patterned isolation region 130a, 130b, 130c disposed on the semiconductor substrate 110, defined A first active area OD1 and a second active area OD2. According to an embodiment of the present invention, the semiconductor substrate 110 is a silicon-on-insulator (SOI) substrate, such as a P-type silicon substrate 101, on which a buried oxide layer 102 and a P-type epitaxial layer 103 are formed. on the buried oxide layer 102 . An isolation region 105 isolates the IGBT-ESD device 100 a from other devices on the substrate 110 .

A high-voltage N-type well 115 is formed in the first active region OD1 of the semiconductor substrate, and a P-type body doped region 120 is formed in the second active region OD2 of the semiconductor substrate, wherein the high-voltage N-type well 115 and the P-type body doped region 120 are separated by a specific distance, exposing the semiconductor substrate. A diffusion region 113 extends from the high voltage N-type well 115 toward the P-type body doped region 120 . A P-type heavily doped drain region 117 is disposed in the high voltage N-type well 115 , and the drain electrodes 145 a, 145 b are in electrical contact with the P-type heavily doped drain region 117 . A pair of adjacent N-type heavily doped source regions 124 and a P-type densely diffused region 122 are arranged in the P-type body doped region 120, and the source electrodes 135a, 135b are respectively connected to the N-type densely The doped source region 124 is in electrical contact with the P-type dense diffusion region 122 . A gate structure 140 is on the semiconductor substrate, one end thereof is in contact with the N-type heavily doped source region 124 , and the other end extends to the patterned isolation region 130b.

According to an embodiment of the present invention, the area of the P-type heavily doped drain region 117 may be larger than the first active region OD1, but smaller than the area of the high voltage N-type well 115, and its planar layout is shown in FIG. 1B.

FIG. 2A is a schematic cross-sectional view showing an IGBT-ESD device according to another embodiment of the present invention. In FIG. 2A , the IGBT-ESD device 100 b is substantially the same as the IGBT-ESD device 100 a in FIG. 1A , and for the sake of brevity, similar descriptions are omitted here. The difference is that the area of the P-type heavily doped drain region 217a is smaller than the area of the high-voltage N-type well 115, and its planar layout is shown in FIG. 2B. In the high-voltage N-type well 115, there is a hetero-doped interface between the high-voltage N-type well 115 and the P-type heavily doped drain region 217a, which can disperse and reduce the ESD voltage by about 0.7V. According to another embodiment of the present invention, the P-type heavily doped drain region 217b is a plurality of isolated island regions, which are disposed in the high-voltage N-type well 115 , and its planar layout is shown in FIG. 2C . Since there is a hetero-doped interface between each island region 217b and the high-voltage N-type well 115, the ESD voltage can be dispersed and reduced, so that the IGBT-ESD device can be turned on more uniformly (uniform turn-on).

FIG. 3A is a schematic cross-sectional view showing an IGBT-ESD device according to yet another embodiment of the present invention. In FIG. 3A , an IGBT-ESD device 300 a includes a semiconductor substrate 310 , such as a P-type silicon substrate, and a high voltage N-type well 315 disposed in the semiconductor substrate 310 . A patterned isolation region 330a, 330b, 330c is disposed on the high voltage N-type well 315, defining a first active region and a second active region. An N-type double diffused region 316a is disposed in the first active region of the high voltage N-type well 315, and a P-type heavily doped drain region 317 is disposed in the N-type double diffused region 316a. A P-type body doped region 320 is disposed in the second active region of the high-voltage N-type well 315, wherein the N-type double diffused region 316a and the P-type body doped region 320 are separated by a specific distance, exposing the high voltage N-type well. A pair of adjacent N-type heavily doped source regions 324 and a P-type densely doped diffusion region 322 are disposed in the P-type body doped region 320 . A gate structure 340 is on the high voltage N-type well 315, one end of which is in contact with the N-type heavily doped source region 324, and the other end extends to the patterned isolation region 330b.

FIG. 3B is a schematic cross-sectional view showing an IGBT-ESD device according to yet another embodiment of the present invention. In FIG. 3B , an IGBT-ESD device 300 b is substantially the same as the IGBT-ESD device 300 a in FIG. 3A , and for the sake of brevity, the same description is omitted here. The difference is that the IGBT-ESD element 300b has a P-type double diffusion region 316b disposed in the first active region of the high-voltage N-type well 315, and a P-type heavily doped drain region 317 is disposed in the P- type double diffused region 316b. Since both the P-type heavily doped drain region 317 and the P-type double diffusion region 316b are P-type doped, the performance of the ESD device can be improved.

FIG. 4A is a schematic cross-sectional view showing an IGBT-ESD device according to yet another embodiment of the present invention. In FIG. 4A, an IGBT-ESD device 400a includes a semiconductor substrate 410, a high voltage N-type well 415b in the semiconductor substrate, and a high voltage P-type well 415c in the semiconductor substrate. A patterned isolation region 430a-430d is disposed on the semiconductor substrate, defining a first active region in the high voltage N-type well 415b and a second active region and a third active region in the high voltage P-type well 415c . The high voltage P-type well 415a is disposed under the isolation region 430a. A P-type heavily doped drain region 417 is disposed in the first active region, an N-type heavily doped source region 424 is disposed in the second active region, and a P-type heavily doped diffusion region 422 is set in the third active area. A gate structure 440 is on the high voltage P-type well 415c, one end of which is in contact with the N-type heavily doped source region 424, and the other end extends to the patterned isolation region 430b.

FIG. 4B is a schematic cross-sectional view showing an IGBT-ESD device according to yet another embodiment of the present invention. In FIG. 4B, an IGBT-ESD device 400b includes a semiconductor substrate 410, such as a P-type silicon substrate 401, on which there is a P-type epitaxial layer 403, and an N-type buried layer 402 is disposed on the P-type Between the silicon substrate 401 and the P-type epitaxial layer 403 . A high voltage N-type well 415b is in the semiconductor substrate, and a high voltage P-type well 415c is in the semiconductor substrate. A patterned isolation region 430a-430f is disposed on the semiconductor substrate, defining a first active region in the high voltage N-type well 415b and a second active region and a third active region in the high voltage P-type well 415c . A high voltage N-type well 415d is disposed under the isolation region 430e. A P-type heavily doped drain region 417 is disposed in the first active region, an N-type heavily doped source region 424 is disposed in the second active region, and a P-type heavily doped diffusion region 422 is set in the third active area. Furthermore, an additional P-type heavily doped region 416 is disposed in the high voltage P-type well 415a, and an additional P-type heavily doped region 426 is disposed in the high voltage P-type well 415e. A gate structure 440 is on the high voltage P-type well 415c, one end of which is connected to the N-type heavily doped source region 424, and the other end extends to the patterned isolation region 430c.

FIG. 5 is a schematic cross-sectional view showing an IGBT-ESD device according to yet another embodiment of the present invention. In FIG. 5, an IGBT-ESD device 500 includes: a semiconductor substrate 510, and a patterned isolation region 530a-530c disposed on the semiconductor substrate 510, defining a first active region and a second active region. A gate structure 540 is disposed on the first active region of the semiconductor substrate, and an N-type double diffusion region 516 is disposed on one side of the gate structure 540 and disposed in the first active region of the semiconductor substrate 510 . An N-type well 515 is disposed in the N-type double diffusion region 516 , the bottom of which extends to the semiconductor substrate 510 , and a P-type heavily doped drain region 517 is disposed in the N-type well 515 . An N-type heavily doped source region 524 is disposed in the semiconductor substrate on the other side of the gate structure 540 , and an N-type lightly doped (NLDD) region 524 ′ extends to the gap of the gate structure 540 below the wall. A P-type dense diffusion region 522 is disposed in the second active region of the semiconductor substrate.

It should be noted that the area of the P-type densely doped drain region of the IGBT-ESD element of each embodiment of the present invention is smaller than the area of the high-voltage N-type well, so that the high-voltage N-type well and the P-type densely doped There is a hetero-doped interface between the drain regions, which can disperse and reduce the ESD voltage by about 0.7V. What's more, the P-type densely doped drain region is a plurality of separated island regions, which are arranged in the high-voltage N-type well, so that there is a heterogeneous doping between each island region and the high-voltage N-type well. The interface can disperse and reduce the ESD voltage, so that the IGBT-ESD components can be started more uniformly (uniform turn-on).

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Anyone with ordinary knowledge in the technical field can make some changes without departing from the spirit and scope of the present invention. and modification, so the protection scope of the present invention should be defined by the scope of the appended claims.

Claims (4)

1. a protecting component for electrostatic discharge of grid insulating double-junction transistor is characterized in that, described protecting component for electrostatic discharge of grid insulating double-junction transistor comprises:

The semiconductor substrate;

One high pressure N-type trap is in described semiconductor base;

The isolated area of one patterning is arranged on the described high pressure N-type trap, defines one first active region and one second active region;

One N-type double diffusion district is arranged in described first active region of described high pressure N-type trap;

The dense doped drain region of one P-type is arranged in the described N-type double diffusion district;

One P-type body doped region is in described second active region of described high pressure N-type trap, and wherein said N-type double diffusion district and the described P-type body doped region specific range of being separated by exposes described high pressure N-type trap;

The a pair of adjacent dense doping source region of a N-type and the dense doping source region of a P-type are arranged in the described P-type body doped region; And

One grid structure is on described high pressure N-type trap, one end and the dense doping source region of described N-type join, its other end extends on the isolated area of described patterning, the area of the dense doped drain region of wherein said P-type is less than the area of described the first active region, and the dense doped drain region of described P-type comprises the island district of a plurality of separation.

2. a protecting component for electrostatic discharge of grid insulating double-junction transistor is characterized in that, described protecting component for electrostatic discharge of grid insulating double-junction transistor comprises:

The semiconductor substrate;

One high pressure N-type trap is in described semiconductor base;

The isolated area of one patterning is arranged on the described high pressure N-type trap, defines one first active region and one second active region;

One P-type double diffusion district is arranged in described first active region of described high pressure N-type trap;

The dense doped drain region of one P-type is arranged in the described P-type double diffusion district;

One P-type body doped region is in described second active region of described high pressure N-type trap, and wherein said P-type double diffusion district and the described P-type body doped region specific range of being separated by exposes described high pressure N-type trap;

The a pair of adjacent dense doping source region of a N-type and the dense doping source region of a P-type are arranged in the described P-type body doped region; And

One grid structure is on described high pressure N-type trap, one end and the dense doping source region of described N-type join, its other end extends on the isolated area of described patterning, the area of the dense doped drain region of wherein said P-type is less than the area of described the first active region, and the dense doped drain region of described P-type comprises the island district of a plurality of separation.

3. a protecting component for electrostatic discharge of grid insulating double-junction transistor is characterized in that, described protecting component for electrostatic discharge of grid insulating double-junction transistor comprises:

The semiconductor substrate;

One high pressure P-type trap is in described semiconductor base;

One high pressure N-type trap is in described semiconductor base;

The isolated area of one patterning is arranged on the described semiconductor base, defines one first active region in described high pressure N-type trap and one second active region and one the 3rd active region in described high pressure P-type trap;

The dense doped drain region of one P-type is arranged in described the first active region;

The dense doping source region of one N-type is arranged in described the second active region, and the dense doping source region of a P-type is arranged in described the 3rd active region; And

One grid structure is on described high pressure P-type trap, one end and the dense doping source region of described N-type join, its other end extends on the isolated area of described patterning, the area of the dense doped drain region of wherein said P-type is less than the area of described the first active region, and the dense doped drain region of described P-type comprises the island district of a plurality of separation.

4. a protecting component for electrostatic discharge of grid insulating double-junction transistor is characterized in that, described protecting component for electrostatic discharge of grid insulating double-junction transistor comprises:

The semiconductor substrate;

The isolated area of one patterning is arranged on the described semiconductor base, defines one first active region and one second active region;

One grid structure is arranged on described first active region of described semiconductor base;

One N-type double diffusion district is positioned at a side of described grid structure, and arranges in described first active region of described semiconductor base;

One N-type trap is arranged in the described N-type double diffusion district, and its bottom extends to described semiconductor base;

The dense doped drain region of one P-type is arranged in the described N-type trap;

The dense doping source region of one N-type is arranged in the described semiconductor base of opposite side of described grid structure; And

The dense diffusion region of one P-type is arranged in described second active region of described semiconductor base, and the area of the dense doped drain region of wherein said P-type is less than the area of described the first active region, and the dense doped drain region of described P-type comprises the island district of a plurality of separation.

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