CN102142392A - Semiconductor device and manufacturing method thereof - Google Patents
Semiconductor device and manufacturing method thereof Download PDFInfo
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- CN102142392A CN102142392A CN2010101066258A CN201010106625A CN102142392A CN 102142392 A CN102142392 A CN 102142392A CN 2010101066258 A CN2010101066258 A CN 2010101066258A CN 201010106625 A CN201010106625 A CN 201010106625A CN 102142392 A CN102142392 A CN 102142392A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
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- 239000004020 conductor Substances 0.000 claims abstract description 41
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
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Abstract
The invention provides a semiconductor device and a manufacturing method thereof, wherein the semiconductor device comprises: a substrate; a buried layer located in the substrate; and a first deep trench contact structure formed in the substrate, wherein the first deep trench contact structure comprises a conductive material and a liner layer on a sidewall of the conductive material, and a bottom surface of the first deep trench contact structure is in contact with the buried layer. The conductive material of the deep trench contact structure can be formed by chemical vapor deposition in an environment with impurity-doped gas without additional doping process, so as to avoid the possible problems of pollution or device performance reduction. The side wall of the deep trench contact structure has a liner layer with an insulation effect, so that the deep trench contact structure can be used as an isolation element, can be used for defining an active region of an element, and can reduce the area of the active region required by a single element so as to greatly improve the number of elements which can be configured in a single wafer and improve the element density.
Description
Technical field
The invention relates to a kind of semiconductor device and manufacture method thereof, particularly relevant for deep trenches contact structures and manufacture method thereof.
Background technology
In semiconductor technology now, in order to reach the operation of system-on-a-chip (single-chip system), controller, memory, low voltage operated circuit and the power component height of operation with high pressure are integrated on the one chip, it is several that wherein the research and development kind of power component includes rectilinear dmost (VDMOS), insulated gate electrode two-carrier transistor (IGBT), transverse type power transistor (LDMOS) etc., and its research and development purpose is to improve the loss that power supply conversion efficiency reduces the energy.Owing on one chip, need provide high-pressure crystal tube elements and low voltage CMOS circuit element simultaneously, therefore on technology, need to make isolation structure in order to isolated adjacent element, and the conductor structure that can admittance causes the spurious charge of parasitic capacitance.
See also Fig. 1, it shows the generalized section of existing high voltage device.Can be with reference to the patent of U.S. Patent number case US 7,242,070 B2.With a P type semiconductor substrate 10 is example, has a N type epitaxial loayer 40 on its surface.Have a plurality of P+ type isolation structures 50 in the N type epitaxial loayer 40, in order to define the active area of rectilinear double diffusion N type metal oxide semiconductor transistor (VDNMOS) and the transistorized high voltage device of two-carrier (Bipolar).The surface of N type epitaxial loayer 40 have a plurality of field oxides (field oxide, FOX) 18, it is in order to the component structure in the isolated high voltage device active area.Rectilinear double diffusion N type metal oxide semiconductor transistor comprises the P type body 36 that is positioned at N type epitaxial loayer 40, is positioned at the N type doped region 32 and the P type doped region 34 of P type body 36, and the lip-deep grid structure 30 that is positioned at N type epitaxial loayer 40.The two-carrier transistor comprise the P type body 36 that is positioned at N type epitaxial loayer 40 ', and be positioned at P type body 36 ' N type doped region 32 ' and P type doped region 34 '.In the N type epitaxial loayer 40 in the active area of high voltage device, also have N+ type raceway groove 60 and 60 ', it runs through N type epitaxial loayer 40, and partly be embedded into N type buried horizon 2 and 2 between N type epitaxial loayer 40 and P type semiconductor substrate 10 ' in.N+ type raceway groove 60 and 60 ' with the contact plunger 19 that is positioned at interlayer dielectric layer 16, and the metal level 21 that is positioned at contact plunger 19 tops is electrically connected.
N+ type raceway groove 60 and 60 ' generally is to carry out doping process with high dose and high-octane N type impurity, and the activating process of high heat budget (thermal budget) forms.Because N+ type raceway groove 60 and 60 ' and having a high concentration impurities, it is subjected to pollutant in release gas (out gassing) in activating process and the reaction environment and contaminated easily, and the problem that causes its usefulness to reduce.Consider down N+ type raceway groove 60 and 60 ' must therefore limit the parts number that can dispose in the single wafer away from P+ type isolation structure 50 in element support pressure and technology.
See also Fig. 2, it shows the generalized section of existing high voltage device, wherein the P+ type isolation structure 50 to be replaced among Fig. 1 by the formed deep trenches insulation system 70 of dielectric material.Though use deep trenches insulation system 70 can improve the problem of its area size of active area of high voltage device, but the degree of depth of deep trenches insulation system 70 generally need far be deeper than the degree of depth of N type epitaxial loayer 40, can overcome the noise problem that is caused under the operating environment of high pressure.Have deep trenches insulation system 70 its manufacture methods of high depth and be not easy, and the control of depth-to-width ratio also is the challenge that need overcome in the technology.Therefore the depth limit of deep trenches insulation system 70 has limited the size of its operating voltage of high voltage device.
Therefore having to provide a kind of semiconductor device and forming method thereof, to overcome the deficiency of existing skill.
Summary of the invention
, other and of the present invention purpose above-mentioned for reaching the invention provides a kind of semiconductor device, comprising: a substrate; One buried horizon is positioned at this substrate; And one first deep trenches contact structures, form in this substrate, wherein these first deep trenches contact structures comprise an electric conducting material, and a laying that is positioned on the sidewall of this electric conducting material, and the basal surface of these first deep trenches contact structures contacts with this buried horizon.
The present invention also provides a kind of manufacture method of semiconductor device, comprises the following steps: to provide a substrate, and it has a buried horizon and is positioned at wherein; Form one first deep trenches contact structures, in this substrate, wherein these first deep trenches contact structures comprise an electric conducting material, and a laying that is positioned on the sidewall of this electric conducting material, and the basal surface of these first deep trenches contact structures contacts with this buried horizon.
In disclosed semiconductor device of embodiments of the invention and forming process thereof, be beneficial to and have buried horizon in substrate wherein, form the deep trenches contact structures, wherein the deep trenches contact structures comprise electric conducting material and are positioned at laying on the sidewall of electric conducting material.The electric conducting material of deep trenches contact structures can be under the environment when participating in the cintest of the gas with impurity, form in the chemical vapour deposition (CVD) mode, and need not carry out extra doping process, with the problem of avoiding issuable pollution or element efficiency to reduce, so the deep trenches contact structures can be designed in the position of close main element.And the sidewall of deep trenches contact structures has the laying of insulating effect, therefore can be used as isolated component, more can be in order to the active area of definition element, and can reduce the area of the needed active area of single element, significantly to promote the parts number that can dispose in the single wafer and to improve component density.
The degree of depth of deep trenches contact structures can provide high voltage device good isolated environment under the condition of the degree of depth that is no more than buried horizon, makes high voltage device can show desired usefulness under the environment of higher operating voltage.And the formation of deep trenches contact structures more is not subjected to the control problem of the depth-to-width ratio of irrigation canals and ditches, so technology is simpler.When the polysilicon that select to mix during as the electric conducting material in the deep trenches contact structures, its can the oxidiferous laying of buffers packet and epitaxial loayer between because the stress that crystal lattice difference caused, with the stability and the effect thereof of lift elements.
Buried horizon can be connected with external electric by the deep trenches contact structures.Therefore, because near the spurious charge that the operate high pressure element is caused buried horizon can conduct to the outside via the deep trenches contact structures, with the problem of avoiding noise to produce.The voltage of buried horizon also can be controlled by the outside via the deep trenches contact structures.Doped region can be formed in the buried horizon of deep trenches contact structures below.Because the impurity concentration greater than buried horizon of doped region impurity concentration, therefore the resistance at preferable interface can be provided, and form more stable conductive member.Buried horizon can be by first disposal area with higher doping content, and second disposal area with lower doping content constitutes, wherein first disposal area can be coated on, or part be arranged in second disposal area, therefore have under the purpose of preferable conductive effectiveness in first disposal area, but the second disposal area lift elements the operating voltage that can bear.
Description of drawings
Fig. 1 to Fig. 2 shows the profile of existing high voltage device;
Fig. 3 to Fig. 6 shows the profile according to the formation deep trenches contact structures of the embodiment of the invention;
Fig. 7 A to Fig. 7 D shows the profile according to the semiconductor device of the embodiment of the invention;
Fig. 8 A to Fig. 8 D is the profile that corresponds respectively to another embodiment of Fig. 7 A to Fig. 7 D;
Fig. 9 A to Fig. 9 D is the profile that corresponds respectively to another embodiment of Fig. 8 A to Fig. 8 D;
Figure 10 A to Figure 10 D is the profile that corresponds respectively to another embodiment of Fig. 8 A to Fig. 8 D;
Figure 11 A to Figure 11 D is the profile that corresponds respectively to another embodiment of Figure 10 A to Figure 10 D.
Drawing reference numeral:
2～N type buried horizon;
2 '～N type buried horizon;
The substrate of 10～P type semiconductor;
16～interlayer dielectric layer;
17～barrier layer;
18～field oxide;
19～contact plunger;
21～metal level;
30～grid structure;
40～N type epitaxial loayer;
32～N type doped region;
32 '～N type doped region;
34～P type doped region;
34 '～P type doped region;
36～P type body;
36 '～P type body;
50～P+ type isolation structure;
60～N+ type raceway groove;
60 '～N+ type raceway groove;
70～deep trenches insulation system;
100～substrate;
102～buried horizon;
102A～first disposal area;
102B～second disposal area;
110A～deep trenches;
110B～deep trenches;
112A～laying;
112B～laying;
114A～electric conducting material;
114B～electric conducting material;
116～doped region;
120A～deep trenches contact structures;
120B～deep trenches contact structures;
130～isolation structure;
140～epitaxial loayer;
150～mask layer;
151～interlayer dielectric layer;
152～barrier layer;
153～contact plunger;
154～metal level;
180～field oxide.
Embodiment
Embodiments of the invention provide a kind of semiconductor device and manufacture method thereof.About the manufacture of each embodiment with occupation mode is following describes in detail, and follow diagram to be illustrated.Wherein, the identical or similar elements of using in graphic and the specification of components identical numbering expression.And in graphic, for the purpose of clear and convenient explanation, shape and the thickness of relevant embodiment or the situation that is not inconsistent reality is arranged.And the following description person of institute is illustrated at each item or its integration of device of the present invention especially, yet, it should be noted that, said elements is not particularly limited in shown or description, but various forms that can those skilled in the art learnt, in addition, when the layer of material layer is when being positioned on another material layer or the substrate, it can be to be located immediately at its surface to go up or be inserted with in addition other intermediary layers.
Fig. 3 to Fig. 6 shows according to the embodiment of the invention to send out the profile of making a kind of semiconductor device.Though specific embodiments of the invention with rectilinear double diffusion N type metal oxide semiconductor transistor (VDNMOS) and the transistorized high voltage device of two-carrier (Bipolar) as an illustration.Scrutable is that notion of the present invention can certainly be applied to the making of other semiconductor element.
Please refer to Fig. 3, a substrate 100 is provided, can have an epitaxial loayer 140 on it, can have buried horizon 102 between substrate 100 and the epitaxial loayer 140.Can have isolation structure 130 in the epitaxial loayer 140 in buried horizon 102 outsides.Substrate 100 can comprise the base material of silicon or other suitable semi-conducting material.Substrate 100, epitaxial loayer 140 and buried horizon 102 generally can have different electrically.In a specific embodiment, substrate 100 can be the P-type conduction type, and epitaxial loayer 140 can be N type conductivity type, and buried horizon 102 can be N type conductivity type, and isolation structure 130 can be the P-type conduction type.Please refer to Fig. 3, after can forming mask layer 150 and being covered in epitaxial loayer 140 tops,,, for example be positioned at field oxide 180 its surfaces of epitaxial loayer 140 tops that desire removes to expose the surface in zone to be removed with mask layer 150 patternings.
Please refer to Fig. 4, the field oxide 180 that the mask layer 150 of patterning can be exposed, and be positioned at the epitaxial loayer 140 of its below and the buried horizon 102 of partial depth is removed, to form a deep trenches 110A, wherein deep trenches 110A exposes buried horizon 102.In other embodiment, field oxide 180 that the mask layer 150 of patterning can be exposed and the epitaxial loayer 140 that is positioned at its below are removed, and to form a deep trenches 110A, wherein deep trenches 110A exposes the upper surface (not being shown among the figure) of buried horizon 102.Then, form a laying 112A on the bottom and sidewall of deep trenches 110A.Carry out etching technics again the laying 112A on the bottom of deep trenches 110A is removed, stay the laying 112A on the sidewall of deep trenches 110A.Laying 112A can comprise for example tetraethoxysilane (tetraethoxy silane, oxide TEOS).
Please refer to Fig. 5,, can carry out a doping process with formation doped region 116 buried horizon 102 that is exposed in deep trenches 110A in forming laying 112A after on the sidewall of deep trenches 110A.Doped region 116 can have the conductivity type identical with buried horizon 102.In an embodiment, doped region 116 is all N type conductivity type with buried horizon 102.Behind doping process, can be to carrying out an annealing process behind the doped region 116, the impurity that makes doped region 116 diffuses to more lateral or darker zone toward direction laterally or longitudinally, for example diffuses to the zone of laying 112A below, as shown in Figure 5.In other embodiments, can in buried horizon 102, not form doped region 116.The formation of doped region 116 can provide preferable implant uniformity (uniformity).The doping content of doped region 116 generally can be greater than the doping content of buried horizon 102, forming the resistance at preferable interface, and more stable conductive member.
Please refer to Fig. 6, then form electric conducting material 114A with filling deep trenches 110A, and form deep trenches contact structures 120A.In an embodiment, can carry out one time etch step again, the part electric conducting material 114A that is formed at the height that is higher than deep trenches 110A is removed.Electric conducting material 114A can comprise the conductive materials of the polysilicon that for example mixes.In a preferred embodiment, electric conducting material 114A is under the environment (in-situ) when participating in the cintest of the gas with impurity, with the polysilicon of the formed doping of chemical vapour deposition technique.Electric conducting material 114A, doped region 116 and buried horizon 102 can be identical conductivity type.In an embodiment, electric conducting material 114A, doped region 116 and buried horizon 102 are all N type conductivity type.In a preferred embodiment, electric conducting material 114A is the polysilicon with N type doping impurity.In other embodiment, electric conducting material 114A can comprise for example metal of tungsten or aluminium etc.
After forming deep trenches contact structures 120A, can above mask layer 150, continue to form interlayer dielectric layer 151, the contact plunger 153 that passes interlayer dielectric layer 151 and be electrically connected, for example tungsten plug with deep trenches contact structures 120A and high voltage device.The width of contact plunger 153 can less than, be equal to or greater than isolation structure 130 or deep trenches contact structures 120A.In an embodiment, the sidewall of contact plunger 153 and bottom can have the barrier layer 152 of titanium for example or titanium nitride, and the metal level 154 that is positioned at contact plunger 153 tops.Buried horizon 102, doped region 116 and deep trenches contact structures 120A can be connected with external electric by contact plunger 153 and metal level 154.Therefore, deep trenches contact structures 120A can conduct the spurious charges that caused owing to the operate high pressure element near buried horizon 102, to avoid producing the problem of noise.The voltage of buried horizon 102 also can be controlled by the outside via deep trenches contact structures 120A.
Because it is big generally to comprise the laying 112A and the epitaxial loayer 140 crystal lattice difference degree each other of oxide, therefore be easy to generate stress at its joint interface place, especially the high-temperature technology that is carried out in subsequent fabrication steps more may increase the otherness of lattice and causes structural defective.The polysilicon that select to mix can cushion stress problem between the above-mentioned material and then the stability of lift elements and effect thereof as electric conducting material 114A.
Because the electric conducting material 114A of deep trenches contact structures 120A can be under the environment when participating in the cintest of the gas with impurity, form in the chemical vapour deposition (CVD) mode, and need not carry out extra doping process, to avoid carrying out the issuable pollution problem of doping process, or the problem that reduces of the element efficiency that causes of diffusion of impurities, so deep trenches contact structures 120A can be designed in the position near main element.And because the sidewall of deep trenches contact structures 120A has for example laying 112A with insulating effect of oxide, therefore deep trenches contact structures 120A also can be used as the isolation structure of isolated element, in an embodiment, can deep trenches contact structures 120A the active area of definition element.In addition, the degree of depth of deep trenches contact structures 120A can be no more than the degree of depth of buried horizon 102.Therefore, deep trenches contact structures 120A can provide excellent isolated effect, increasing the voltage that element can bear, and can reduce the area of the needed active area of single element, and significantly promote the parts number that can dispose single wafer in the raising component density.
Fig. 7 A to Figure 11 D is the embodiment according to above-mentioned Fig. 3 to Fig. 6, the profile of extended other embodiment.Wherein similar to Fig. 3 to Fig. 6 part will no longer be given unnecessary details.Please refer to Fig. 7 A to Fig. 7 D, it shows a substrate 100, it has a buried horizon 102 and deep trenches contact structures 120A is positioned at wherein, wherein deep trenches contact structures 120A has electric conducting material 114A and is positioned at laying 112A on the sidewall of electric conducting material 114A, and the bottom of deep trenches contact structures 120A and partly the sidewall of the degree of depth can contact with buried horizon 102.In other embodiments, can have doped region (not being shown among the figure) in the buried horizon 102 of deep trenches contact structures 120A below.
Buried horizon 102 can be the buried horizon 102 of single doping content, shown in Fig. 7 A.In the shown embodiment of Fig. 7 B to Fig. 7 D, buried horizon 102 can comprise the first disposal area 102A with higher doping content, and the second disposal area 102B with lower doping content.The first disposal area 102A can be coated among the second disposal area 102B, shown in Fig. 7 B and Fig. 7 C.The first disposal area 102A also can partly be arranged in the second disposal area 102B, shown in Fig. 7 D.Because the first disposal area 102A has the higher doping content compared to the second disposal area 102B, so the resistance of the first disposal area 102A is low than the resistance of the second disposal area 102B, therefore the first disposal area 102A can provide preferable conductive effectiveness.And be positioned at outside the first disposal area 102A, and the second disposal area 102B with lower doping content, because its resistance is than the resistance height of the first disposal area 102A, so it can have under the purpose of preferable conductive effectiveness the operating voltage that lift elements can be born at the first disposal area 102A.
In the shown embodiment of Fig. 7 A to Fig. 7 D, can in substrate 100, define wellblock 104 by deep trenches contact structures 120A and buried horizon 102.In other embodiment, can in wellblock 104, form for example other elements of high voltage device (not being shown among the figure) etc.In preferred embodiment, substrate 100 can be the P-type conduction type, and buried horizon 102 can be N type conductivity type, and wellblock 104 can be N type conductivity type.
Fig. 8 A to Fig. 8 D corresponds respectively to the profile of another embodiment of above-mentioned Fig. 7 A to Fig. 7 D, and wherein similar part will no longer be given unnecessary details.Please refer to Fig. 8 A to Fig. 8 D, the surface of substrate 100 can have epitaxial loayer 140.Buried horizon 102 can be formed between substrate 100 and the epitaxial loayer 140.Deep trenches contact structures 120A can be formed in the epitaxial loayer 140, and the sidewall of the bottom of deep trenches contact structures 120A and the part degree of depth can contact with buried horizon 102.Can in epitaxial loayer 140, define wellblock 104 by deep trenches contact structures 120A and buried horizon 102.In an embodiment, can have doped region (not being shown among the figure) in the buried horizon 102 of deep trenches contact structures 120A below.In an embodiment, substrate 100 can be the P-type conduction type, and buried horizon 102 can be N type conductivity type, and wellblock 104 can be the P-type conduction type.In other embodiment, substrate 100 can be the P-type conduction type, and buried horizon 102 can be N type conductivity type, and wellblock 104 can be N type conductivity type.In one embodiment, can in wellblock 104, form for example false rectilinear dmost (pseudo-VDMOS) or other elements.
9A figure to the 9D figure corresponds respectively to the profile of another embodiment of above-mentioned Fig. 8 A to Fig. 8 D, and wherein similar part will no longer be given unnecessary details.Please refer to Fig. 9 A to Fig. 9 D, can in the epitaxial loayer 140 in the buried horizon 102 and the deep trenches contact structures 120A outside, form isolation structure 130 in substrate 100 tops.In an embodiment, can have doped region (not being shown among the figure) in the buried horizon 102 of deep trenches contact structures 120A below.The conductivity type of isolation structure 130 can be identical with the conductivity type of (but being not limited to) substrate 100.The conductivity type of isolation structure 130 can be different with the conductivity type of (but being not limited to) buried horizon 102.In an embodiment, substrate 100 can be the P-type conduction type, and buried horizon 102 can be N type conductivity type, and wellblock 104 can be the P-type conduction type, and isolation structure 130 can be the P-type conduction type.
Figure 10 A to Figure 10 D corresponds respectively to the profile of another embodiment of above-mentioned Fig. 8 A to Fig. 8 D, and wherein similar part will no longer be given unnecessary details.Please refer to Figure 10 A to Figure 10 D, can in the epitaxial loayer 140 in the buried horizon 102 and the deep trenches contact structures 120A outside, form deep trenches contact structures 120B, and the degree of depth of deep trenches contact structures 120B can be greater than epitaxial loayer 140.In an embodiment, can have doped region in the buried horizon 102 of deep trenches contact structures 120A below, or the substrate 100 of deep trenches contact structures 120B below can have doped region (not being shown among the figure).The degree of depth of deep trenches contact structures 120B can greater than, be equal to or less than deep trenches contact structures 120A.In an embodiment, can replace deep trenches contact structures 120B by the deep trenches insulation system, and the degree of depth of deep trenches insulation system is greater than deep trenches contact structures 120A (not shown).The structure of deep trenches contact structures 120B is similar to deep trenches contact structures 120A, is no longer given unnecessary details at this.The electric conducting material 114B of deep trenches contact structures 120B can be identical with the electric conducting material 114A of (but being not limited to) deep trenches contact structures 120A.The laying 112B of deep trenches contact structures 120B can be identical with the laying 112A of (but being not limited to) deep trenches contact structures 120A.In an embodiment, substrate 100 can be the P-type conduction type, and buried horizon 102 can be N type conductivity type, and wellblock 104 can be N type conductivity type.
Figure 11 A to Figure 11 D corresponds respectively to the profile of another embodiment of above-mentioned Figure 10 A to Figure 10 D, and wherein similar part will no longer be given unnecessary details.Please refer to Figure 11 A to Figure 11 D, isolation structure 130 can be formed in the epitaxial loayer 140 between deep trenches contact structures 120A and the deep trenches contact structures 120B.In an embodiment, can have doped region in the buried horizon 102 of deep trenches contact structures 120A below, or the substrate 100 of deep trenches contact structures 120B below can have doped region (not being shown among the figure).The degree of depth of deep trenches contact structures 120B can greater than, be equal to or less than deep trenches contact structures 120A.In an embodiment, can replace deep trenches contact structures 120B by the deep trenches insulation system, and the degree of depth of deep trenches insulation system is greater than deep trenches contact structures 120A (not shown).In an embodiment, substrate 100 can be the P-type conduction type, and buried horizon 102 can be N type conductivity type, and wellblock 104 can be N type conductivity type, and isolation structure 130 can be the P-type conduction type.
In disclosed semiconductor device of embodiments of the invention and forming process thereof, be beneficial to and have buried horizon in substrate wherein, form the deep trenches contact structures, wherein the deep trenches contact structures comprise electric conducting material and are positioned at laying on the sidewall of electric conducting material.The electric conducting material of deep trenches contact structures can be under the environment when participating in the cintest of the gas with impurity, form in the chemical vapour deposition (CVD) mode, and need not carry out extra doping process, with the problem of avoiding issuable pollution or element efficiency to reduce, so the deep trenches contact structures can be designed in the position of close main element.And the sidewall of deep trenches contact structures has the laying of insulating effect, therefore can be used as isolated component, more can be in order to the active area of definition element, and can reduce the area of the needed active area of single element, significantly to promote the parts number that can dispose in the single wafer and to improve component density.
The degree of depth of deep trenches contact structures can provide high voltage device good isolated environment under the condition of the degree of depth that is no more than buried horizon, makes high voltage device can show desired usefulness under the environment of higher operating voltage.And the formation of deep trenches contact structures more is not subjected to the control problem of the depth-to-width ratio of irrigation canals and ditches, so technology is simpler.When the polysilicon that select to mix during as the electric conducting material in the deep trenches contact structures, its can the oxidiferous laying of buffers packet and epitaxial loayer between because the stress that crystal lattice difference caused, with the stability and the effect thereof of lift elements.
Buried horizon can be connected with external electric by the deep trenches contact structures.Therefore, because near the spurious charge that the operate high pressure element is caused buried horizon can conduct to the outside via the deep trenches contact structures, with the problem of avoiding noise to produce.The voltage of buried horizon also can be controlled by the outside via the deep trenches contact structures.Doped region can be formed in the buried horizon of deep trenches contact structures below.Because the impurity concentration greater than buried horizon of doped region impurity concentration, therefore the resistance at preferable interface can be provided, and form more stable conductive member.Buried horizon can be by first disposal area with higher doping content, and second disposal area with lower doping content constitutes, wherein first disposal area can be coated on, or part be arranged in second disposal area, therefore have under the purpose of preferable conductive effectiveness in first disposal area, but the second disposal area lift elements the operating voltage that can bear.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (15)
1. a semiconductor device is characterized in that, described semiconductor device comprises:
One substrate;
One buried horizon is positioned at described substrate; And
One first deep trenches contact structures, form in the described substrate, the wherein said first deep trenches contact structures comprise the laying on the sidewall that an electric conducting material and is positioned at described electric conducting material, and the basal surface of the described first deep trenches contact structures contacts with described buried horizon.
2. semiconductor device as claimed in claim 1 is characterized in that, described semiconductor device more comprises one first doped region, between described first deep trenches contact structures and described buried horizon.
3. semiconductor device as claimed in claim 1, it is characterized in that, described buried horizon comprises one first disposal area and one second disposal area, wherein said first disposal area is in abutting connection with described second disposal area, described first disposal area and described second disposal area have identical conduction type, and the carrier concentration of described first disposal area is greater than the carrier concentration of described second disposal area.
4. semiconductor device as claimed in claim 3 is characterized in that, at least one contacts the basal surface of the described first deep trenches contact structures and described first disposal area or described second disposal area.
5. semiconductor device as claimed in claim 1 is characterized in that the top of described substrate has an epitaxial loayer.
6. semiconductor device as claimed in claim 5 is characterized in that described semiconductor device more comprises an isolation structure, is arranged in the described epitaxial loayer in described buried horizon and the described first deep trenches contact structures outside.
7. semiconductor device as claimed in claim 6 is characterized in that, described isolation structure in abutting connection with described buried horizon or the described first deep trenches contact structures at least one.
8. semiconductor device as claimed in claim 6 is characterized in that, described isolation structure and described buried horizon and the described first deep trenches contact structures separate.
9. semiconductor device as claimed in claim 5 is characterized in that, described semiconductor device more comprises:
One second deep trenches contact structures are formed in the described epitaxial loayer, and the wherein said second deep trenches contact structures comprise described electric conducting material, and are positioned at the described laying on the sidewall of described electric conducting material.
10. semiconductor device as claimed in claim 9 is characterized in that, described semiconductor device comprises that more an isolation structure is between described first deep trenches contact structures and the described second deep trenches contact structures.
11. semiconductor device as claimed in claim 5 is characterized in that, described semiconductor device more comprises:
One second deep trenches insulation system is formed in the described epitaxial loayer.
12. the manufacture method of a semiconductor device is characterized in that, the manufacture method of described semiconductor device comprises the following steps:
One substrate is provided, and it has a buried horizon and is positioned at wherein;
Form one first deep trenches contact structures, in described substrate, the wherein said first deep trenches contact structures comprise the laying on the sidewall that an electric conducting material and is positioned at described electric conducting material, and the basal surface of the described first deep trenches contact structures contacts with described buried horizon.
13. the manufacture method of semiconductor device as claimed in claim 12, it is characterized in that, described buried horizon comprises one first disposal area and one second disposal area, wherein said first disposal area is in abutting connection with described second disposal area, described first disposal area and described second disposal area have identical conduction type, and the carrier concentration of described first disposal area is greater than the carrier concentration of described second disposal area.
14. the manufacture method of semiconductor device as claimed in claim 12, it is characterized in that, the top of described substrate has an epitaxial loayer, described epitaxial loayer below, described buried horizon position, the described first deep trenches contact structures are formed in the described epitaxial loayer, and the basal surface of the described first deep trenches contact structures contacts with described buried horizon.
15. the manufacture method of semiconductor device as claimed in claim 14, it is characterized in that, the manufacture method of described semiconductor device more comprises formation one second deep trenches contact structures in described epitaxial loayer, the wherein said second deep trenches contact structures comprise described electric conducting material, and be positioned at described laying on the sidewall of described electric conducting material, and the basal surface of the described second deep trenches contact structures contacts with described substrate.
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