CN102157192A

CN102157192A - Method for compensating memory particle data delay of synchronous dynamic random access memory

Info

Publication number: CN102157192A
Application number: CN201010598448XA
Authority: CN
Inventors: 李静; 白宗元; 张磊; 纪奎; 张英文
Original assignee: Dawning Information Industry Co Ltd
Current assignee: Dawning Information Industry Co Ltd
Priority date: 2010-12-17
Filing date: 2010-12-17
Publication date: 2011-08-17

Abstract

The invention provides a method for compensating memory particle data delay of an SDRAM (Synchronous Dynamic Random Access Memory), which is realized by utilizing an FPGA (Field Programmable Gate Array). Each mainboard is provided with a plurality of memory controllers; each memory controller is used for controlling read-write of four memories and measuring working clock of each memory; and the FPGA is used for determining a phase of the working clock according to the position of each memory and regulating time delay error brought by different PCB (Printed Circuit Board) wirings of the memory positions through regulating the phase of the clock. In the design of a high-capacity multi-memory controller system, the wiring error caused by the PCB wirings can be greatly eliminated, the PCB wiring difficulty is decreased, and the design risk is reduced.

Description

A kind of method that compensates source Synchronous Dynamic Random Access Memory internal memory particle data delay

Technical field

The present invention relates to the Memory Controller Hub design field, be specifically related to the method for a kind of compensation source Synchronous Dynamic Random Access Memory (Synchronous Dynamic Random Access Memory is called for short SDRAM) internal memory particle data delay.

Background technology

In high capacity, multi-memory system, signal integrity is the key of system design.Because Memory Controller Hub is inconsistent to the time that the inconsistent meeting of the track lengths between the internal memory causes arriving from the signal that Memory Controller Hub sends different sdram memory particles, walk SDRAM acknowledge(ment) signal evening time of line length with Memory Controller Hub, cabling short SDRAM acknowledge(ment) signal time, early the serious inconsistency of this cabling length significantly limited the frequency of operation of high capacity, multi-memory system.

In Memory Controller Hub design at present, in order to solve owing to the signal routing access delay of bringing different in size, cabling length to signal wire when wiring requires relatively stricter, the length gap must be controlled in the effective range, brought very big difficulty to PCB layout in high capacity, multi-memory system, design margin is very little.

Number of patent application is the method that 200510137024.2 patent " Memory Controller Hub and control method thereof " has been described the internal storage access delayed impact that a kind of PCB of reducing cabling brings, but adopt this method can obtain 8 clocks with system clock same frequency out of phase, each clock is compared with system clock and is postponed 1/8 clock period respectively.Memory Controller Hub can be selected different internal memory work clock phase places according to the different wire delays of walking, and can dynamically adjust according to postponing to change.But this method only is applicable under the situation of having only an internal memory that each internal memory can only be selected a phase place.And in multi-memory system (〉=4), this method is also inapplicable, in multi-memory system, many internal memory can be worked simultaneously, can not adopt the work clock of same phase place, article one internal memory and second internal memory promptly can occur, all different situation of phase place of the 3rd internal memory, can not lack dirigibility to these several memory shared clock phases like this.

Summary of the invention

The present invention utilizes field programmable logic device (FPGA) to realize the design of high capacity, many internal memories Memory Controller Hub, owing to the dirigibility of FPGA design, remedies the delayed impact of PCB cabling by the phase place of regulating every memory read-write clock.

A kind of method that compensates source Synchronous Dynamic Random Access Memory internal memory particle data delay is characterized in that: adopt FPGA to realize that process is as follows:

A, every mainboard assembling Memory Controller Hub;

B, each Memory Controller Hub are responsible for controlling the read-write of 4 internal memories;

The work clock of C, the every root memory of mensuration;

D, FPGA are according to the phase place of its work clock of determining positions of each internal memory, and its clock phase is regulated because the delay time error that the different PCB layout in memory bar position are brought by regulating.

A kind of optimal technical scheme of the present invention is: when the PCB cabling error of two or many internal memories differs very little, can regulate these memory shared identical clock and phase places.

Another kind of optimal technical scheme of the present invention is: described D step for measuring the track lengths of every root memory, is calculated conduction time according to the conduction of current velograph according to core position decision work clock phase method for position, sets clock phase then.

Another optimal technical scheme of the present invention is: the Memory Controller Hub that assembles on every mainboard is at least one.

The present invention can eliminate the wiring error of bringing owing to the PCB cabling greatly in high capacity, the system design of many internal memories Memory Controller Hub, less PCB layout difficulty reduces the design risk.Can be according to the phase place of the every memory read-write clock of length dynamic adjustments of PCB layout, and then the time-delay of each signal wire of adjusting internal memory, can accomplish each memory bar is disposed a clock phase separately, also can be configured to identical phase place, to satisfy sequential requirement to high capacity, many memory read-writes.

Description of drawings

Fig. 1 is the invention process process

Embodiment

As shown in Figure 1, each Memory Controller Hub is responsible for the read-write of 4 internal memories, every internal memory all has the clock clk0 of its work separately, clk1,, clk7 is because different in size cause of signal wire from FPGA to each internal memory, cause the time of signal arrival internal memory particle inconsistent, can cause the read-write of internal memory to make mistakes like this.FPGA is according to the phase place of its work clock of determining positions of each internal memory when design, and its clock phase is regulated because the error time-delay that the different PCB layout in memory bar position are brought by regulating.Nearest such as DIMM 0 from FPGA, the time-delay of PCB cabling is minimum, and the like, DIMM3 from FPGA farthest, PCB cabling time-delay is maximum, by FPGA when each internal memory provides work clock, the clock phase of DIMM0 can be postponed to transfer to maximum, the clock phase of DIMM3 postpones to transfer to minimum, like this by the clock phase adjustment, guarantee that signal wire can arrive each memory bar simultaneously, the influence that postpones to bring is reduced as far as possible.

Can also determine the phase place of each internal memory work clock according to the concrete condition of PCB cabling, differ very little such as PCB cabling error as if DIMM0 and DIMM1, like this when adjusting the clock phase of DIMM0 and DIMM1, can allow shared identical clock of DIMM0 and DIMM1 and phase place thereof, DIMM2 and DIMM3 and the like, best situation is that the PCB cabling of four internal memories is very nearly the same, and Memory Controller Hub can be these 4 memory shared same work clocks when design like this, needn't adjust successively separately.

Claims

1. method that compensates source Synchronous Dynamic Random Access Memory internal memory particle data delay is characterized in that: adopt FPGA to realize that process is as follows:

A, every mainboard assembling Memory Controller Hub;

The work clock of C, the every root memory of mensuration;

2. a kind of according to claim 1 method that compensates source Synchronous Dynamic Random Access Memory internal memory particle data delay, it is characterized in that: when the PCB cabling error of two or many internal memories differs very little, can regulate these memory shared identical clock and phase places.

3. a kind of according to claim 1 method that compensates source Synchronous Dynamic Random Access Memory internal memory particle data delay, it is characterized in that: described D step is according to the track lengths of core position decision work clock phase method for position for the every root memory of mensuration, calculate conduction time according to the conduction of current velograph, set clock phase then.

4. a kind of according to claim 1 method that compensates source Synchronous Dynamic Random Access Memory internal memory particle data delay is characterized in that: the Memory Controller Hub that assembles on every mainboard is at least one.