CN102157553B - Structure of asymmetric semiconductor and forming method thereof - Google Patents
Structure of asymmetric semiconductor and forming method thereof Download PDFInfo
- Publication number
- CN102157553B CN102157553B CN201010111063.6A CN201010111063A CN102157553B CN 102157553 B CN102157553 B CN 102157553B CN 201010111063 A CN201010111063 A CN 201010111063A CN 102157553 B CN102157553 B CN 102157553B
- Authority
- CN
- China
- Prior art keywords
- ion implantation
- substrate
- layer
- semiconductor structure
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims description 48
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 238000005468 ion implantation Methods 0.000 claims description 43
- 238000000151 deposition Methods 0.000 claims description 8
- 239000002019 doping agent Substances 0.000 claims description 5
- 229910052735 hafnium Inorganic materials 0.000 claims description 5
- 229910052715 tantalum Inorganic materials 0.000 claims description 5
- 229910052719 titanium Inorganic materials 0.000 claims description 5
- 229910052726 zirconium Inorganic materials 0.000 claims description 5
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 94
- 238000002513 implantation Methods 0.000 description 27
- 239000000463 material Substances 0.000 description 26
- 238000004519 manufacturing process Methods 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 9
- 238000005229 chemical vapour deposition Methods 0.000 description 9
- 150000002500 ions Chemical class 0.000 description 7
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 230000008859 change Effects 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 230000005669 field effect Effects 0.000 description 6
- 239000011229 interlayer Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000010276 construction Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 238000000137 annealing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000007246 mechanism Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000000750 progressive effect Effects 0.000 description 3
- 229910004129 HfSiO Inorganic materials 0.000 description 2
- 229910004166 TaN Inorganic materials 0.000 description 2
- 229910010037 TiAlN Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- VLJQDHDVZJXNQL-UHFFFAOYSA-N 4-methyl-n-(oxomethylidene)benzenesulfonamide Chemical compound CC1=CC=C(S(=O)(=O)N=C=O)C=C1 VLJQDHDVZJXNQL-UHFFFAOYSA-N 0.000 description 1
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical compound CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 description 1
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- -1 HfRu Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 241000849798 Nita Species 0.000 description 1
- 235000003976 Ruta Nutrition 0.000 description 1
- 240000005746 Ruta graveolens Species 0.000 description 1
- 229910004491 TaAlN Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910021340 platinum monosilicide Inorganic materials 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000005297 pyrex Substances 0.000 description 1
- 238000004151 rapid thermal annealing Methods 0.000 description 1
- 235000005806 ruta Nutrition 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明公开了一种非对称半导体结构，包括：衬底；形成在所述衬底上的栅堆叠，所述栅堆叠包括一个或多个栅介质层和栅电极层；形成在所述栅堆叠侧壁的侧墙；以及形成在所述衬底中，位于所述栅堆叠侧壁的源极和漏极；其中所述栅介质层在源极区一侧的等效氧化层厚度相对较低，在漏极区一侧的等效氧化层厚度相对较高。该半导体结构通过例子注入而使栅介质层两端的相对介电常数不同，从而导致源/漏极区单位面积电容不同，EOT不同，本发明可以满足漏极和源极不同的工作需要，最大限度地发挥漏极和源极的效率，从而整体上提高该半导体器件的工作性能。
The invention discloses an asymmetric semiconductor structure, comprising: a substrate; a gate stack formed on the substrate, the gate stack including one or more gate dielectric layers and a gate electrode layer; The sidewall of the sidewall; and the source and drain formed in the substrate and located on the sidewall of the gate stack; wherein the equivalent oxide thickness of the gate dielectric layer on the side of the source region is relatively low , the equivalent oxide thickness on the side of the drain region is relatively high. The semiconductor structure makes the relative dielectric constants at both ends of the gate dielectric layer different through sample injection, thereby causing the source/drain region to have different capacitance per unit area and different EOT. The present invention can meet the different working needs of the drain and the source, and maximize the The efficiencies of the drain and the source are maximized, thereby improving the performance of the semiconductor device as a whole.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly structure of a kind of asymmetrical semiconductor and forming method thereof.
Background technology
At present, FET (Field Effect Transistor, field-effect transistor) be one of the most widely used assembly in integrated circuit, because field effect transistor circuitry can be carried out multiple different function, and the manufacture of field-effect transistor has reproducibility and the predictability of height, its another advantage is that this structure can be made very littlely, and can is closely aligned and install.
Typical field-effect transistor is comprised of substrate, source electrode, drain electrode and a grid that can conduct electricity.Wherein, source electrode and drain electrode are positioned at the both sides of channel region, and grid is separated by grid oxic horizon and channel region.Field-effect transistor grows in the surface of silicon or other Semiconductor substrate, has the doping of the first conductivity type.At substrate surface, generate one deck gate oxide level, normally utilize thermal oxidation technology to generate evenly oxide skin(coating) closely of one deck, its have can be default thickness with can preset and the fixed charge of low degree, follow deposit spathic silicon layer and be etched with formation grid, can utilize in deposition process doping or by diffusion technology, or after deposition, carry out Implantation, give this polysilicon layer conductivity.Conventionally, can above polysilicon layer, generate one deck conductive materials, for example metal or metal silicide are to reduce the resistivity of grid.Take grid as protective layer again, utilize the admixture of the second conductivity type to carry out Implantation to substrate, to make source electrode and drain electrode, this source electrode, drain electrode and channel region are self-aligned to grid.
At present, typical MOSFET (Metal-Oxide-Semiconductor Field-EffectTransistor, metal-oxide layer-semiconductor-field-effect transistor) be all made as the device of grid oxic horizon symmetry, but consider at AC different with the function of source electrode in DC device and drain electrode, so wish to form source electrode and the asymmetric MOSFET structure of drain electrode in practical operation, therefore how making asymmetric MOSFET structure is a problem demanding prompt solution.
Summary of the invention
For the deficiencies in the prior art, the object of the invention is to provide a kind of structure and forming method thereof of asymmetrical semiconductor of favorable working performance.
To achieve these goals, the invention provides a kind of asymmetrical semiconductor structure, comprising: substrate; The grid that are formed on described substrate are stacking, stacking one or more gate dielectric layers and the gate electrode layer of comprising of described grid; Be formed on one or more side walls of the stacking sidewall of described grid; And be formed in described substrate, be positioned at source electrode and the drain electrode of the stacking sidewall of described grid; The equivalent oxide thickness of wherein said gate dielectric layer one side in source area is relatively low, and in drain region, the equivalent oxide thickness of one side is relatively high.
The invention has the beneficial effects as follows, this semiconductor device adopts asymmetrical structure, corresponding with the actual functional capability of drain electrode and source electrode, can bring into play better the function of drain electrode and source electrode, thereby greatly improve on the whole the service behaviour of semiconductor device, not only can reduce the electric capacity of drain electrode, but also can contribute to improve the carrier density of source electrode, and the drive current that improves MOSFET, thereby DC and the AC performance of raising device.
Correspondingly, the present invention also provides a kind of formation method of asymmetrical semiconductor structure, comprises the following steps: a. forms substrate; B. on described substrate, form one or more side walls and source electrode and the drain electrode of the stacking sidewall of stacking, the described grid of pseudo-grid; C. remove described pseudo-grid stacking, to form opening; D. in described opening, form one or more gate dielectric layers, the equivalent oxide thickness of described gate dielectric layer one side in source area is relatively low, and in drain region, the equivalent oxide thickness of one side is relatively high; E. on described gate dielectric layer, form new grid stacking.
According to formation method of the present invention, adopt the ion implantation concentration of change gate dielectric layer to change the EOT at gate dielectric layer two ends, thereby make the EOT at gate dielectric layer two ends not identical, the different operating needs that can adapt to drain electrode and source electrode, therefore, can greatly improve the service behaviour of this semiconductor device, not only can reduce the electric capacity of drain electrode, but also can contribute to improve the carrier density of source electrode, and the drive current that improves MOSFET, thereby DC and the AC performance of raising device.
Accompanying drawing explanation
Above-mentioned and/or the additional aspect of the present invention and advantage will become from the following description of the accompanying drawings of embodiments and obviously and easily understand, wherein:
Fig. 1-4th, according to the schematic diagram in each stage of the asymmetrical semiconductor device of first embodiment of the invention;
Fig. 5-7th, according to the schematic diagram in each stage of the asymmetrical semiconductor device of second embodiment of the invention;
Fig. 8-10th, according to the schematic diagram in each stage of the asymmetrical semiconductor device of third embodiment of the invention; And
Figure 11 is according to the flow chart of the manufacture method of embodiments of the invention asymmetrical semiconductor device.
Embodiment
Describe embodiments of the invention below in detail, the example of described embodiment is shown in the drawings, and wherein same or similar label represents same or similar element or has the element of identical or similar functions from start to finish.Below by the embodiment being described with reference to the drawings, be exemplary, only for explaining the present invention, and can not be interpreted as limitation of the present invention.Disclosing below provides many different embodiment or example to be used for realizing different structure of the present invention.Of the present invention open in order to simplify, hereinafter the parts of specific examples and setting are described.Certainly, they are only example, and object does not lie in restriction the present invention.In addition, the present invention can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and object clearly, itself do not indicate the relation between discussed various embodiment and/or setting.In addition, the various specific technique the invention provides and the example of material, but those of ordinary skills can recognize the property of can be applicable to of other techniques and/or the use of other materials.In addition, First Characteristic described below Second Characteristic it " on " structure can comprise that the first and second Characteristics creations are for the direct embodiment of contact, also can comprise the embodiment of other Characteristics creation between the first and second features, such the first and second features may not be direct contacts.
The present invention is mainly by forming the different gate dielectric layer of equivalent oxide thickness (EOT, Equivalent OxideThick) to reach the object that forms asymmetric MOSFET structure.In addition, in the present invention, can select a side that EOT is relatively high as drain electrode, select a side that EOT is relatively low as source electrode, so not only can reduce the electric capacity of drain electrode, but also can contribute to improve the carrier density of source electrode, and and the drive current that improves MOSFET, thus DC and the AC performance of device improved.
Asymmetrical semiconductor structure proposed by the invention, comprises substrate 101, is formed on grid on described substrate stacking 118, stacking one or more gate dielectric layers 111,112 and the gate electrode layer 114 of comprising of described grid; Be formed on one or more side walls 106 of the stacking sidewall of described grid; And be formed in described substrate, be positioned at source electrode 104 and the drain electrode 102 of the stacking both sides of described grid; The equivalent oxide thickness of wherein said gate dielectric layer 111,112 104 1 sides in source area is relatively low, and in drain region, the equivalent oxide thickness of 102 1 sides is relatively high.
According to the formation method of asymmetrical semiconductor structure of the present invention, utilize grid alternative techniques to carry out the manufacture of semiconductor device, comprise the following steps: form substrate; On described substrate, form one or more side walls and source electrode and the drain electrode of the stacking sidewall of stacking, the described grid of pseudo-grid; Remove described pseudo-grid stacking, to form opening; In described opening, form one or more gate dielectric layers, the equivalent oxide thickness of described gate dielectric layer one side in source area is relatively low, and in drain region, the equivalent oxide thickness of one side is relatively high; On described gate dielectric layer, form new grid stacking.
Described gate dielectric layer can be one deck or multilayer, and in the first and second embodiment, gate dielectric layer is one deck, and it can be the boundary layer 111 on substrate, and described boundary layer 111 can be oxide skin(coating).In the 3rd embodiment, gate dielectric layer can be multilayer, for example, can be boundary layer 111 and high K medium layer 112, and this will be described in detail hereinafter.
the first embodiment
In the present embodiment, can manufacture by the following method asymmetrical semiconductor structure of the present invention.The present invention adopts grid alternative techniques, as shown in figure 11, first according to traditional grid alternative techniques flow manufacturing semiconductor device, in step 101, forms substrate 100.In the present embodiment, substrate 100 comprises the silicon substrate (for example wafer) that is arranged in crystal structure.For example, according to the known designing requirement of prior art (p-type substrate or N-shaped substrate), substrate 100 can comprise various doping configurations.The substrate 100 of other examples can also comprise other basic semiconductors, for example germanium and diamond.Or substrate 100 can comprise compound semiconductor, for example carborundum, GaAs, indium arsenide or indium phosphide.In addition, substrate 100 can comprise epitaxial loayer alternatively, can be by stress changes to strengthen the property, and can comprise silicon-on-insulator (SOI) structure.
In step 102, on described substrate 100, form one or more side walls 106 and the source electrode 104 of the stacking (not shown) of pseudo-grid, the stacking sidewall of described pseudo-grid and drain 102.
Pseudo-grid are stacked as sacrifice layer, can comprise pseudo-gate dielectric layer and dummy gate layer.Described pseudo-gate dielectric layer can be thermal oxide layer, comprises silica, silicon nitride, for example silicon dioxide.Dummy gate layer can be for example polysilicon.In one embodiment, dummy gate layer comprises amorphous silicon.Pseudo-gate dielectric layer and dummy gate layer can be by MOS technical matters, and for example deposition, photoetching, etching and/or other suitable methods form.
Source/drain region 104,102 can, by according to the transistor arrangement of expectation, be injected p-type or N-shaped alloy or impurity and form to substrate 100.Source/drain region 104,102 can be formed by the method that comprises photoetching, Implantation, diffusion and/or other appropriate process.Utilize common semiconducter process and step, described device is carried out to thermal annealing, to activate the doping in source electrode and drain electrode 104,102, thermal annealing can adopt the technique that those skilled in the art such as comprising rapid thermal annealing, spike annealing know to carry out.
Cover the stacking formation side wall 106 of described pseudo-grid.Side wall 106 can be by silicon nitride, silica, silicon oxynitride, carborundum, fluoride-doped silex glass, low K dielectrics material and combination thereof, and/or other suitable materials form.Side wall 106 can have sandwich construction, and side wall has double-decker in the present embodiment, i.e. side wall 106-1 and 106-2.Side wall 106 can be by comprising that the method for the dielectric substance that deposition is suitable forms.Side wall 106 can have one section, and to cover pseudo-grid stacking upper, and the technique that this structure can be known with those skilled in the art obtains.In other embodiments, side wall 106 also can not cover pseudo-grid stacking on.
Especially, can also on described substrate, deposit and form interlayer dielectric layer (ILD) 108, describedly can be but be not limited to silica (as Pyrex, boron-phosphorosilicate glass etc.) and the silicon nitride (Si3N4) such as unadulterated silica (SiO2), doping.Described interlayer dielectric layer 108 can be used methods such as chemical vapour deposition (CVD) (CVD), physical vapour deposition (PVD) (PVD), ald (ALD) and/or other suitable technique to form.Interlayer dielectric layer 108 can have sandwich construction.In one embodiment, the thickness range of interlayer dielectric layer 108 is about 30 to 90 nanometers.
Then, to described interlayer dielectric layer 108 and described side wall 106 planarization to expose the upper surface of described dummy grid.For example can remove described interlayer dielectric layer 108 by chemico-mechanical polishing (CMP) method, until expose the upper surface of described side wall 106.Then more described side wall 106 is carried out to chemico-mechanical polishing or reactive ion etching, thereby remove the upper surface of described side wall 106, thereby expose described dummy gate layer.
Above step is all according to traditional grid alternative techniques flow manufacturing, therefore in order to simplify description of the invention, not shown in figures, but those skilled in the art will be appreciated that, foregoing description is not intended to limit the present invention, the present invention can adopt other techniques that are different from above-mentioned technological process to manufacture, as long as it can be applied in grid alternative techniques.
Then, in step 103, remove described pseudo-grid stacking, to form opening 120.
In step 104, in described opening 120, form one or more gate dielectric layers, the equivalent oxide thickness of described gate dielectric layer 104 1 sides in source area is relatively low, and in drain region, the equivalent oxide thickness of 102 1 sides is relatively high.In the present embodiment, described gate dielectric layer is one deck, and specifically, described gate dielectric layer is boundary layer 111, and it can be oxide skin(coating).Can form as follows described boundary layer 111.As shown in Figure 1, from 120 pairs of substrates of described opening, carry out Implantation to form ion implanted region 110, in source area, 104 1 sides have relatively high ion implantation concentration to described Implantation, in drain region, 102 1 sides have relatively low ion implantation concentration, in Fig. 1, by progressive greyscale pattern, represent the change in concentration of ion implanted region 110, dark relatively high ion implantation concentration, the ion implantation concentration that light color expression is relatively low of representing.This can realize by carrying out angled Implantation from opening, for example can be to become the angle of about 20-60 degree to carry out Implantation to the substrate of opening below with vertical direction, preferably described Implantation is that low energy ion injects, and the degree of depth of described Implantation is preferably and is less than about 5nm.The element of Implantation comprises Hf, Zr, Ti, Ta, La, N, O and combination thereof.The element injecting should have with the material of substrate to be compared and has higher relative dielectric constant, and substrate is silicon substrate in the present embodiment.Then, as shown in Figure 2, carry out heat growth, to form boundary layer 111.Owing to 104 thering is relatively high ion implantation concentration in source area, in drain region, 102 have relatively low ion implantation concentration, therefore in oxygen environment, carry out in the process of heat growth, having compared with macroion implantation concentration is that the side that relative dielectric constant is higher will have higher unit-area capacitance, and formed equivalent oxide thickness also can be relatively little; And have lower ion implantation concentration, be that the side that relative dielectric constant is lower will have lower unit-area capacitance, formed equivalent oxide thickness also can be relatively large.It is the equivalent oxide thickness that the equivalent oxide thickness of source area 104 1 sides will be less than drain region 102 1 sides.
Then in step 105, as shown in Figure 3, Figure 4, on described boundary layer 111, form new grid stacking 118, for example can form high K medium layer 112 and metal gate layers 114.
High K medium layer 112 is high-k (high k) material.In one embodiment, high k material comprises hafnium oxide (HfO
2).The high k material of other examples comprises HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and combination thereof, and/or other suitable materials.High K medium layer 112 can comprise that about 12 dusts are to the thickness between 35 dust scopes.High K medium layer 112 can form by the technique of for example chemical vapour deposition (CVD) (CVD) or ald (ALD).High K medium layer 112 can also have sandwich construction, comprises the more than one layer with above-mentioned material.
On described high K medium layer 112, form metal gate layers 114 afterwards, metal gate material can comprise one or more material layers, and lining for example provides material, gate material and/or other suitable materials of appropriate work function number to grid.For N type semiconductor device, can be from comprising select one or more elements to deposit in the group of column element: TiN, TiAlN, TaAlN, TaN, TaSiN, HfSiN, MoSiN, RuTa
x, NiTa
xand the combination of these materials; For P type semiconductor device, can be from comprising select one or more elements to deposit in the group of column element: TiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi
x, Ni
3si, Pt, Ru, Ir, Mo, HfRu, RuO
xand the combination of these materials.
Finally carry out chemico-mechanical polishing (CMP) technique, to form grid stacking 118.
Like this, high EOT end can help to reduce the electric capacity of drain electrode as drain electrode, and low EOT end can help to increase the carrier density of source electrode as source electrode, also can increase drive current simultaneously.Therefore, this set can increase DC (Direct Current, direct current) and AC (the Alternating Current exchanges) performance of this semiconductor device.
the second embodiment
Below the aspect that is only different from the first embodiment with regard to the second embodiment is set forth.The part of not describing will be understood that with the first embodiment and has adopted identical step, method or technique to carry out, and therefore again repeats no more.According to a second embodiment of the present invention, described gate dielectric layer is one deck, and specifically, described gate dielectric layer is boundary layer 111, and it can be oxide skin(coating).Can form described boundary layer 111 by following alternative steps.Step 101-103 is the step identical with the first embodiment, as shown in Figure 5, first device is carried out to heat growth, to form boundary layer 111 in the substrate 100 below opening after step 103.Then in step 104, as shown in Figure 6, from 120 pairs of boundary layers of described opening 111, carry out Implantation dopant is injected to boundary layer 111, in source area, 104 1 sides have relatively high ion implantation concentration to described Implantation, in drain region, 102 1 sides have relatively low ion implantation concentration, in Fig. 6, by progressive greyscale pattern, represent the change in concentration of boundary layer 111, dark relatively high ion implantation concentration, the ion implantation concentration that light color expression is relatively low of representing.This can realize by carrying out angled Implantation from opening, for example can be to become the angle of about 20-60 degree to carry out Implantation to the boundary layer 111 of opening below with vertical direction, and preferably described Implantation is that low energy ion injects.The element of Implantation comprises Hf, Zr, Ti, Ta, La, N, O and combination thereof.The element injecting should have with the material of substrate 100 to be compared and has higher relative dielectric constant, and boundary layer is oxide skin(coating) in the present embodiment.Then, can selectively the anneal dopant that injects with active ions repair the defect that Implantation is caused.Owing to 104 thering is relatively high ion implantation concentration in source area, in drain region, 102 have relatively low ion implantation concentration, therefore, having compared with macroion implantation concentration is that the side that relative dielectric constant is higher will have higher unit-area capacitance, and formed equivalent oxide thickness also can be relatively little; And have lower ion implantation concentration, be that the side that relative dielectric constant is lower will have lower unit-area capacitance, formed equivalent oxide thickness also can be relatively large.It is the equivalent oxide thickness that the equivalent oxide thickness of source area 104 1 sides will be less than drain region 102 1 sides.
Then with the first embodiment in the same manner, in step 105, as shown in Figure 7, on described boundary layer 111, form new high K medium layer 112 and metal gate layers 114, to form grid stacking 118.
the 3rd embodiment
Below the aspect that is only different from the first embodiment with regard to the 3rd embodiment is set forth.The part of not describing will be understood that with the first embodiment and has adopted identical step, method or technique to carry out, and therefore again repeats no more.In a third embodiment in accordance with the invention, described gate dielectric layer is two-layer, and specifically, described gate dielectric layer is boundary layer 111 and high K medium layer 112.Can form gate dielectric layer by following alternative steps.Step 101-103 is the step identical with the first embodiment, as shown in Figure 8, first device is carried out to heat growth, to form boundary layer 111 in the substrate 100 below opening after step 103.And depositing high K medium layer 112 on described boundary layer 111, high K medium layer 112 is high-k (high k) material.In one embodiment, high k material comprises hafnium oxide (HfO
2).The high k material of other examples comprises HfSiO, HfSiON, HfTaO, HfTiO, HfZrO and combination thereof, and/or other suitable materials.High K medium layer 112 can form by the technique of for example chemical vapour deposition (CVD) (CVD) or ald (ALD).Then in step 104, as shown in Figure 9, from 120 pairs of high K medium layers of described opening 112, carry out Implantation dopant is injected to the boundary layer 111 of high K medium layer 112 below, in source area, 104 1 sides have relatively high ion implantation concentration to described Implantation, in drain region, 102 1 sides have relatively low ion implantation concentration, in Fig. 9, by progressive greyscale pattern, represent the change in concentration of boundary layer 111, dark relatively high ion implantation concentration, the ion implantation concentration that light color expression is relatively low of representing.This can realize by carrying out angled Implantation from opening, for example can be to become the angle of about 20-60 degree to carry out Implantation to the substrate of opening below with vertical direction, and preferably described Implantation is that low energy ion injects.The element of Implantation comprises Hf, Zr, Ti, Ta, La, N, O and combination thereof.The element injecting should have with the material of substrate 100 to be compared and has higher relative dielectric constant.Then, can selectively the anneal dopant that injects with active ions repair the defect that Implantation is caused.Owing to 104 thering is relatively high ion implantation concentration in source area, in drain region, 102 have relatively low ion implantation concentration, therefore, having compared with macroion implantation concentration is that the side that relative dielectric constant is higher will have higher unit-area capacitance, and formed equivalent oxide thickness also can be relatively little; And have lower ion implantation concentration, be that the side that relative dielectric constant is lower will have lower unit-area capacitance, formed equivalent oxide thickness also can be relatively large.It is the equivalent oxide thickness that the equivalent oxide thickness of source area 104 1 sides will be less than drain region 102 1 sides.
Then with the first embodiment in the same manner, in step 105, as shown in figure 10, on described high K medium layer 112, form new metal gate layers 114, to form grid stacking 118.
Therefore, gate dielectric layer can be the common sandwich construction forming of oxide skin(coating), high K dielectric layer or two media layer.The gate dielectric layer from one end to the other side gradually changing for EOT, can select one end that EOT is relatively high as drain electrode, and selects one end that EOT is relatively low as source electrode.Like this, high EOT end can help to reduce the electric capacity of drain electrode as drain electrode, and low EOT end can help to increase the carrier density of source electrode as source electrode, also can increase drive current simultaneously.Therefore, this set can increase DC (Direct Current, direct current) and AC (AlternatingCurrent exchanges) performance of this semiconductor device.
Although describe in detail about example embodiment and advantage thereof, be to be understood that in the situation that do not depart from the protection range that spirit of the present invention and claims limit, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should easily understand within keeping protection range of the present invention, the order of processing step can change.
In addition, range of application of the present invention is not limited to technique, mechanism, manufacture, material composition, means, method and the step of the specific embodiment of describing in specification.From disclosure of the present invention, as those of ordinary skill in the art, will easily understand, for the technique, mechanism, manufacture, material composition, means, method or the step that have existed or be about to develop at present later, wherein they carry out identical function or the identical result of acquisition cardinal principle of corresponding embodiment cardinal principle of describing with the present invention, according to the present invention, can apply them.Therefore, claims of the present invention are intended to these technique, mechanism, manufacture, material composition, means, method or step to be included in its protection range.
Claims (13)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010111063.6A CN102157553B (en) | 2010-02-11 | 2010-02-11 | Structure of asymmetric semiconductor and forming method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010111063.6A CN102157553B (en) | 2010-02-11 | 2010-02-11 | Structure of asymmetric semiconductor and forming method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102157553A CN102157553A (en) | 2011-08-17 |
| CN102157553B true CN102157553B (en) | 2014-02-12 |
Family
ID=44438888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201010111063.6A Active CN102157553B (en) | 2010-02-11 | 2010-02-11 | Structure of asymmetric semiconductor and forming method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102157553B (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103187278B (en) * | 2011-12-28 | 2016-04-27 | 北大方正集团有限公司 | A kind of manufacture method of metal-oxide-semiconductor and a kind of metal-oxide-semiconductor |
| CN106876274A (en) * | 2015-12-11 | 2017-06-20 | 中芯国际集成电路制造(上海)有限公司 | The forming method of transistor |
| CN108122760B (en) * | 2016-11-30 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| EP3671860A1 (en) * | 2018-12-20 | 2020-06-24 | Infineon Technologies Austria AG | Semiconductor transistor device and method of manufacturing the same |
| CN113644111B (en) * | 2020-05-11 | 2022-07-15 | 北京华碳元芯电子科技有限责任公司 | Transistor and method of making the same |
| CN115084245B (en) * | 2022-07-25 | 2023-01-17 | 北京芯可鉴科技有限公司 | LDMOS device and its preparation method and chip |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7064399B2 (en) * | 2000-09-15 | 2006-06-20 | Texas Instruments Incorporated | Advanced CMOS using super steep retrograde wells |
| US6686245B1 (en) * | 2002-12-20 | 2004-02-03 | Motorola, Inc. | Vertical MOSFET with asymmetric gate structure |
| US20080111185A1 (en) * | 2006-11-13 | 2008-05-15 | International Business Machines Corporation | Asymmetric multi-gated transistor and method for forming |
| US7829945B2 (en) * | 2007-10-26 | 2010-11-09 | International Business Machines Corporation | Lateral diffusion field effect transistor with asymmetric gate dielectric profile |
-
2010
- 2010-02-11 CN CN201010111063.6A patent/CN102157553B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN102157553A (en) | 2011-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9166020B2 (en) | Metal gate structure and manufacturing method thereof | |
| CN103311247B (en) | Semiconductor device and method for manufacturing the same | |
| CN102129978B (en) | Method for forming semiconductor element | |
| US8329566B2 (en) | Method of manufacturing a high-performance semiconductor device | |
| US8420490B2 (en) | High-performance semiconductor device and method of manufacturing the same | |
| CN100345265C (en) | Structure and method for silicided metal gate transistors | |
| US20120112249A1 (en) | High performance semiconductor device and method of fabricating the same | |
| US20120273901A1 (en) | Semiconductor device and method for manufacturing the same | |
| WO2014082332A1 (en) | Manufacturing method of semiconductor device | |
| CN102157553B (en) | Structure of asymmetric semiconductor and forming method thereof | |
| WO2013026243A1 (en) | Semiconductor structure and manufacturing method thereof | |
| CN102148252A (en) | Device and method for manufacturing semiconductor element | |
| CN105321883A (en) | Method for fabricating semiconductor device | |
| WO2011124061A1 (en) | Semiconductor device and method for fabricating the same | |
| WO2014082341A1 (en) | Method for manufacturing p-type mosfet | |
| US9634116B2 (en) | Method to improve reliability of high-K metal gate stacks | |
| CN102237277B (en) | Semiconductor device and method of forming the same | |
| WO2014082333A1 (en) | Manufacturing method of n-type mosfet | |
| CN102254824B (en) | Semiconductor device and method of forming the same | |
| CN118658780B (en) | Manufacturing method of semiconductor device | |
| CN203134802U (en) | Semiconductor structure | |
| CN102683397B (en) | Metal gate structure and fabrication method thereof | |
| CN102214688A (en) | High-speed transistor structure and manufacturing method thereof | |
| CN104900502A (en) | Gate dielectric layer forming method and MOS transistor forming method | |
| CN110534419B (en) | A kind of semiconductor device and its manufacturing method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Co-patentee after: BEIJING NAURA MICROELECTRONICS EQUIPMENT Co.,Ltd. Patentee after: Institute of Microelectronics of the Chinese Academy of Sciences Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Co-patentee before: BEIJING NMC Co.,Ltd. Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20190215 Address after: No. 8, Wenchang Avenue, Beijing economic and Technological Development Zone, 100176 Patentee after: BEIJING NAURA MICROELECTRONICS EQUIPMENT Co.,Ltd. Address before: No. 3, North Tu Cheng West Road, Chaoyang District, Beijing Co-patentee before: BEIJING NAURA MICROELECTRONICS EQUIPMENT Co.,Ltd. Patentee before: Institute of Microelectronics of the Chinese Academy of Sciences |