CN102152413A - Wafer processing method - Google Patents

Abstract

The present invention provides a wafer processing method capable of removing the degenerated layer on the side surface without causing cracks on the periphery of individual devices. The wafer processing method includes the following steps: a wafer grinding step of grinding the back surface of the wafer to form the thickness of the wafer to a predetermined thickness; The transmissive laser light forms a metamorphic layer along the interval road inside the wafer at a depth below the surface of the wafer, and the depth is greater than the finished thickness of the device; the wafer dividing process applies an external force to the wafer along the interval where the metamorphic layer is formed. The process of dividing the wafer into individual devices; and the degenerated layer removal process, which grinds the back of the wafer to form the wafer into the finished thickness of the device, thereby removing the degenerated layer. The degenerated layer is removed by using vitrified bonding Grinding tools formed of diamond abrasive grains with a particle size of 0.5 μm to 7 μm are used.

Description

Wafer processing method

technical field

The present invention relates to a processing method for dividing a wafer into individual devices along a spacer. The surface of the wafer is divided into a plurality of regions by the spacer formed in a grid pattern, and a plurality of regions are formed in the plurality of regions. device.

Background technique

In the manufacturing process of a semiconductor device, a plurality of regions are divided on the surface of a roughly disc-shaped semiconductor wafer by dividing lines called streets arranged in a grid pattern, and ICs are formed in the divided regions ( Integrated Circuit: Integrated Circuit), LSI (Large Scale Integration: Large Scale Integrated Circuit) and other devices. Then, the devices are manufactured individually by cutting the semiconductor wafer along the lanes to divide the regions where the devices are formed. In addition, an optical device wafer in which gallium nitride-based compound semiconductors and the like are stacked on the surface of a sapphire substrate or a silicon carbide substrate is also divided into individual optical devices such as light-emitting diodes and laser diodes by cutting along the streets, and Widely used in electrical equipment.

As a method of dividing a wafer along the lanes, a laser processing method has been attempted in which a pulsed laser beam is used which is transparent to the wafer and irradiated with the pulsed laser beam so that the focal point is aligned with the inside of the region to be divided. In the division method using this laser processing method, a pulsed laser beam having a wavelength that is transmissive to the wafer is irradiated along the interval track from one surface side of the wafer with a focus point aligned with the inside of the wafer. Wavelength, so that a degenerated layer is continuously formed inside the wafer along the lanes, and an external force is applied along the lanes whose strength is reduced by the formation of the degenerated layer, thereby dividing the wafer into individual devices (for example, refer to Patent Document 1) .

However, since a degenerated layer remains on the side surfaces of individual devices divided by the dividing method described in Patent Document 1, there is a problem that the bending strength of the device is lowered and the quality of the device is lowered. In particular, in an optical device, if a degraded layer remains on the side surface, there is a problem that light emitted from the optical device is absorbed by the degraded portion, resulting in a decrease in luminance.

In order to solve this problem, a method of processing a wafer has been proposed in which a laser beam having a transmittance with respect to the wafer is irradiated along the lanes, thereby forming a degenerated layer of a predetermined thickness from the back surface of the wafer, and forming After dividing the wafer by the spacer of the degenerated layer, the back surface of the wafer is ground to remove the degenerated layer (for example, refer to Patent Document 2).

Patent Document 1: Japanese Patent No. 3408805

Patent Document 2: Japanese Patent Laid-Open No. 2005-86161

If the backside of the wafer that has been divided into individual devices is ground with a grinding tool as in the wafer processing method disclosed in the above-mentioned Patent Document 2, there will be an impact force due to the grinding tool acting on the periphery of the device after the division. As a result, cracks are generated on the peripheral edge of the device to damage the device. In addition, the same problem also arises in the case where a wafer of a predetermined thickness is formed from the back surface of the wafer by irradiating the wafer formed of quartz with laser light having a wavelength that is transparent to the wafer along the lanes as described above. For the degenerated layer, after dividing the wafer along the lanes in which the degenerated layer was formed, the back surface of the wafer is ground to remove the degenerated layer, thereby manufacturing a cover glass (cover glass).

Contents of the invention

The present invention was made in view of the above facts, and the main technical object of the present invention is to provide a wafer processing method capable of removing the degenerated layer on the side surface without causing cracks on the periphery of individual devices.

In order to solve the above-mentioned main technical problems, according to the present invention, a wafer processing method is provided. In the wafer processing method, the wafer is divided along the lanes, and the surface of the wafer is divided by the lanes formed in a grid pattern. a plurality of regions, and devices are formed in the plurality of regions, the processing method of the wafer is characterized in that the processing method of the wafer includes the following steps: a wafer grinding step, in the wafer grinding step, the Grinding the back surface of the wafer so that the thickness of the wafer is formed to a predetermined thickness; a modified layer forming step, in which the modified layer is formed from the back side of the wafer after the wafer grinding step is carried out along the spacer lane irradiating laser light having transmissibility with respect to the wafer to form a metamorphic layer along the spacer lanes inside the wafer at a depth greater than the finished thickness of the device from the surface of the wafer; a wafer dividing process, in which the wafer dividing process, applying an external force to the wafer after the degenerated layer forming process, dividing the wafer into individual devices along the partition lanes in which the degenerated layer is formed; Grinding the back surface of the wafer after the wafer splitting step to form the wafer into the finished thickness of the device, thereby removing the altered layer. The altered layer removal step is implemented using the following grinding tool: the grinding tool It is formed by fixing diamond abrasive grains with a particle diameter of 0.5 μm to 7 μm with a vitrified bond.

In the present invention, the altered layer removal step is carried out using a grinding tool formed by fixing diamond abrasive grains with a particle diameter of 0.5 μm to 7 μm with a vitrified bond, wherein In the degenerated layer removal step, the back surface of the wafer subjected to the division process is ground to form the wafer into the finished thickness of the device, thereby removing the degenerated layer. Therefore, even if the wafer is divided into individual devices, since the impact force of the grinding tool on the periphery of the divided devices is small, cracks will not occur in the devices.

Description of drawings

FIG. 1 is a perspective view showing a semiconductor wafer as a wafer and an enlarged sectional view of main parts.

FIG. 2 is a perspective view showing a state where the surface of the semiconductor wafer shown in FIG. 1 is attached to a dicing tape attached to a ring frame.

3 is an explanatory diagram of a wafer grinding step in the wafer processing method according to the present invention.

4 is a perspective view of main parts of a laser processing apparatus for performing a modified layer forming step in the wafer processing method according to the present invention.

5 is an explanatory diagram of a modified layer forming step in the method of processing an optical device wafer according to the present invention.

6 is a perspective view of a dividing apparatus for performing a wafer dividing step in the wafer processing method according to the present invention.

7 is an explanatory diagram of a wafer dividing step in the wafer processing method according to the present invention.

8 is an explanatory diagram of a modified layer removal step in the wafer processing method according to the present invention.

9 is an enlarged cross-sectional view showing a main part of a semiconductor wafer after performing a modified layer removal step in the wafer processing method according to the present invention.

10 is an explanatory diagram of a wafer transfer step in the wafer processing method according to the present invention.

11 is a perspective view of a pick-up device for performing a pick-up step in the wafer processing method according to the present invention.

12 is an explanatory diagram of a pick-up step in the wafer processing method according to the present invention.

Label description

2: semiconductor wafer; 20: silicon substrate; 21: device layer; 3: grinding device; 31: chuck table of grinding device; 32: grinding wheel; 321: grinding tool; 4: laser processing device; 41 : chuck table of laser processing device; 42: laser beam irradiation member; 5: wafer dividing device; 56: tension applying member; 7: pickup device; F: ring frame; T: dicing tape.

Detailed ways

Hereinafter, preferred embodiments of the wafer processing method according to the present invention will be described in detail with reference to the drawings.

1 shows a perspective view of a semiconductor wafer as a wafer processed by a wafer processing method according to the present invention, and an enlarged cross-sectional view showing a main part of the wafer. The semiconductor wafer 2 shown in (a) and (b) of FIG. 1 is composed of a silicon wafer, and for example, a plurality of devices 22 such as ICs and LSIs are formed in a matrix using a device layer 21 on the surface of a silicon substrate 20 with a thickness of 600 μm. , the device layer 21 is formed by stacking an insulating film and a functional film for forming a circuit. And, each device 22 is partitioned by a partition 23 formed in a lattice shape. The device layer 21 is formed to have a thickness of, for example, 10 μm. Hereinafter, a processing method for dividing the semiconductor wafer 2 into individual devices 22 along the streets 23 will be described.

First, in order to protect the devices formed on the surface of the semiconductor wafer, a protective member affixing step of affixing a protective member to the surface of the semiconductor wafer is performed. That is, as shown in FIG. 2 , the surface 2 a of the semiconductor wafer 2 is attached to the surface of a dicing tape T as a protective member attached to an annular frame F formed of a metal material. In addition, in the illustrated embodiment, the above-mentioned dicing tape T is formed by coating acrylic resin paste with a thickness of about 5 μm on the surface of a sheet-shaped base material made of polyvinyl chloride (PVC) with a thickness of 100 μm. . As this paste, a paste having a property of lowering the adhesive force by irradiation with ultraviolet rays is used.

After the surface 2a of the semiconductor wafer 2 is attached to the dicing tape T mounted on the ring frame F by carrying out the above-mentioned protective member attaching process, the back surface of the wafer is ground to make the thickness of the wafer a predetermined thickness. Wafer grinding process. This wafer grinding step is implemented using the grinding apparatus 3 shown in FIG. 3 . The grinding device 3 shown in FIG. 3 is provided with a chuck table 31 for holding a workpiece, and a grinding wheel 32 for holding a workpiece held on the chuck table 31. A grinding wheel 321 for grinding a workpiece. In addition, the central part of the chuck table 31 for holding the workpiece is formed to be high, and the outer peripheral part is formed to be lower than the central part. Moreover, the grinding stone 321 used the grinding stone formed by fixing the diamond abrasive grain whose particle diameter is 40 micrometers - 50 micrometers, and a concentration degree to 50 with a vitrified bond. When the above-mentioned wafer grinding process is carried out using the grinding device 3 configured in this way, as shown in FIG. 31, and the ring frame F is placed on the outer peripheral portion of the chuck table 31, and the semiconductor wafer 2 and the ring frame F are sucked and held on the chuck table 31 by operating a suction member (not shown). Therefore, with respect to the semiconductor wafer 2 held on the chuck table 31 , the back surface 20 b of the silicon substrate 20 is located on the upper side. After the semiconductor wafer 2 is sucked and held on the chuck table 31 in this way, the chuck table 31 is rotated at a speed of, for example, 300 rpm in the direction shown by the arrow 31a, while the grinding wheel 32 is rotated toward the direction shown by the arrow 32a. Rotate in the direction of for example 6000rpm, and make grinding wheel 32 contact with the back surface 20b of the silicon substrate 20 that constitutes semiconductor wafer 2, and make grinding wheel 32 toward the direction shown by arrow 32b with the grinding feed speed of for example 3 μm/second A grinding feed of, for example, 410 μm is performed. As a result, the back surface 20b of the silicon substrate 20 is ground, and the semiconductor wafer 2 is formed to a predetermined thickness (200 μm in the illustrated embodiment).

After the above-mentioned wafer grinding step is carried out, a modified layer forming step is carried out. In the modified layer forming step, a laser beam which is transmissive to the wafer is irradiated from the back side of the wafer along the lanes, and the wafer is formed along the lanes. The interior of the metamorphic layer is formed at a depth from the surface of the wafer that is greater than the finished thickness of the device. This modified layer forming step is carried out using the laser processing device 4 shown in FIG. 4 . The laser processing device 4 shown in FIG. 4 is equipped with: a chuck table 41, which is used to hold the workpiece; The workpiece on the table 41 is irradiated with laser light; and the imaging means 43 is used to image the workpiece held on the chuck table 41 . The chuck table 41 is configured to attract and hold the workpiece, and the chuck table 41 is moved in the processing feeding direction shown by the arrow X in FIG. The index feed member shown moves the chuck table 41 along the index feed direction shown by arrow Y in FIG. 4 .

The above-mentioned laser beam irradiation member 42 includes a cylindrical housing 421 arranged substantially horizontally. A pulsed laser beam oscillating unit (not shown) including a pulsed laser beam oscillator and a repetition rate setting unit is arranged in the casing 421 . A concentrator 422 for concentrating the pulsed laser beam oscillated from the pulsed laser beam oscillating member is attached to the end portion of the housing 421 . In addition, the laser beam irradiation unit 42 includes a condensed point position adjustment unit (not shown) for adjusting the condensed point position of the pulsed laser beam condensed by the condenser 422 .

An imaging unit 43 for imaging the processing area of the workpiece held on the chuck table 41 is disposed at the end portion of the casing 421 constituting the laser beam irradiation unit 42 . In the illustrated embodiment, the imaging component 43 includes, in addition to a common imaging device (CCD) that utilizes visible light for imaging, the following components: an infrared illuminating component, which is used to monitor the workpiece Irradiating infrared rays; an optical system for capturing infrared rays irradiated by the infrared lighting member; and an imaging element (infrared ray CCD) for outputting electrical signals corresponding to the infrared rays captured by the optical system, This imaging means 43 transmits the imaged image signal to the control means mentioned later.

4 and 5, the modified layer forming process will be described. In the modified layer forming process, the above-mentioned laser processing device 4 is used to position the focused spot in the inside of the silicon substrate 20, from the back surface 20b side of the silicon substrate 20. A laser beam having a wavelength that is transparent to the silicon substrate 20 constituting the above-mentioned semiconductor wafer 2 is irradiated onto the partition 23, thereby forming a metamorphic layer at the following depth from the surface of the semiconductor wafer 2 inside the silicon substrate 20. layer, the depth is greater than the finished thickness of the device.

First, the dicing tape T side to which the semiconductor wafer 2 is pasted is placed on the chuck table 41 of the laser processing apparatus 4 shown in FIG. 4 described above. Then, the semiconductor wafer 2 is held on the chuck table 41 via the dicing tape T by operating a suction member (not shown) (wafer holding step). Therefore, with respect to the semiconductor wafer 2 held on the chuck table 41 , the back surface 20 b of the silicon substrate 20 is located on the upper side. In addition, in FIG. 4 , the ring frame F to which the dicing tape T is mounted is omitted, but the ring frame F is held by an appropriate frame holding member arranged on the chuck table 41 . The chuck table 41 on which the optical device wafer 2 is sucked and held in this way is positioned directly below the imaging member 43 by a process feeding member not shown.

When the chuck table 41 is positioned directly below the imaging member 43 , the imaging member 43 and a control unit not shown are used to perform a calibration operation for detecting a processing area of the wafer 2 to be laser processed. That is, the imaging means 43 and the control means (not shown) perform image processing such as pattern matching for performing the lanes 23 formed in a predetermined direction of the semiconductor wafer 2 and the irradiation along the lanes 23. The positions of the laser beams between the condensers 422 of the laser beam irradiation member 42 are aligned, thereby completing the alignment of the laser beam irradiation positions (calibration process). In addition, alignment of the irradiation position of the laser light is similarly performed for the streets 23 formed on the semiconductor wafer 2 in a direction perpendicular to the above-mentioned predetermined direction. At this time, although the surface of the device layer 21 on which the streets 23 are formed in the semiconductor wafer 2 is located on the lower side, since the imaging member 43 is equipped with an infrared illuminating member, an optical system for capturing infrared rays, and a An imaging device such as an imaging device (infrared CCD) that outputs electrical signals corresponding to infrared rays can image the lanes 23 through the back surface 20 b of the silicon substrate 20 .

The semiconductor wafer 2 held on the chuck table 41 has a device layer 21. After detecting the spacer 23 formed on the surface of the device layer 21 in the above-mentioned manner, and performing calibration of the irradiation position of the laser light, as Shown in (a) of Fig. 5, the chuck table 41 is moved to the laser beam irradiation area where the light collector 422 of the laser beam irradiation member 42 is located, and an end of the predetermined spaced road 23 (in Fig. 5 (a) ) is the left end) is positioned directly below the concentrator 422 of the laser light irradiation member 42 . Then, the converging point P of the pulsed laser beam irradiated from the concentrator 422 is aligned at a position above, for example, 80 μm from the surface 2 a (lower surface) of the semiconductor wafer 2 . In order to position the converging point P of the pulsed laser light irradiated from the concentrator 422 at a predetermined position on the semiconductor wafer 2, for example, a method for holding on a chuck stage described in JP 2009-63446 A is used. The height position detection device that detects the height position of the processed object detects the height position of the upper surface of the semiconductor wafer 2 held on the chuck table 41, and uses the detected position of the upper surface of the semiconductor wafer 2 as a reference. The focusing point P of the pulsed laser light is positioned at a predetermined position by operating an unillustrated focusing point position adjustment member. Next, while irradiating pulsed laser light with a wavelength that is transparent to the silicon substrate 20 constituting the semiconductor wafer 2 from the concentrator 422, the chuck table 41 is directed toward the direction indicated by the arrow X1 in FIG. 5(a). Direction moves at a predetermined machining feed rate. Then, as shown in (b) of FIG. 5 , when the irradiation position of the light collector 422 of the laser beam irradiation member 42 reaches the position of the other end (right end in (b) of FIG. 5 ) of the interval road 23, stop The pulsed laser light is irradiated, and the movement of the chuck table 41 is stopped. As a result, as shown in FIG. 5( b ) and FIG. 5( c ), a continuous altered layer 210 is formed along the streets 23 inside the silicon substrate 20 constituting the semiconductor wafer 2 (altered layer forming step). This altered layer 210 is formed in the silicon substrate 20 at a position from the surface 2 a of the semiconductor wafer 2 at a depth greater than the finished thickness of the device (for example, 20 μm). The aforementioned altered layer forming step is performed along all the streets 23 formed on the semiconductor wafer 2 .

The processing conditions in the above-mentioned altered layer forming step are set as follows, for example.

Light source: LD excites Q-switched Nd:YVO4 laser

Wavelength : 1064nm

Repetition frequency : 80kHz

Pulse Width : 120ns

Average output : 1.2W

Spot diameter:

Processing feed speed : 100mm/sec

By performing the above-mentioned modified layer forming step under the above-mentioned processing conditions, the modified layer 210 can be formed with a depth of about 100 μm in the vertical direction centering on the converging point P of the pulsed laser beam. Therefore, by performing the above-mentioned altered layer forming process, an altered layer 210 having a depth of about 100 μm is formed toward the back surface 20 b (upper surface) side of the silicon substrate 20 from a position 30 μm away from the front surface 2 a (lower surface) of the semiconductor wafer 2 . . That is, metamorphic layer 210 is formed along street 23 inside silicon substrate 20 at a depth greater than the finished thickness of the device (for example, 20 μm) from surface 2 a of semiconductor wafer 2 . In this way, since the modified layer forming step is carried out in a thick state (for example, 200 μm) before the modified layer removing step, the converging point P of the pulsed laser beam can be easily positioned at a desired position without causing damage to the device layer 21. In the case of damage, the altered layer 210 is formed, wherein in the altered layer removal process, the back surface of the silicon substrate 20 constituting the semiconductor wafer 2 is ground as described later, thereby forming the wafer into a finished thickness of the device (for example, 20 μm ), thereby removing the degenerated layer.

After performing the modified layer forming step above, a dividing step is performed. In the dividing step, an external force is applied to the wafer after the modified layer forming step, and the wafer is divided into individual devices along the lanes formed with the modified layer. This wafer dividing step is carried out using the wafer dividing apparatus 5 shown in FIG. 6 . The wafer dividing apparatus 5 shown in FIG. 6 includes a base 51 and a moving table 52 which is disposed on the base 51 so as to be movable in a direction indicated by an arrow Y. As shown in FIG. The base 51 is formed in a rectangular shape, and two guide rails 511 and 512 are arranged parallel to each other along the direction indicated by the arrow Y on the upper surfaces of both sides. The mobile table 52 is movably arranged on these two guide rails 511 and 512 . The moving table 52 is moved in the direction indicated by the arrow Y by the moving member 53 . A frame holding member 54 for holding the above-mentioned ring frame F is disposed on the movable table 52 . The frame holding member 54 has: a cylindrical main body 541; an annular frame holding member 542 provided on the upper end of the main body 541; 543. The frame holding member 54 configured in this way fixes the ring-shaped frame F placed on the frame holding member 542 with the clamp 543 . Furthermore, the wafer dividing apparatus 5 shown in FIG. 6 includes a rotating member 55 for rotating the above-mentioned frame holding member 54 . The rotating member 55 has: a pulse motor 551 disposed on the moving table 52; a pulley 552 mounted on the rotating shaft of the pulse motor 551; and an endless belt 553. The belt 553 is wound around the pulley 552 and the cylindrical main body 541 . The rotating member 55 configured in this way rotates the frame holding member 54 via the pulley 552 and the endless belt 553 by driving the pulse motor 551 .

The wafer dividing apparatus 5 shown in FIG. 6 is provided with a tension applying member 56 for acting a tensile force on the semiconductor wafer 2 passing through the dicing tape T in a direction perpendicular to the partition lane 23. It is supported by the ring-shaped frame F, and this ring-shaped frame F is held by the above-mentioned ring-shaped frame holding member 542 . The tension applying member 56 is arranged in the ring-shaped frame holding member 542 . The tension applying member 56 includes a first suction and holding member 561 and a second suction and holding member 562 that are long in a direction perpendicular to the arrow Y direction. The rectangular retaining surface. A plurality of suction holes 561 a are formed in the first suction holding member 561 , and a plurality of suction holes 562 a are formed in the second suction holding member 562 . The plurality of suction holes 561a and 562a communicate with a suction member not shown. In addition, the first suction holding member 561 and the second suction holding member 562 are respectively moved in the arrow Y direction by a moving member not shown.

The wafer dividing device 5 shown in FIG. 6 is equipped with a detection member 57 for detecting the partition lanes 23 of the semiconductor wafer 2 supported on the ring-shaped frame F via the dicing tape T, and the ring-shaped The frame F is held by the above-mentioned annular frame holding member 542 . The detection member 57 is attached to an L-shaped support column 571 disposed on the base 51 . The detecting member 57 is constituted by an optical system, an imaging device (CCD), and the like, and is arranged at a position above the tension applying member 56 . The detection means 57 configured in this way takes an image of the partition lane 23 of the semiconductor wafer 2 supported by the ring frame via the dicing tape T, and converts it into an electrical signal and sends it to a control means not shown in the figure. F, and the ring-shaped frame F is held by the above-mentioned ring-shaped frame holding member 542 .

Wafer breaking performed using the above-described wafer dividing apparatus 5 will be described with reference to FIG. 7 .

As shown in FIG. This is fixed to the frame holding member 542 . Next, the moving member 53 is operated so that the moving table 52 moves in the direction shown by the arrow Y (refer to FIG. 6 ), and a space formed on the semiconductor wafer 2 along a predetermined direction will be formed as shown in (a) of FIG. 7 . The lane 23 (the leftmost spaced lane in the illustrated embodiment) is positioned between the holding surface of the first suction holding part 561 and the holding surface of the second suction holding part 562 constituting the tension applying member 56 . At this time, the partition lane 23 is imaged by the detection member 57, and the holding surface of the first suction holding member 561 and the holding surface of the second suction holding member 562 are aligned. After positioning a partition road 23 in this way between the holding surface of the first suction holding part 561 and the holding surface of the second suction holding part 562, the suction member not shown is operated, thereby making the suction hole 561a and the suction hole 561a 562a applies negative pressure, whereby the semiconductor wafer 2 is sucked and held on the holding surface of the first suction holding member 561 and the holding surface of the second suction holding member 562 via the dicing tape T (holding process).

After carrying out the above-mentioned holding process, the moving member (not shown) constituting the tension applying member 56 is operated to make the first suction holding member 561 and the second suction holding member 562 move away from each other as shown in FIG. 7( b ). direction to move. As a result, a tensile force acts on the lanes 23 positioned between the holding surface of the first suction holding member 561 and the holding surface of the second suction holding member 562 in a direction perpendicular to the lanes 23, whereby the semiconductor wafer 2 Fracture is performed along the streets 23 with the altered layer 210 formed on the silicon substrate 20 as the starting point of fracture (wafer dividing step). By performing this wafer dividing step, the dicing tape T is slightly elongated. In this wafer splitting process, since the semiconductor wafer 2 forms the degenerated layer 210 along the partition road 23 and the strength decreases, the first suction and holding member 561 and the second suction and holding member 562 are moved about 0.5 mm away from each other. Therefore, the semiconductor wafer 2 can be fractured along the spacer 23 with the altered layer 210 formed on the silicon substrate 20 as a fracture starting point.

After performing the wafer dividing process of fracturing along one lane 23 formed in a predetermined direction as described above, the suction and holding of the semiconductor wafer 2 by the first suction holding member 561 and the second suction holding member 562 described above is released. Next, the moving member 53 is actuated to move the moving table 52 in the direction indicated by the arrow Y (see FIG. 6 ) by an amount corresponding to the distance between the lanes 23, and the lanes 23 that have been subjected to the wafer dividing process described above are moved. The adjacent partition lanes 23 are positioned between the holding surface of the first suction holding part 561 and the holding surface of the second suction holding part 562 constituting the tension applying member 56 . Then, the above-mentioned holding step and wafer dividing step are carried out.

After the above-mentioned holding process and wafer dividing process are performed on all the lanes 23 formed in the predetermined direction as described above, the rotating member 55 is operated to rotate the frame holding member 54 by 90 degrees. As a result, the semiconductor wafer 2 held by the frame holding member 542 of the frame holding member 54 is also rotated by 90 degrees, so that the street 23 formed in a direction perpendicular to the street 23 formed in a predetermined direction and subjected to the above-mentioned wafer dividing process , are positioned in a state parallel to the holding surface of the first suction holding member 561 and the holding surface of the second suction holding member 562 . Next, the above-mentioned holding process and wafer dividing process are performed on all the streets 23 formed in the direction perpendicular to the streets 23 subjected to the wafer dividing process, whereby the semiconductor wafer 2 is divided along the streets 23 into Each device 22 .

After performing the above-mentioned wafer dividing step, an altered layer removing step is carried out. In this altered layer removing step, the back surface of the wafer subjected to the wafer dividing step is ground to form the wafer into the finished thickness of the device, whereby the The metamorphic layer is removed. This altered layer removal step is implemented using a grinding device substantially the same as the grinding device 3 shown in FIG. 3 described above. In addition, it is important that the grinding tool 321 of the grinding wheel 32 equipped on the grinding device 3 shown in FIG. 8 for implementing the degenerated layer removal process uses a vitrified bond with a fixed particle size of 0.5 μm to 7 μm and A grinding tool formed of diamond abrasive grains with a concentration of 30 to 70, preferably 50. The particle size of the diamond abrasive grains constituting the grinding tool 321 depends on the type of wafer (silicon wafer, sapphire wafer, quartz wafer, gallium arsenide (GaAs) wafer, gallium nitride (GaN) wafer, gallium phosphide (GaP) wafer ) and different, according to the experiment of the present inventors etc., under the situation that wafer is a silicon wafer, the particle diameter of desired diamond abrasive grain is 0.5 μm～2 μm, and the particle diameter of desired diamond abrasive grain is 5 μm under the situation that wafer is a sapphire wafer ~7μm, when the wafer is a quartz wafer, the particle size of the diamond abrasive grain is expected to be 3 μm to 6 μm, when the wafer is a GaAs wafer, the particle size of the diamond abrasive grain is expected to be 1 μm to 3 μm, when the wafer is a GaN wafer Below, it is desirable that the particle diameter of the diamond abrasive grain is 2 μm to 5 μm, and when the wafer is a GaP wafer, it is desirable that the particle diameter of the diamond abrasive grain is 1.5 μm to 4 μm. The lower limit of the diamond abrasive grains constituting the grinding wheel 321 is the lower limit value at which the workpiece can be ground, and the upper limit of the diamond abrasive grains is that the device can not be damaged when the degenerated layer removal process described later is implemented. The upper limit value for grinding with cracks on the periphery of the Therefore, in the illustrated embodiment, since the semiconductor wafer 2 as a workpiece is a silicon wafer, the diamond abrasive grains constituting the grinding wheel 321 are set to have a particle diameter of 0.5 μm to 2 μm and a concentration of 50. .

When the above-mentioned grinding device 3 is used to perform the altered layer removal step, as shown in FIG. On the chuck table 31 of the grinding device 3, and the ring-shaped frame F is placed on the outer peripheral portion of the chuck table 31, and the semiconductor wafer 2 and the ring-shaped frame are separated by operating a suction member (not shown). F suction is held on the chuck table 31 . Therefore, the back surface 20b of the silicon substrate 20 of the semiconductor wafer 2 held on the chuck table 31 is located on the upper side. After the semiconductor wafer 2 is sucked and held on the chuck table 31 in this way, the chuck table 31 is rotated at a speed of, for example, 40 rpm to 300 rpm in the direction indicated by the arrow 31 a, while the grinding wheel 32 is rotated toward the arrow 32 a. The direction shown is rotated at a rotational speed of, for example, 1000rpm to 3500rpm, and the grinding wheel 32 is brought into contact with the back surface 20b of the silicon substrate 20 constituting the semiconductor wafer 2, and the grinding wheel 32 is turned in the direction shown by the arrow 32b at a speed of, for example, 0.3 μm/sec. The grinding feed rate is, for example, a grinding feed of 180 μm. As a result, the back surface 20b of the silicon substrate 20 constituting the semiconductor wafer 2 is ground, and as shown in FIG. Formed to the finished thickness of the device (20 μm in the illustrated embodiment). In this way, since the altered layer removal process is carried out using a grinding tool formed by fixing diamond abrasive grains with a particle diameter of 0.2 μm to 2 μm and a concentration of 50 by using a vitrified bond, even if the semiconductor wafer 2 is divided into Each device 22, because the impact force of the grinding tool on the periphery of the divided device 22 is small, so no cracks will be generated in the device 22.

After performing the above-mentioned altered layer removal process, a wafer transfer process is performed. In this wafer transfer process, the back surface of the wafer that has been divided into individual devices is pasted on the surface of the protective tape mounted on the ring frame, and the The above-mentioned dicing tape T stuck on the surface of the wafer is peeled off and the above-mentioned ring frame F is removed. In this wafer transfer process, as shown in FIG. 10( a ), the dicing tape T (the semiconductor wafer 2 on which the individual devices 22 have been divided) attached to the ring frame F is irradiated from the ultraviolet ray irradiator 6 . ultraviolet light. As a result, the adhesive paste of the dicing tape T hardens and the adhesive force decreases. Next, as shown in FIG. 10( b ), the surface (lower surface in FIG. 10( b )) of the dicing tape Ta attached to the ring frame Fa is attached to the back surface of the silicon substrate 20 constituting the semiconductor wafer 2. 20b (upper surface in (b) of FIG. 10 ), wherein the semiconductor wafer 2 is pasted on the dicing tape T mounted on the ring frame F. In addition, the ring frame Fa and the dicing tape Ta may have substantially the same structures as the ring frame F and the dicing tape T described above. Next, the semiconductor wafer 2 (segmented into individual devices 22 ) whose surface is attached to the dicing tape T is peeled off from the dicing tape T as shown in FIG. 10( c ). At this time, the dicing tape T is irradiated with ultraviolet rays as shown in (a) of FIG. Each device 22) is peeled off from the dicing tape T. Then, the ring frame F equipped with the dicing tape T is removed, whereby, as shown in (d) of FIG. Its surface. In this way, the wafer grinding step, the altered layer forming step, the wafer dividing step, and the altered layer removing step are carried out in a state where the surface of the wafer is attached to the dicing tape T attached to the ring frame F, and the semiconductor wafer 2 is divided into one Therefore, the front and back sides of the semiconductor wafer 2 can be turned over and reattached to the dicing tape Ta assembled on the ring frame Fa without the semiconductor wafer 2 being broken. Therefore, the conduction test of the devices 22 can be performed in a state where the semiconductor wafer 2 divided into individual devices 22 is reattached to the dicing tape Ta attached to the ring frame Fa.

After the wafer transfer process is carried out in the above-mentioned manner, a pick-up process is carried out in which the individually divided devices attached to the surface of the protective tape attached to the ring frame are peeled off from the protective tape and processed. pick up. This pick-up step is implemented using the pick-up device 7 shown in FIG. 11 . The pick-up device 7 shown in FIG. 11 is provided with: a frame holding member 71, which is used to hold the above-mentioned annular frame Fa; The cutting tape Ta of the held ring frame Fa expands; and the chuck 73 is picked up. The frame holding member 71 has an annular frame holding member 711 and a plurality of clamps 712 as fixing members arranged on the outer periphery of the frame holding member 711 . The upper surface of the frame holding member 711 forms a mounting surface 711a on which the ring-shaped frame Fa is mounted, and the ring-shaped frame Fa is mounted on the mounting surface 711a. Then, the ring-shaped frame Fa placed on the mounting surface 711 a is fixed to the frame holding member 711 by the clamp 712 . The frame holding member 71 configured in this way is supported by the belt expansion member 72 so as to be able to advance and retreat in the vertical direction.

The belt expansion member 72 includes an expansion drum 721 disposed inside the above-mentioned annular frame holding member 711 . Both the inner diameter and the outer diameter of the expansion drum 721 are smaller than the inner diameter of the annular frame Fa, and larger than the outer diameter of the semiconductor wafer 2 (divided into individual devices 22 ) mounted on the annular frame Fa. Also, the expansion drum 721 has a support flange 722 at the lower end. The belt expansion member 72 in the illustrated embodiment includes a support member 723 capable of advancing and retreating the above-mentioned annular frame holding member 711 in the vertical direction. The support member 723 is constituted by a plurality of air cylinders 723a disposed on the support flange 722, and the piston rods 723b of the air cylinders 723a are connected to the lower surface of the annular frame holding member 711 described above. The supporting member 723 composed of the plurality of air cylinders 723a can move the annular frame holding member 711 in the vertical direction between the standard position and the expanded position, the standard position being the placement shown in (a) of FIG. 12 . The surface 711a is located at substantially the same height as the upper end of the expansion drum 721, which is a predetermined amount below the upper end of the expansion drum 721 as shown in FIG.

The pick-up process performed using the pick-up apparatus 7 comprised as mentioned above is demonstrated with reference to FIG. 12. FIG. That is, as shown in (a) of FIG. In the frame holding member 711 (frame holding process), the dicing tape Ta on which the semiconductor wafer 2 (divided into individual devices) is pasted is mounted on the ring frame Fa. At this time, the frame holding member 711 is positioned at the reference position shown in (a) of FIG. 12 . Next, the plurality of air cylinders 723a serving as support members 723 constituting the belt expansion member 72 are operated to lower the annular frame holding member 711 to the expanded position shown in FIG. 12( b ). Therefore, since the annular frame Fa fixed on the mounting surface 711a of the frame holding member 711 also descends, the cutting tape Ta and the upper end of the expansion drum 721 mounted on the annular frame Fa as shown in (b) of FIG. The edge contacts and is expanded (with expansion process). As a result, since the semiconductor wafer 2 pasted on the dicing tape Ta is divided into individual devices 22 along the lanes 23 , the distance between the individual devices 22 is increased to form a space S. In this state, the pickup chuck 73 is operated to attract and hold the surface (upper surface) of the device 22, and the device 22 is peeled off from the dicing tape Ta and picked up. At this time, the device 22 can be easily peeled off from the dicing tape Ta by pushing up the device 22 from the lower side of the dicing tape Ta with the lifting pin 74 as shown in FIG. 12( b ). Since the lifting pin 74 acts on the back of the device 22 to lift up the device 22 , the surface of the device 22 will not be damaged. In addition, since the gap S between individual devices 22 is enlarged as described above in the pickup step, the devices 22 can be easily picked up without contacting adjacent devices 22 . Since the surface (upper surface) of the device 22 picked up by the pick-up chuck 73 in this way is suction-held, there is no need to turn the front and back of the device 22 over afterwards.

As mentioned above, although this invention was demonstrated based on illustrated embodiment, this invention is not limited to embodiment, Various deformation|transformation is possible within the range of the summary of this invention. For example, in the above-mentioned embodiment, it is shown that the above-mentioned wafer grinding step, altered layer forming step, wafer dividing step, and altered layer removing step are performed in a state where the surface of the wafer is attached to the dicing tape attached to the ring frame. However, it is also possible to carry out the above-mentioned wafer grinding process and the altered layer forming process after attaching the protective tape to the surface of the wafer, and then attach the back surface of the wafer to the dicing tape mounted on the ring frame and attach the protective tape to the surface of the wafer. The above-mentioned wafer dividing step is carried out in the peeled state, and then the altered layer removal step is carried out after affixing the protective tape to the front surface of the wafer and peeling the dicing tape from the back surface of the wafer.

Claims (1)

1. A method for processing a wafer, in which the wafer is divided along a spacer, the surface of the wafer is divided into a plurality of regions by the spacer formed in a grid pattern, and the plurality of regions are divided into Devices are formed in the region, and the wafer processing method is characterized in that, The processing method of described wafer comprises following steps: a wafer grinding process in which the back surface of the wafer is ground so that the thickness of the wafer is formed into a predetermined thickness; A modified layer forming step, in which the modified layer is irradiated from the back side of the wafer subjected to the wafer grinding step along the spacer lanes with laser light that is transparent to the wafer, and inside the wafer along the spacer lines. forming a metamorphic layer at a depth from the surface of the wafer that is greater than the finished thickness of the device; A wafer dividing step, in which an external force is applied to the wafer subjected to the altered layer forming step, and the wafer is divided into individual devices along the interval lanes on which the altered layer is formed; and an altered layer removal step in which the altered layer is removed by grinding the back surface of the wafer subjected to the wafer dividing step to form the wafer into a finished thickness of the device, The degenerated layer removal step is implemented using a grinding tool formed by fixing diamond abrasive grains with a particle diameter of 0.5 μm to 7 μm with a vitrified bond.

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