CN102176182B - Method for improving stability of low drop-out voltage regulating circuit and low drop-out voltage regulating stabilizer for realizing same - Google Patents

Abstract

The invention provides a method for improving the stability of a low drop-out voltage regulating circuit and a low drop-out voltage stabilizer for realizing the same. The circuit is realized by introducing an additional zero pole in the low drop-out voltage regulating circuit so as to improve the stability of the low drop-out voltage regulator circuit. The method comprises the following specific steps: introducing a feedback loop formed by serial connection of a compensation capacitor and a compensation resistor between the grid and drain of a P-channel metal oxide semiconductor (PMOS) drive tube; designing values of the compensation capacitor and the compensation resistor; calculating a second main pole of the low drop-out voltage stabilizer through an additional zero point generated in the compensation circuit; and simultaneously compensating the added additional pole brought by the compensation circuit by the zero point generated by the output capacitor of the low drop-out voltage regulating circuit. Therefore, the phase margin of the circuit is improved, better stability of the low drop-out voltage regulator circuit can be realized, and the output end of the low drop-out voltage regulator circuit cannot oscillate.

Description

Improve the method for low-pressure drop voltage-stabilizing circuit stability and realize the low dropout voltage regulator of the method

Technical field

The invention belongs to the mu balanced circuit field, relate to a kind of voltage stabilizer that improves the method for mu balanced circuit stability and realize the method, relate in particular to a kind of low dropout voltage regulator that improves the method for low-pressure drop voltage-stabilizing circuit stability and realize the method.

Background technology

In low dropout (LDO) regulator circuit design, loop stability be a part and parcel.Fig. 1 is the structural representation of existing low dropout (LDO) regulator circuit.Referring to Fig. 1, low dropout (LDO) regulator circuit 10 is mainly by error amplifier circuit 100, and PMOS driving tube 110 and resistance-feedback network 120 consist of.The positive input of error amplifier circuit 100 meets input reference voltage Vref, the grid G of the output termination PMOS driving tube 110 of error amplifier circuit 100, and, input reference voltage Vref is produced by bandgap voltage reference circuit.The output of PMOS driving tube 110 drain D by resistance-feedback network 120 the first resistance R 1 and the second resistance R 2 dividing potential drops after feed back to the reverse input end of error amplifier circuit 100.Be connected to the output capacitance Co that falls stabilizer output voltage in order to stabilizing low voltage at output point Vout.Resr is the equivalent series resistance of output capacitance Co, and Iload is the load current of circuit.

Fig. 2 is the small-signal model figure of low dropout (LDO) regulator circuit shown in Figure 1.Wherein Roa is the output impedance of error amplifier circuit 100, and Cgs is the grid source capacitance of PMOS driving tube, and Cgd is the grid leak electrode capacitance of PMOS driving tube.GmVgs is the current source that the gate source voltage Vgs of PMOS driving tube controls, r ₀Output impedance for the PMOS driving tube.Small-signal model to low dropout (LDO) regulator circuit shown in Figure 2 is carried out zero-pole analysis as can be known, and the value of its output capacitance Co is the stray capacitance on error amplifier circuit 100 output points generally, so this point is output dominant pole P1 usually.The angular frequency of output dominant pole P1 _p1For:

${\mathrm{\ω}}_{P1}=\frac{1}{r_0{C}_o}---\left(1\right)$

Wherein: r ₀The output impedance of the PMOS driving tube of low dropout voltage regulator.

The second dominant pole P2 is positioned at the output terminal of error amplifier circuit 100, and by the output impedance Roa of error amplifier circuit 100, the grid source capacitor C gs of PMOS driving tube 110 and the shunt capacitance of gate leakage capacitance Cgd obtain.The angular frequency of the second dominant pole P2 _p2For:

${\mathrm{\ω}}_{P2}\≈\frac{1}{R_{\mathrm{oa}}(C_{\mathrm{gs}}+C_{\mathrm{gd}})}---\left(2\right)$

Because there is equivalent series resistance Resr in output capacitance Co, circuit can exist one zero point Z1.Zero point Z1 angular frequency _z1For:

${\mathrm{\ω}}_{Z1}=\frac{1}{R_{\mathrm{esr}}{C}_o}---\left(3\right)$

Fig. 3 is the amplitude-versus-frequency curve figure of low dropout (LDO) regulator circuit shown in Figure 1.As shown in Figure 3,90 degree phase shifted cancellation that zero point, Z1 brought the negative 90 degree phase shifts that bring of the second dominant pole P2, this shows, as long as it is stable preferably to make the unity gain bandwidth of voltage stabilizer less than the 3rd dominant pole P3, loop be had.

Above analysis has been supposed the frequency of Z1 at zero point lower than the frequency of the second dominant pole P2, or frequency both is mutually close, because the impact that positive phase shifted cancellation the second dominant pole P2 negative of Z1 at zero point is moved.But in some practical applications, often require the output capacitance Co value of low dropout (LDO) regulator circuit less, because output capacitance Co adopts ceramic disc capacitor usually, the variation of its capacitance and resistance value is subjected to the impact of flow-route and temperature very large, in particular, in some situation, the value of output capacitance Co and equivalent series resistance Resr thereof can be very little, thereby make the angular frequency of Z1 at zero point very high, and Fig. 4 is namely that low dropout (LDO) regulator circuit shown in Figure 1 is in the angular frequency at zero point _z1Amplitude-versus-frequency curve figure when too high.In this case, Z1 can't compensate the phase shift of the second dominant pole P2 at zero point, and the stability of low dropout (LDO) regulator circuit shows as variation stabilizer output voltage and vibration can occur, makes the circuit cisco unity malfunction.

Summary of the invention

In order to solve the technical matters that exists in background technology, the invention provides a kind of low dropout voltage regulator that improves the method for low-pressure drop voltage-stabilizing circuit stability and realize the method, it has improved the phase margin of low-pressure drop voltage-stabilizing circuit, its output terminal can not vibrated, thereby can guarantee that low-pressure drop voltage-stabilizing circuit has higher stability.

Technical solution of the present invention is as follows:

A kind of method that improves low-pressure drop voltage-stabilizing circuit stability, the method comprises the steps:

(i) angular frequency of the dominant pole P1 of low-pressure drop voltage-stabilizing circuit _p1For:

${\mathrm{\ω}}_{P1}=\frac{1}{r_0{C}_o}---\left(1\right)$

Wherein: Co is the output capacitance of low-pressure drop voltage-stabilizing circuit, r ₀The output impedance of the PMOS driving tube of low-pressure drop voltage-stabilizing circuit;

(ii) angular frequency of the second dominant pole P2 of low-pressure drop voltage-stabilizing circuit _p2For:

${\mathrm{\ω}}_{P2}\≈\frac{1}{R_{\mathrm{oa}}(C_{\mathrm{gs}}+C_{\mathrm{gd}})}---\left(2\right)$

Wherein: Roa is the output impedance of the error amplifier 100 of low-pressure drop voltage-stabilizing circuit, and Cgs is the grid source capacitance of PMOS driving tube, and Cgd is the grid leak electrode capacitance of PMOS driving tube;

(iii) the output capacitance Co of low-pressure drop voltage-stabilizing circuit zero point Z1 angular frequency _z1For:

${\mathrm{\ω}}_{Z1}=\frac{1}{R_{\mathrm{esr}}{C}_o}---\left(3\right)$

Wherein: Resr is the equivalent series resistance of low-pressure drop voltage-stabilizing circuit output capacitance Co;

(iv) introduce additional zero Zc and additional pole Pc, and be ω by angular frequency _zcAdditional zero Zc to come the offset angle frequency be ω _p2The second dominant pole P2, the angular frequency that the output capacitance Co by low-pressure drop voltage-stabilizing circuit produces is ω _z1Z1 at zero point to come the offset angle frequency be ω _pcAdditional pole Pc.

The above is ω by angular frequency _zcAdditional zero Zc to come the offset angle frequency be ω _p2The second dominant pole P2, its more suitable mode refers to: the angular frequency that makes the second dominant pole P2 _p2Be substantially equal to the angular frequency of additional zero Zc _zcThe described angular frequency that produces by the output capacitance Co of low-pressure drop voltage-stabilizing circuit is ω _z1Z1 at zero point to come the offset angle frequency be ω _pcAdditional pole Pc, its more suitable mode refers to: the angular frequency that makes additional pole Pc _pcBe substantially equal to the angular frequency of Z1 at zero point _z1

The above is ω by angular frequency _zcAdditional zero Zc to come the offset angle frequency be ω _p2The second dominant pole P2, its ideal style refers to: the angular frequency that makes the second dominant pole P2 _p2Angular frequency with additional zero Zc _zcEquate; The described angular frequency that produces by the output capacitance Co of low-pressure drop voltage-stabilizing circuit is ω _z1Z1 at zero point to come the offset angle frequency be ω _pcAdditional pole Pc, its ideal style refers to: the angular frequency that makes additional pole Pc _pcAngular frequency with Z1 at zero point _z1Equate.

Above-described introducing additional zero Zc and additional pole Pc specifically can realize by introducing backfeed loop 130.

Above-described backfeed loop 130 specifically can be by compensating resistance Rc and the RC feedback circuit that consists of of building-out capacitor Cc of serial connection mutually, and this backfeed loop 130 is connected between the drain electrode and grid of PMOS driving tube 110.

The above-described angular frequency that makes the second dominant pole P2 _p2Angular frequency with additional zero Zc _zcPhase etc. can be specifically to satisfy following formula:

$\frac{1}{C_c{R}_c}=\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

Wherein: Rc is the compensating resistance of RC backfeed loop, and Cc is the building-out capacitor of RC backfeed loop;

The described angular frequency that makes additional pole Pc _pcAngular frequency with Z1 at zero point _z1Equating, can be specifically to satisfy following formula:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}=\frac{1}{R_{\mathrm{esr}}{C}_o}.$

A kind of low dropout voltage regulator of realizing above-mentioned raising low-pressure drop voltage-stabilizing circuit stability approach, comprise: error amplifier circuit 100, the positive input of this error amplifier circuit 100 meets input reference voltage Vref, the output terminal of its reverse input end connecting resistance feedback network 120, the grid G of its output termination PMOS driving tube 110; The source S of described PMOS driving tube 110 meets supply voltage VDD, and its drain D meets the output end vo ut of low dropout voltage regulator; One termination power voltage VDD of described resistance-feedback network 120, other end ground connection, the reverse input end of the output termination error amplifier circuit 100 of this resistance-feedback network 120; Its special character is: be connected to backfeed loop 130 between the drain D of described PMOS driving tube 110 and grid G, this backfeed loop 130 is to comprise the compensating resistance Rc that is in series and the RC backfeed loop of building-out capacitor Cc.

Above-described compensating resistance Rc and building-out capacitor Cc are advisable to satisfy following condition:

(i) angular frequency of the second dominant pole P2 _p2Be substantially equal to the angular frequency of additional zero Zc _zc:

$\frac{1}{C_c{R}_c}\∝\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

(ii) angular frequency of additional pole Pc _pcBe substantially equal to the angular frequency of Z1 at zero point _z1:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}\∝\frac{1}{R_{\mathrm{esr}}{C}_o},$

Wherein: Cc is the building-out capacitor of backfeed loop 130, Rc is the compensating resistance of backfeed loop 130, Roa is the output impedance of error amplifier circuit 100, Cgs is the grid source capacitance of PMOS driving tube, Cgd is the grid leak electrode capacitance of PMOS driving tube, Co is output capacitance, and Resr is the equivalent series resistance of output capacitance Co.

Above-described compensating resistance Rc and building-out capacitor Cc are to satisfy following condition for the most desirable:

(i) angular frequency of the second dominant pole P2 _p2Angular frequency with additional zero Zc _zcEquate:

$\frac{1}{C_c{R}_c}=\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gs}})},$

(ii) angular frequency of additional pole Pc _pcAngular frequency with Z1 at zero point _z1Equate:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}=\frac{1}{R_{\mathrm{esr}}{C}_o}.$

Above-described resistance-feedback network 120 generally can adopt the first resistance R 1 and the second resistance R 2 that are in series to consist of.

Advantage of the present invention is as follows:

Stability is high.The present invention's angular frequency is ω _zcAdditional zero Zc offset angle frequency be ω _p2The second dominant pole P2, the angular frequency that produces with output capacitance Co is ω _z1Z1 offset angle frequency at zero point be ω _pcAdditional pole Pc, improved the phase margin of low-pressure drop voltage-stabilizing circuit, its output terminal can not vibrated, thereby can guarantee that low-pressure drop voltage-stabilizing circuit has higher stability.

Implementation is simple.The present invention only need to add components and parts seldom in low dropout (LDO) regulator circuit, simple in structure, is easy to realize.

Circuit power consumption is relatively low.Because the added components and parts of the present invention are passive device, therefore, its realization can not increase the power consumption of low dropout (LDO) regulator circuit.

Description of drawings

Fig. 1 is the structural representation of existing low dropout (LDO) regulator circuit;

Fig. 2 is the small-signal analysis illustraton of model of existing low dropout (LDO) regulator circuit;

Fig. 3 is the amplitude-versus-frequency curve figure of existing low dropout (LDO) regulator circuit shown in Figure 1;

Fig. 4 is the amplitude-versus-frequency curve figure of existing low dropout (LDO) regulator circuit shown in Figure 1 in the too high situation of angular frequency at zero point;

Fig. 5 is circuit structure principle schematic of the present invention;

Fig. 6 is small-signal analysis illustraton of model of the present invention;

Fig. 7 is that the present invention adopts the RC feedback to carry out the amplitude-versus-frequency curve figure of zero compensation.

The explanation of accompanying drawing drawing:

The 10-low dropout (LDO) regulator circuit, 100-error amplifier circuit, 110-driving tube, 120-resistance-feedback network, 130-backfeed loop; The Rc-compensating resistance, Cc-building-out capacitor, the output impedance of the error amplifier of Roa-low dropout voltage regulator, the grid source capacitance of Cgs-PMOS driving tube, the grid leak electrode capacitance of Cgd-PMOS driving tube, r ₀The output impedance of the PMOS driving tube of-low dropout voltage regulator, the output capacitance of Co-low dropout voltage regulator, the equivalent series resistance of the output capacitance Co of Resr-low dropout voltage regulator, R1-the first resistance, R2-the second resistance.

Embodiment

The present invention introduces additional zero Zc and additional pole Pc in low dropout (LDO) regulator circuit, utilize additional zero Zc and additional pole Pc to improve the stability of low dropout (LDO) regulator circuit, backfeed loop that specifically can access is made of building-out capacitor Cc and compensating resistance Rc series connection between the grid G of PMOS driving tube and drain D, the value of design compensation capacitor C c and compensating resistance Rc makes the angular frequency of the additional zero Zc that building-out capacitor Cc and compensating resistance Rc produce _zcBe substantially equal to the angular frequency of the second dominant pole P2 of low dropout (LDO) regulator circuit self _p2, make simultaneously the angular frequency of the additional pole Pc that the loop of the grid leak electrode capacitance Cgd of building-out capacitor Cc, compensating resistance Rc and PMOS driving tube produces _pcBe substantially equal to low dropout (LDO) regulator circuit zero point Z1 angular frequency _z1Thereby, make the angular frequency of the second dominant pole P2 of low dropout (LDO) regulator circuit self _p2By the angular frequency of additional zero Zc _zcCompensation, the angular frequency of additional pole Pc _pcBy the external output capacitance of circuit zero point Z1 angular frequency _z1Compensate, the phase margin of circuit improves, low dropout (LDO) regulator circuit can be realized preferably stability, its output terminal can not vibrate.

It is as follows that the present invention improves the performing step of low-pressure drop voltage-stabilizing circuit stability approach:

(i) angular frequency of the dominant pole P1 of low-pressure drop voltage-stabilizing circuit _p1For:

${\mathrm{\ω}}_{P1}=\frac{1}{r_0{C}_o}---\left(1\right)$

Wherein: Co is the output capacitance of low-pressure drop voltage-stabilizing circuit, r ₀The output impedance of the PMOS driving tube of low-pressure drop voltage-stabilizing circuit;

(ii) angular frequency of the second dominant pole P2 of low-pressure drop voltage-stabilizing circuit _p2For:

${\mathrm{\ω}}_{P2}\≈\frac{1}{R_{\mathrm{oa}}(C_{\mathrm{gs}}+C_{\mathrm{gd}})}---\left(2\right)$

Wherein: Roa is the output impedance of the error amplifier 100 of low-pressure drop voltage-stabilizing circuit, and Cgs is the grid source capacitance of PMOS driving tube, and Cgd is the grid leak electrode capacitance of PMOS driving tube;

(iii) the output capacitance Co of low-pressure drop voltage-stabilizing circuit zero point Z1 angular frequency _z1For:

${\mathrm{\ω}}_{Z1}=\frac{1}{R_{\mathrm{esr}}{C}_o}---\left(3\right)$

Wherein: Resr is the equivalent series resistance of low-pressure drop voltage-stabilizing circuit output capacitance Co;

(iv) introduce additional zero Zc and additional pole Pc, specifically can realize by the RC feedback circuit that is connected to compensating resistance Rc between the PMOS driving tube 110 drain-gate utmost points, that be connected in series mutually and building-out capacitor Cc formation.And:

(a) be ω by angular frequency _zcAdditional zero Zc to come the offset angle frequency be ω _p2The second dominant pole P2.Angular frequency with the second dominant pole P2 _p2Be substantially equal to the angular frequency of additional zero Zc _zcFor more suitable, with the angular frequency of the second dominant pole P2 _p2Angular frequency with additional zero Zc _zcEquate for best, namely

$\frac{1}{C_c{R}_c}=\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

Wherein: Rc is the compensating resistance of RC backfeed loop, and Cc is the building-out capacitor of RC backfeed loop;

(b) angular frequency that produces of the output capacitance Co by low-pressure drop voltage-stabilizing circuit is ω _z1Z1 at zero point to come the offset angle frequency be ω _pcAdditional pole Pc.Angular frequency with additional pole Pc _pcBe substantially equal to the angular frequency of Z1 at zero point _z1For more suitable, with the angular frequency of additional pole Pc _pcAngular frequency with Z1 at zero point _z1Equate for best, namely

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}=\frac{1}{R_{\mathrm{esr}}{C}_o}.$

Referring to Fig. 5, low dropout voltage regulator of the present invention is the RC backfeed loop that has added compensating resistance Rc and building-out capacitor Cc to be in series and to consist of between the drain D of the PMOS of existing low dropout (LDO) regulator circuit shown in Figure 1 driving tube 110 and grid G.The positive input of error amplifier circuit 100 meets input reference voltage Vref, the output terminal of its reverse input end connecting resistance feedback network 120, the grid G of its output termination PMOS driving tube 110.The source S of PMOS driving tube 110 meets supply voltage VDD, and its drain D is the output end vo ut of low dropout (LDO) regulator circuit.One termination power voltage VDD of resistance-feedback network 120, other end ground connection, the reverse input end of the output termination error amplifier circuit 100 of this resistance-feedback network 120.Resistance-feedback network 120 is made of the first resistance R 1 that is in series and the second resistance R 2.The input end of resistance-feedback network 120 is ends of the second resistance R 2, and the other end of the second resistance R 2 and the first resistance R 1 are joined, and the end that the second resistance R 2 and the first resistance R 1 are joined is the output terminal of resistance-feedback network 120, the other end ground connection of the first resistance R 1.

The value of compensating resistance Rc and building-out capacitor Cc is advisable to satisfy following condition:

(i) angular frequency of the second dominant pole P2 _p2Be substantially equal to the angular frequency of additional zero Zc _zc:

$\frac{1}{C_c{R}_c}\∝\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

(ii) angular frequency of additional pole Pc _pcBe substantially equal to the angular frequency of Z1 at zero point _z1:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}\∝\frac{1}{R_{\mathrm{esr}}{C}_o},$

The value of compensating resistance Rc and building-out capacitor Cc is to satisfy following condition as best:

(i) angular frequency of the second dominant pole P2 _p2Angular frequency with additional zero Zc _zcEquate:

$\frac{1}{C_c{R}_c}=\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gs}})},$

(ii) angular frequency of additional pole Pc _pcAngular frequency with Z1 at zero point _z1Equate:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}=\frac{1}{R_{\mathrm{esr}}{C}_o}.$

Referring to figure Fig. 6, it is the small-signal model figure of low dropout (LDO) regulator circuit shown in Figure 5, and wherein Roa is the output impedance of error amplifier 100, and Cgs is the grid sources electric capacity of PMOS driving tube, and Cgd is the gate leakage capacitance of PMOS driving tube.GmVgs is the current source that gate pmos source voltage Vgs controls, r ₀Output impedance for the PMOS driving tube.

Usually, the electric current that PMOS driving tube 110 flows through is larger, and its output impedance r0 will be much larger than the loaded impedance RL of low dropout (LDO) regulator circuit.And, because output capacitance Co is generally nF or uF rank, the stray capacitance Cgs of low dropout (LDO) regulator circuit inside, Cgd etc. are generally the pF rank, so the output capacitance Co of low dropout voltage regulator will be much larger than the internal capacitance of low dropout voltage regulator, the output limit is dominant pole P1.Analyze thus the angular frequency of the dominant pole P1 that obtains low dropout (LDO) regulator circuit _p1For:

${\mathrm{\ω}}_{p1}=\frac{1}{R_{\mathrm{oa}}[(1+g_m{r}_0)(C_c+C_{\mathrm{gd}})+C_{\mathrm{gs}}]+r_0(C_c+C_{\mathrm{gd}}+C_o)}\≈\frac{1}{r_0{C}_o}---\left(4\right)$

The angular frequency of the second dominant pole P2 _p2For:

${\mathrm{\ω}}_{p2}=\frac{R_{\mathrm{oa}}[(1+g_m{r}_0)(C_c+C_{\mathrm{gd}})+C_{\mathrm{gs}}]+r_0(C_c+C_{\mathrm{gd}}+C_o)}{R_{\mathrm{oa}}{r}_0[(C_c+C_{\mathrm{gd}})C_{\mathrm{gs}}+(C_c+C_{\mathrm{gd}})C_o+C_{\mathrm{gs}}{C}_o]}\≈\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})}---\left(5\right)$

The upper series equivalent resistance of output capacitance Co produces zero point Z1 angular frequency _z1For:

${\mathrm{\ω}}_{z1}\≈\frac{1}{R_{\mathrm{esr}}{C}_o}---\left(6\right)$

The backfeed loop that the compensating resistance Rc that the present invention adds between the grid leak utmost point of the PMOS of low dropout (LDO) regulator circuit driving tube and building-out capacitor Cc form, the angular frequency of the additional zero Zc that it produces _zcFor:

${\mathrm{\ω}}_{\mathrm{zc}}\≈\frac{1}{C_c{R}_c}---\left(7\right)$

Grid G, the transition function between drain D of PMOS driving tube are:

$H\left(s\right)\≈\frac{(R_c+\frac{1}{s{C}_c})\frac{1}{s{C}_{\mathrm{gd}}}}{R_c+\frac{1}{{\mathrm{sC}}_c}+\frac{1}{{\mathrm{sC}}_{\mathrm{gd}}}}---\left(8\right)$

(8) in formula, be namely the additional zero Zc that is produced by compensating resistance Rc and building-out capacitor Cc the zero point that is obtained by molecule, and by denominator obtain limit be the additional pole that the grid source capacitance Cgs by compensating resistance Rc, building-out capacitor Cc and PMOS driving tube produces, the angular frequency of this additional pole _pcFor

${\mathrm{\ω}}_{\mathrm{pc}}\≈\frac{1}{R_c(C_c//C_{\mathrm{gs}})}---\left(9\right)$

In the circuit analysis of above-mentioned institute, when the equivalent resistance Resr of the upper series connection of very little or output capacitance Co is very little as external output capacitance Co, its generation zero point Z1 angular frequency _z1Angular frequency much larger than the second dominant pole P2 of system _p2By compensating resistance Rc and the building-out capacitor Cc in rational design of feedback loop, the angular frequency of the additional zero Zc that produces with backfeed loop _zcCompensate the angular frequency of the second dominant pole P2, make the angular frequency of the limit of backfeed loop generation _pcBe output electric capacity zero point Z1 angular frequency _z1Compensate, that is, make the angular frequency of the second dominant pole P2 _p2Be substantially equal to the angular frequency of additional zero Zc _zc, the angular frequency of additional pole Pc _pcBe substantially equal to the angular frequency of Z1 at zero point _z1Optimal design is to satisfy following formula:

$\frac{1}{C_c{R}_c}=\frac{1}{R_s(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})}---\left(10\right)$

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}=\frac{1}{R_{\mathrm{esr}}{C}_o}---\left(11\right)$

Shown in Figure 7 is the amplitude-versus-frequency curve that the present invention satisfies the optimal design of (10) formula, (11) formula, its phase margin that demonstrates low dropout (LDO) regulator circuit improves, thereby can guarantee that its output terminal can not vibrate, therefore make low-pressure drop voltage-stabilizing circuit have higher stability.

Claims (9)

1. method that improves low-pressure drop voltage-stabilizing circuit stability, the method comprises the steps:

(i) angular frequency of the dominant pole of low-pressure drop voltage-stabilizing circuit (P1) _p1For:

${\mathrm{\ω}}_{P1}=\frac{1}{r_0{C}_o}---\left(1\right)$

Wherein: Co is the output capacitance of low-pressure drop voltage-stabilizing circuit, r ₀The output impedance of the PMOS driving tube of low-pressure drop voltage-stabilizing circuit;

(ii) angular frequency of second dominant pole (P2) of low-pressure drop voltage-stabilizing circuit _p2For:

${\mathrm{\ω}}_{P2}\≈\frac{1}{R_{\mathrm{oa}}(C_{\mathrm{gs}}+C_{\mathrm{gd}})}---\left(2\right)$

Wherein: Roa is the output impedance of the error amplifier (100) of low-pressure drop voltage-stabilizing circuit, and Cgs is the grid source capacitance of PMOS driving tube, and Cgd is the grid leak electrode capacitance of PMOS driving tube;

(iii) angular frequency at the zero point (Z1) of the output capacitance of low-pressure drop voltage-stabilizing circuit (Co) _z1For:

${\mathrm{\ω}}_{Z1}=\frac{1}{R_{\mathrm{esr}}{C}_o}---\left(3\right)$

Wherein: Resr is the equivalent series resistance of low-pressure drop voltage-stabilizing circuit output capacitance (Co);

(iv) introduce additional zero (Zc) and additional pole (Pc), and,

A) be ω by angular frequency _zcAdditional zero (Zc) to come the offset angle frequency be ω _p2The second dominant pole (P2): the angular frequency that makes the second dominant pole (P2) _p2Be substantially equal to the angular frequency of additional zero (Zc) _zc

B) angular frequency that produces of the output capacitance (Co) by low-pressure drop voltage-stabilizing circuit is ω _z1To come the offset angle frequency be ω zero point (Z1) _pcAdditional pole (Pc): the angular frequency that makes additional pole (Pc) _pcBe substantially equal to the angular frequency of zero point (Z1) _z1

2. the method for raising low-pressure drop voltage-stabilizing circuit stability according to claim 1, it is characterized in that: described is ω by angular frequency _zcAdditional zero (Zc) to come the offset angle frequency be ω _p2The second dominant pole (P2) refer to: the angular frequency that makes the second dominant pole (P2) _p2Angular frequency with additional zero (Zc) _zcEquate; The angular frequency that described output capacitance by low-pressure drop voltage-stabilizing circuit (Co) produces is ω _z1To come the offset angle frequency be ω zero point (Z1) _pcAdditional pole (Pc) refer to: the angular frequency that makes additional pole (Pc) _pcAngular frequency with zero point (Z1) _z1Equate.

3. the method for raising low-pressure drop voltage-stabilizing circuit stability according to claim 1 and 2 is characterized in that: described introducing additional zero (Zc) and additional pole (Pc) are to realize by introducing backfeed loop (130).

4. the method for raising low-pressure drop voltage-stabilizing circuit stability according to claim 3, it is characterized in that: described backfeed loop (130) is the RC feedback circuit that is made of the compensating resistance (Rc) that is connected in series mutually and building-out capacitor (Cc), and this backfeed loop (130) is connected between the drain electrode and grid of PMOS driving tube (110).

5. the method for raising low-pressure drop voltage-stabilizing circuit stability according to claim 4 is characterized in that:

The described angular frequency that makes the second dominant pole (P2) _p2Angular frequency with additional zero (Zc) _zcEquate, specifically satisfy following formula:

$\frac{1}{C_c{R}_c}=\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

Wherein: Rc is the compensating resistance of RC backfeed loop, and Cc is the building-out capacitor of RC backfeed loop;

The described angular frequency that makes additional pole (Pc) _pcAngular frequency with zero point (Z1) _z1Equate, specifically satisfy following formula:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}=\frac{1}{R_{\mathrm{esr}}{C}_o}.$

6. low dropout voltage regulator of realizing the described raising low-pressure drop voltage-stabilizing circuit of claim 1 stability approach, comprise error amplifier circuit (100), the positive input of this error amplifier circuit (100) connects input reference voltage (Vref), the output terminal of its reverse input end connecting resistance feedback network (120), the grid (G) of its output termination PMOS driving tube (110); The source electrode (S) of described PMOS driving tube (110) connects supply voltage (VDD), and its drain electrode (D) connects the output terminal (Vout) of low dropout voltage regulator; One termination power voltage (VDD) of described resistance-feedback network (120), other end ground connection, the reverse input end of the output termination error amplifier circuit (100) of this resistance-feedback network (120); It is characterized in that: be connected to backfeed loop (130) between the drain electrode (D) of described PMOS driving tube (110) and grid (G), this backfeed loop (130) is to comprise the compensating resistance (Rc) that is in series and the RC backfeed loop of building-out capacitor (Cc).

7. low dropout voltage regulator according to claim 6, is characterized in that, described compensating resistance (Rc) and building-out capacitor (Cc) satisfy following condition:

(i) angular frequency of the second dominant pole (P2) _p2Be substantially equal to the angular frequency of additional zero (Zc) _zc:

$\frac{1}{C_c{R}_c}\∝\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

(ii) angular frequency of additional pole (Pc) _pcBe substantially equal to the angular frequency of zero point (Z1) _z1:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}\∝\frac{1}{R_{\mathrm{esr}}{C}_o},$

Wherein: Cc is the building-out capacitor of backfeed loop (130), Rc is the compensating resistance of backfeed loop (130), Roa is the output impedance of error amplifier circuit (100), Cgs is the grid source capacitance of PMOS driving tube, Cgd is the grid leak electrode capacitance of PMOS driving tube, Co is output capacitance, and Resr is the equivalent series resistance of output capacitance (Co).

8. according to claim 6 or 7 described low dropout voltage regulators, it is characterized in that: described compensating resistance (Rc) and building-out capacitor (Cc) satisfy following condition:

(i) angular frequency of the second dominant pole (P2) _p2Angular frequency with additional zero (Zc) _zcEquate:

$\frac{1}{C_c{R}_c}=\frac{1}{R_{\mathrm{oa}}(C_c+C_{\mathrm{gs}}+C_{\mathrm{gd}})},$

(ii) angular frequency of additional pole (Pc) _pcAngular frequency with zero point (Z1) _z1Equate:

$\frac{1}{R_c(C_c//C_{\mathrm{gs}})}=\frac{1}{R_{\mathrm{esr}}{C}_o}.$

9. low dropout voltage regulator according to claim 8, it is characterized in that: described resistance-feedback network (120) comprises the first resistance (R1) and the second resistance (R2) that is in series.

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