CN102176442B - Test structure and method for measuring HCI (hot carrier injection) reliability of MOS (metal oxide semiconductor) device - Google Patents

Abstract

The invention discloses a test structure for measuring HCI reliability of a MOS device, comprising: an n-type MOS device and a p-type MOS device, a source electrode of the n-type MOS device, a substrate and a drain electrode of the p-type MOS device The three are connected together to form the source of the structure; and the source of the p-type MOS device, the substrate and the drain of the n-type device are connected together to form the drain of the structure; the n-type The gates of the MOS device and the p-type MOS device respectively constitute the n-type gate and the p-type gate of the structure. The invention provides a test structure and method capable of simultaneously measuring the HCI reliability of n-type and p-type MOS devices, so that the HCI reliability test of n-type and p-type MOSFET devices can be completed on the same test structure.

Description

Test structure and method for measuring HCI reliability of MOS devices

technical field

The invention relates to the field of MOS device reliability research, in particular to a test structure and method for measuring the reliability of MOS device HCI (Hot Carrier Injection, hot carrier injection).

Background technique

With the rapid development of semiconductor technology and the substantial increase in the integration of microelectronic chips, the design and processing level of integrated circuits has entered the nano-MOS era, resulting in the degradation of nano-MOS device performance and the continuous emergence of factors affecting device reliability. . Due to the shrinking of the device size, the lateral electric field and the effective electric field of the channel in the MOS device increase. At the same time, the HCI degradation caused by pMOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) has become comparable to that of nMOSFET. In order to obtain the law of HCI degradation of n and p-type MOSFET devices, conventional The test method is to use the HCI test structure to conduct HCI reliability tests on n- and p-type MOSFET devices with minimum channel lengths, respectively.

The commonly used HCI test structure is a MOS device (especially a MOSFET device) with a minimum channel length, as shown in Figure 1, which is a four-terminal device including source, gate, drain and substrate, where W and L Respectively represent the channel width and channel length of the device, which are determined by the relative positions of the gate and the source and drain regions of the MOSFET device. Measuring the HCI degradation of n- and p-type MOS devices requires n- and p-type MOSFET devices with minimum channel lengths, respectively.

Contents of the invention

(1) Technical problems to be solved

The technical problem to be solved by the present invention is: how to provide a test structure and method that can simultaneously measure n-type and p-type MOS devices (especially MOSFET devices) HCI reliability, so that n-type and p-type MOSFET devices HCI reliability test Can be done on the same test structure.

(2) Technical solution

In order to solve the above technical problems, the present invention provides a test structure for measuring the HCI reliability of MOS devices, including: n-type MOS devices and p-type MOS devices, the source electrode of the n-type MOS devices, substrate and p The drains of the p-type MOS devices are connected together to form the source of the structure; and the source of the p-type MOS device, the substrate and the drain of the n-type device are connected together to form the drain of the structure The gates of the n-type MOS device and the p-type MOS device constitute the n-type gate and the p-type gate of the structure respectively.

Wherein, the MOS device is a metal oxide semiconductor field effect transistor device.

The present invention also provides a kind of method utilizing described structure to carry out HCI reliability test of MOS device, comprises the following steps:

S1. Measuring the initial characteristics of the n-type MOS device and the p-type MOS device to obtain initial device parameters;

S2. Apply stress conditions to the n-type MOS device and the p-type MOS device, and perform a stress aging test within a preset time interval;

S3. Perform parameter tests on the n-type MOS device and the p-type MOS device to obtain device parameters corresponding to the degradation time until the total time of stress application ends.

Wherein, the stress aging test is a hot carrier effect HCI degradation test.

Wherein, the stress condition includes voltage.

Wherein, the stress conditions applied to the n-type MOS device and the p-type MOS device in step S2 are consistent.

Wherein, the stress condition is: applying a stress voltage to the n-type gate and the drain of the structure, and grounding the p-type gate and the source of the structure.

(3) Beneficial effects

The present invention provides a kind of testing structure and the method that can measure HCI reliability of n-type and p-type MOS device (especially MOSFET device) HCI reliability by combining n-type and p-type HCI test structure, make n-type and p-type The HCI reliability test of p-type MOSFET devices can be completed on the same test structure, which shortens the reliability measurement time by half, thereby improving the reliability test efficiency, and also reducing the layout area of the test structure and reducing the test cost. .

Description of drawings

The structure diagram of traditional HCI reliability test device in Fig. 1;

Fig. 2 is the HCI reliability test structural representation of the present invention;

3 is a schematic diagram of the HCI degradation generation mechanism of the MOS device produced by testing the test structure of the present invention;

Among Fig. 4 (a) and (b) have shown respectively the accelerated stress parameter and characteristic test parameter that are set when utilizing test structure of the present invention to test;

Fig. 5 is the test result curve of the test structure of the present invention;

Fig. 6 is a flow chart of the method of the present invention.

Detailed ways

The specific implementation manners of the present invention will be described in further detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

The present invention provides a test structure capable of simultaneously measuring the HCI reliability of n-type and p-type MOS devices (MOSFET devices in this embodiment). As shown in Figure 2, this structure combines the HCI test structure of n-type and p-type MOSFET devices. The source Sn of the n-type MOSFET device, the substrate Sub-n and the drain Dp of the p-type MOSFET device pass through Internally connected together to form the source of the structure of the present invention, meanwhile, the source Sp of the p-type MOSFET device, the substrate Sub-p and the drain Dn of the n-type device are also connected together to form the drain of the structure of the present invention, The gates of the n-type and p-type MOSFET devices are independent of each other to form the n-type gate and the p-type gate of the structure of the present invention, thus forming a four-terminal structure including both n-type and p-type devices.

As shown in Figure 2, where Wn and Ln represent the channel width and channel length of the n-type MOSFET device, Wp and Lp represent the channel width and channel length of the p-type MOSFET device, respectively, in the HCI degradation test, the channel The channel length should be the shortest channel length of n-type and p-type MOSFET devices. In CMOS technology, the shortest channel length of n-type devices is generally greater than or equal to the shortest channel length of p-type MOSFET devices, and the channel width is much larger Fixed value for minimum width of n-type and p-type MOSFET devices.

When the MOS device is under HCI reliability stress, because the stress voltage is applied on the gate and drain at the same time, the carriers moving in the channel are accelerated by the electric field at the drain end, and obtain higher energy. Impact ionization occurs at the end, generating high-energy electron-hole pairs, which easily cross the Si/SiO ₂ interface barrier and enter the gate oxide layer, resulting in degradation of device performance. The mechanism of HCI generation is shown in Figure 3. The slanted line in Figure 3 shows the pinch-off condition of the channel under the HCI stress condition, and the five-pointed star indicates the impact ionization at the drain due to the high electric field, which causes the HCI degradation of the device. The degradation of device characteristics is mainly manifested in the drift of key device parameters such as threshold voltage, saturation leakage current, and transconductance. Once the key parameters of the device drift to a certain extent, the normal working state of the device will no longer exist, eventually leading to the failure of the integrated circuit.

Utilize the structure of the present invention, n-type and p-type MOS device are properly arranged, make n-type and p-type MOS device carry out reliability degradation experiment under the same stress condition, the voltage setting of each end point is as in Fig. 4 (a ) shown. A stress voltage is applied to the n-type gate and drain, and the p-type gate and source are grounded. This stress condition corresponds to Vgs (representing the voltage between the gate and source) = Vds (representing the drain and source In the case of the voltage between)=Vstress (representing the stress voltage), the stress conditions of the n-type and p-type MOS devices are consistent. Then, when it is necessary to measure the device characteristics, the voltage between the source and the drain of the structure of the present invention is set as the power supply voltage Vdd, and the n-type and p-type grids are scanned synchronously, from 0V to Vdd, and the voltage is set as Shown in (b) in Figure 4. Current is measured at the drain of the structure of the present invention, because n-type and p-type MOSFET devices are turned on at different stages of gate voltage scanning, therefore, the different parts of the leakage current curve represent the characteristics of n and p-type MOSFET devices respectively, Fig. 5 A typical test result is given. In the measured leakage current, not only the curves on the left and right sides can respectively represent the transfer characteristics of the p-type and n-type MOSFET devices, but also the drift of the threshold voltage caused by the degradation of the device HCI leads to the shift of the data to the two sides with the increase of the stress time. Broadening, it can be seen that the test results can be used to characterize the HCI degradation of n- and p-type MOSFETs, respectively.

Under normal working conditions, HCI degradation is a slow accumulation process throughout the life cycle of integrated circuits. Therefore, the characterization of HCI degradation of silicon-level MOS devices must rely on short-term accelerated stress. The test flow is shown in Figure 6 As shown, it includes the following steps: S1, measuring the initial characteristics of the n-type MOS device and the p-type MOS device, and obtaining the initial device parameters; S2, applying stress conditions to the n-type MOS device and the p-type MOS device, in the preset Stress aging test is carried out within the time interval; S3, carry out parameter test on described n-type MOS device and p-type MOS device, obtain the device parameter corresponding to degradation time, until the total time of applying stress ends. Before stress is applied, it is first necessary to measure the initial characteristics of the device to obtain initial device parameters, such as initial leakage current Id ₀ , initial threshold voltage Vth _0, etc., and perform stress aging tests (including HCI degradation tests) within a preset time interval , followed by parameter testing of the device to obtain parameters such as Id and Vth related to the degradation time, and the whole process is until the end of the time when the stress is applied. From this, the dynamic relationship between the change of the key parameters of the device (such as Id-Id ₀ , Vth-Vth _0, etc.) with the degradation time can be obtained, which is represented by Δ(t). Satisfy the power exponent relation:

Δ(t)=At ⁿ (1)

Among them, A and n are model constants, which are related to factors such as process, device, and stress conditions. In the logarithmic-logarithmic coordinate system, according to the slope and intercept of the test data line, the corresponding model parameters n and A can be extracted.

It can be seen from the above embodiments that, through reasonable design and voltage configuration, the present invention can simultaneously measure the reliability characteristics of HCI degradation of n-type and p-type MOSFET devices under the same stress condition, effectively improving the test efficiency. In addition, the multiplexing of source and drain is adopted in the structure design, which reduces the test structure area.

Specifically, by using the present invention, the HCI degradation test of nanometer n-type and p-type MOS devices can be integrated in one test structure without additionally increasing the number of pads (PAD), thereby saving the area of the test structure. With the invention, the HCI degradation test of the nano MOS device is completed through a single measurement of the same structure, the reliability measurement time is reduced, and the test efficiency is improved. The degeneration of the n-type and p-type MOSFET devices obtained by the invention widens the test characteristics to both sides, reduces the coupling between the two, and is beneficial to the acquisition and analysis of the respective degeneration data.

The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Those of ordinary skill in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all Equivalent technical solutions also belong to the category of the present invention, and the scope of patent protection of the present invention should be defined by the claims.

Claims (7)

1. a test structure for measuring MOS device HCI reliability, is characterized in that, comprises: n-type MOS device and p-type MOS device, the source electrode of described n-type MOS device, substrate and p-type MOS device The three drains are connected together to form the source of the structure; and the source of the p-type MOS device, the substrate and the drain of the n-type device are connected together to form the drain of the structure; The gates of the n-type MOS device and the p-type MOS device respectively constitute the n-type gate and the p-type gate of the structure. 2. The test structure according to claim 1, wherein the MOS device is a metal oxide semiconductor field effect transistor device. 3. a method utilizing the test structure described in claim 1 or 2 to carry out MOS device HCI reliability test, is characterized in that, comprises the following steps: S1. Measuring the initial characteristics of the n-type MOS device and the p-type MOS device to obtain initial device parameters; S2. Apply stress conditions to the n-type MOS device and the p-type MOS device, and perform a stress aging test within a preset time interval; S3. Perform parameter tests on the n-type MOS device and the p-type MOS device to obtain device parameters corresponding to the degradation time until the total time of stress application ends. 4. The method according to claim 3, wherein the stress aging test is a hot carrier effect HCI degradation test. 5. The method of claim 3, wherein the stress condition comprises voltage. 6. The method according to claim 3, characterized in that, in step S2, the stress conditions applied to the n-type MOS device and the p-type MOS device are the same. 7. The method according to claim 6, wherein the stress condition is: a stress voltage is applied to the n-type gate and the drain of the structure, and the p-type gate and the The source of the structure is grounded.

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