CN102194519B - Memory - Google Patents
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- CN102194519B CN102194519B CN201010125884.5A CN201010125884A CN102194519B CN 102194519 B CN102194519 B CN 102194519B CN 201010125884 A CN201010125884 A CN 201010125884A CN 102194519 B CN102194519 B CN 102194519B
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- 238000003491 array Methods 0.000 claims description 19
- 238000013500 data storage Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- 238000000034 method Methods 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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Abstract
The invention provides a memory. The memory comprises a plurality of memory regions, a voltage source, a voltage dividing unit and a precoding unit, wherein the voltage source is used for providing the read reference voltage to the memory regions; the voltage dividing unit comprises a plurality of memory region voltage dividing units corresponding to the memory regions; the precoding unit is connected with the voltage dividing unit and is used for selecting the corresponding memory region voltage dividing units according to the address signals input into the precoding unit; and the selected memory region voltage dividing units are used for outputting the divided read reference voltage as the read voltage provided to the corresponding memory regions after dividing the read reference voltage provided by the voltage source. The memory has the following advantages: the power consumption of the memory is reduced and the reading time of the memory can be optimized; and besides, crosstalk between the adjacent memory regions can be avoided from being easily caused when data of some memory regions are read for a long time.
Description
Technical field
The present invention relates to memory area, particularly relate to flash memory.
Background technology
In recent years, along with developing rapidly of semiconductor memory, the advanced storeies such as DRAM, EEPROM, flash memory, owing to having the advantage of high density, low-power consumption and low price, widely use.
Fig. 1 is the structural representation of the storer of existing display read method, and with reference to figure 1, existing storer comprises several storage arrays 103, is respectively storage array 1, storage array 2 ... storage array n; Line decoder 102, is connected with described some storage arrays 101; Voltage source 101, in prior art, voltage source is generally voltage regulator (Regulator), be connected with described line decoder 102, when reading the data stored in storer, voltage source 101 provides reading voltage by described line decoder 102 to the storage array of correspondence, realizes the digital independent to corresponding storage array.
The storer of the prior art, identical reading voltage is provided to all storage arrays, but, the reading characteristic of the storage unit (Cell) of different storage array (Array) is not identical, the size of the reading voltage needed for reality is not identical yet, in order to the digital independent to all storage arrays can be realized, higher reading voltage need be provided to meet the requirement of the reading voltage of all storage arrays, can cause that the power consumption of storer is large, reading speed is slow like this; In addition, when the reading voltage height of the reading voltage ratio actual needs applied a certain storage array, when carrying out reading data to this storage array for a long time, easily cause the crosstalk phenomenon between adjacent storage array.
In addition, when the situation that the array structure that different storage arrays is corresponding is different, the number of corresponding line decoder can be different, and thus can need the line decoder driver of different size, this will cause storer difficult wiring; If make the measure-alike of all line decoder drivers be beneficial to wiring, reading speed will be caused slack-off, and power consumption is large.
Application number be 03100073.8 Chinese patent application disclose one and " reading circuit of the memory element of operating voltage can be reduced ", but, do not solve the shortcoming of above-described prior art.
Summary of the invention
When what the present invention solved is the storer reading of prior art, power consumption is large, reading speed is slow and the phenomenon of crosstalk can occur between adjacent storage array.
Another problem that the present invention solves be expert at Encoder driving device measure-alike time storer difficult wiring problem, if or line decoder driver size different, can not reading time of optimize storage and speed, problem that power consumption is large.
For solving above technical matters, the invention provides a kind of storer, it comprises several storage areas; Voltage source, provides reading reference voltage to described storage area; Also comprise:
Partial pressure unit, comprises several respectively corresponding to the storage area partial pressure unit of several storage areas described;
Pre-decode unit, be connected with described partial pressure unit, according to the address signal of this pre-decode unit of input, select corresponding storage area partial pressure unit, exported as the reading voltage being supplied to respective memory regions by after the reading reference voltage dividing potential drop that described voltage source provides by the storage area partial pressure unit selected.
Optionally, described partial pressure unit also comprises voltage output end, and described reading voltage is exported by described voltage output end.
Optionally, described storer comprises several storage arrays, and each storage array is a storage area.
Optionally, described storer comprises several storage arrays, and each storage array comprises some sectors respectively, and wherein, each sector of each storage array is a storage area.
Optionally, described storer comprises some storage arrays, and each storage array comprises some sectors respectively, and each sector comprises some pages respectively, and wherein, every one page of each sector of each storage array is a storage area.
Optionally, described storage area partial pressure unit comprises: resistance, MOS transistor, control module;
Wherein, described resistor coupled in parallel is in the grid of described MOS transistor and source electrode, and the drain electrode of MOS transistor is connected with described voltage output end, and the source electrode of described MOS transistor is connected with the output terminal of described voltage source;
Described control module is connected with the grid of described MOS transistor, in described storage area partial pressure unit by the unlatching of this MOS transistor of the time control system of selection.
Optionally, described voltage source is voltage regulator.
Optionally, described reading reference voltage is 0.1 ~ 0.5V with the voltage difference scope of reading voltage.
Compared with prior art, the present invention has the following advantages:
When reading the data in storage area, corresponding storage area is supplied to as reading voltage after the reading reference voltage dividing potential drop that voltage source provides by storage area partial pressure unit, the corresponding storage area partial pressure unit of each storage area, can according to the reading characteristic of the storage unit of different storage areas, the voltage provided by voltage source different storage areas is respectively after dividing potential drop, be supplied to different storage areas, can be optimized respectively the reading voltage of each storage area like this, thus reduce the power consumption of storer, and can reading time of optimize storage, in addition, can avoiding the reading voltage of the reading voltage ratio actual needs that some storage area applies high, when carrying out reading data to some storage area for a long time, easily causing the crosstalk phenomenon between neighbouring storage areas.
And, easily connect up to make storer, line decoder driver measure-alike, by storage area partial pressure unit, after the reading reference voltage dividing potential drop provided by voltage source, be supplied to different storage areas, can be optimized respectively the reading time of different storage zone and speed, solve line decoder driver size identical time, cannot to the reading time of storer and speed is optimized and power consumption is large problem.
Accompanying drawing explanation
Fig. 1 is the structural representation of existing storer;
Fig. 2 is the structural representation of the storer of the specific embodiment of the invention;
Fig. 3 is the electrical block diagram of the storage area partial pressure unit of the specific embodiment of the invention.
Embodiment
The storer of prior art, identical reading voltage is provided to all storage arrays, but, the reading characteristic of the storage unit (Cell) of different storage array (Array) is not identical, the size of the reading voltage needed for reality is not identical yet, in order to the digital independent to all storage arrays can be realized, higher reading voltage need be provided to meet the requirement of the reading voltage of all storage arrays, can cause that the power consumption of storer is large, reading speed is slow like this, the storer of the specific embodiment of the invention, corresponding storage area is supplied to as reading voltage after the reading reference voltage dividing potential drop that voltage source provides by storage area partial pressure unit, the corresponding storage area partial pressure unit of each storage area, can according to the reading characteristic of the storage unit of different storage areas, respectively to the different voltage that voltage source is provided after dividing potential drop, be supplied to different storage areas, can be optimized respectively the reading voltage of each storage area like this, thus reduce the power consumption of storer, and can reading time of optimize storage.In addition, the storer of prior art, when the reading voltage height of the reading voltage ratio actual needs applied a certain storage area, when carrying out reading data to this storage area for a long time, easily causes the crosstalk phenomenon between neighbouring storage areas; The storer of the specific embodiment of the invention, according to the reading characteristic of the storage unit of different storage zone, different reading voltage can be provided, crosstalk phenomenon when avoiding the data read for a long time in storage area and between neighbouring storage areas respectively to different storage areas.
And, the storer of prior art, if line decoder driver is measure-alike, the reading time of storer then can be made slack-off, if the size of line decoder driver is different, storer is not easy wiring, storer of the present invention, even if line decoder driver is measure-alike, by storage area partial pressure unit; As reading voltage after the reading reference voltage dividing potential drop that voltage source is provided, be supplied to different storage areas, can be optimized respectively the reading time of different storage zone, when avoiding line decoder driver size identical, the shortcoming that cannot be optimized the reading time of storer, storer can be made so both to have connected up easily, the reading time of storer can be improved again, reduce power consumption.
In order to make those skilled in the art better understand essence of the present invention, below in conjunction with accompanying drawing, specific embodiments of the invention are described in detail.
Fig. 2 is the structural representation of the storer of the specific embodiment of the invention, with reference to figure 2, storer of the present invention, comprise several storage areas 201, be respectively storage area 1, storage area 2 ... storage area n, wherein, the quantity of storage area is determined according to the actual needs, does not limit at this; Voltage source 202, for providing reading reference voltage, in a particular embodiment of the present invention, described voltage source 202 is voltage regulator; Partial pressure unit 204, its input end is connected with the output terminal of described voltage source, this partial pressure unit 204 comprises voltage output end Vout and several are respectively corresponding to the storage area partial pressure unit of described storage area, be respectively storage area partial pressure unit 1, storage area partial pressure unit 2 ... storage area partial pressure unit n, the quantity of storage area partial pressure unit is equal with the quantity of storage area; Pre-decode unit 205, be connected with described partial pressure unit 204, according to its address signal (namely will carry out the address of the storage area of read operation) of input, select corresponding storage area partial pressure unit, export as the reading voltage being supplied to corresponding storage area after the described reading reference voltage dividing potential drop described voltage source 202 provided by the storage area partial pressure unit selected, in a particular embodiment of the present invention, described reading voltage can be exported by described voltage output end Vout.In this embodiment of the present invention, storer also comprises line decoder 203, its input end is connected with the voltage output end Vout of described partial pressure unit 204, output terminal is connected with several storage areas 201 described, for carrying out addressing to several storage areas 201 described, corresponding storage area is selected to read, such as, when described pre-decode unit 205 selects storage area partial pressure unit 1 to carry out dividing potential drop, line decoder 203 selects storage area 1, the reading voltage that storage area partial pressure unit 1 exports exports to storage area 1 through line decoder 203, realize the digital independent to storage area 1.
In other embodiments, the reading voltage (exporting by by the storage area partial pressure unit selected) that the voltage output end Vout of partial pressure unit 204 exports also can directly be supplied to corresponding storage area without line decoder 203.In addition, the reading voltage that each storage area partial pressure unit of partial pressure unit 204 exports also can obstructed superpotential output end vo ut and be directly supplied to corresponding storage area, such as, the output terminal of each storage area partial pressure unit is connected with the input end of corresponding storage area respectively
Fig. 3 is the electrical block diagram of the storage area partial pressure unit of the specific embodiment of the invention, Fig. 3 is for storage area partial pressure unit 1 and storage area 1 (eliminating line decoder 203 in figure), and other storage area partial pressure unit are identical with the circuit structure of storage area 1 with storage area partial pressure unit 1 with the circuit structure of corresponding storage area.
With reference to figure 3, storage area partial pressure unit 1 comprises resistance R1, MOS transistor 301, control module 302; Wherein, resistance R1 is parallel to grid and the source electrode of described MOS transistor 301, the drain electrode of MOS transistor 301 is connected with described voltage output end Vout, provides reading voltage to storage area 1, and the source electrode of described MOS transistor 301 is connected with the output terminal of described voltage source 202; Described control module 302 is connected with the grid of described MOS transistor 301, for being selected the unlatching (conducting) of time control system this MOS transistor 301 in described storage area partial pressure unit 1, this control module 302 is added in the size of the voltage on the grid of described MOS transistor 301 by adjustment, control the unlatching of this MOS transistor 301; Described pre-decode unit 205 is connected with this control module 302, when pre-decode unit 205 selects storage area partial pressure unit 1, the voltage that control module 302 adjustment is added on MOS transistor 301 grid, MOS transistor 301 is opened (conducting), provides reading voltage to described storage area 1.The voltage V that voltage source 202 provides, voltage after resistance R1 and MOS transistor 301 dividing potential drop is that V-Vr-Vt exports to storage area 1, Vr represents the voltage difference of resistance R1 input end and output terminal, Vt represents the threshold voltage of MOS transistor 301, therefore the voltage that the drain electrode of MOS transistor exports is V-Vr-Vt, the dividing potential drop Vr of resistance R1 and the threshold voltage vt sum of MOS transistor are stores up the input end of region partial pressure unit 1 and the voltage difference of output terminal, can be regulated the size of storage area partial pressure unit dividing potential drop by the size of adjusting resistance R1.
In practical application, resistance R1 is designed to adjustable resistance, after storer manufacture completes, can test storer: by adjusting the resistance of the first resistance R1, the read operation of storage area is verified, the reading voltage of applicable described storage area 1 can be determined, thus determine the voltage difference of storage area partial pressure unit input end and output terminal.The voltage (the reading reference voltage of input) of usual storage area partial pressure unit input end is 0.1V ~ 0.5V with the difference scope of the voltage (the reading voltage of output) of output terminal, and the scope of the voltage difference of each storage area partial pressure unit input end and output terminal can be the same or different.
In a specific embodiment of the present invention, described storer comprises some storage arrays, be respectively storage array 1, storage array 2 ... storage array n, wherein, each storage array is a storage area, storage array 1 corresponding stored region 1, storage array 2 corresponding stored region 2, the like, described storage area partial pressure unit 1 provides reading voltage to storage array 1, storage area partial pressure unit 2 provides reading voltage to storage array 2, the like.In one example, storer comprises two storage arrays, is respectively data storage array and code storage array, then the quantity of storage array is two, and storage array 1 is data storage array, and storage array 2 is code storage array.
In other embodiments of the invention, described storer comprises some storage arrays, each storage array comprises some sectors (Section) respectively, be respectively sector 1, sector 2 ... sector n, wherein, each sector of each storage array is a storage area, corresponding stored region, sector 11, corresponding stored region, sector 22, the like, described storage area partial pressure unit 1 provides program/erase voltage to sector 1, and storage area partial pressure unit 2 provides program/erase voltage to sector 2, the like.
Spirit of the present invention also can be generalized to less storage area, such as, described storer comprises some storage arrays, each storage array comprises some sectors respectively, each sector comprises some pages (Bank) respectively, be respectively page 1, page 2 ... page n, wherein, every one page of each sector of each storage array is a storage area, page 1 corresponding stored region 1, page 2 corresponding stored regions 2, the like, described storage area partial pressure unit 1 provides program/erase voltage to page 1, storage area partial pressure unit 2 provides program/erase voltage to page 2, the like.
The foregoing is only specific embodiments of the invention; spirit of the present invention is better understood in order to make those skilled in the art; but protection scope of the present invention not with the specific descriptions of this specific embodiment for limited range; any those skilled in the art without departing from the spirit of the scope of the invention; can make an amendment specific embodiments of the invention, and not depart from protection scope of the present invention.
Claims (8)
1. a storer, it comprises several storage areas; Voltage source, provides reading reference voltage to described storage area; Line decoder, for carrying out addressing to several storage areas described, selects corresponding storage area to read; It is characterized in that, also comprise:
Partial pressure unit, comprises several respectively corresponding to the storage area partial pressure unit of several storage areas described, the corresponding storage area partial pressure unit of each storage area;
Pre-decode unit, be connected with described partial pressure unit, according to the address signal of this pre-decode unit of input, select corresponding storage area partial pressure unit, export as the reading voltage being supplied to respective memory regions after the described reading reference voltage dividing potential drop described voltage source provided by the storage area partial pressure unit selected;
The input end of line decoder is connected with the voltage output end of described partial pressure unit, and output terminal is connected with several storage areas described; When described pre-decode unit selects storage area partial pressure unit to carry out dividing potential drop, line decoder selects storage area, and the reading voltage that storage area partial pressure unit exports exports to storage area through line decoder, realizes the digital independent to storage area.
2. storer as claimed in claim 1, it is characterized in that, described partial pressure unit also comprises voltage output end, and described reading voltage is exported by described voltage output end.
3. storer as claimed in claim 1, it is characterized in that, described storer comprises several storage arrays, and each storage array is a storage area.
4. storer as claimed in claim 1, it is characterized in that, described storer comprises several storage arrays, and each storage array comprises some sectors respectively, and wherein, each sector of each storage array is a storage area.
5. storer as claimed in claim 1, it is characterized in that, described storer comprises some storage arrays, each storage array comprises some sectors respectively, each sector comprises some pages respectively, and wherein, every one page of each sector of each storage array is a storage area.
6. storer as claimed in claim 1, it is characterized in that, described storage area partial pressure unit comprises: resistance, MOS transistor, control module;
Wherein, described resistor coupled in parallel is in the grid of described MOS transistor and source electrode, and the drain electrode of MOS transistor is connected with described voltage output end, and the source electrode of described MOS transistor is connected with the output terminal of described voltage source;
Described control module is connected with the grid of described MOS transistor, in described storage area partial pressure unit by the unlatching of this MOS transistor of the time control system of selection.
7. the storer as described in any one of claim 1 ~ 6, is characterized in that, described voltage source is voltage regulator.
8. storer as claimed in claim 1, is characterized in that, described reading reference voltage is 0.1 ~ 0.5V with the voltage difference scope of reading voltage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010125884.5A CN102194519B (en) | 2010-03-08 | 2010-03-08 | Memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201010125884.5A CN102194519B (en) | 2010-03-08 | 2010-03-08 | Memory |
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| CN102194519B true CN102194519B (en) | 2015-06-17 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1828764A (en) * | 2004-12-03 | 2006-09-06 | 旺宏电子股份有限公司 | Memory array with low power pre-charged bit lines |
| CN101027729A (en) * | 2004-07-29 | 2007-08-29 | 斯班逊有限公司 | Method for initializing non-volatile storage device, and non-volatile storage device |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100420125B1 (en) * | 2002-02-02 | 2004-03-02 | 삼성전자주식회사 | Non-volatile semiconductor memory device and power-up to read method thereof |
| JP4041054B2 (en) * | 2003-11-06 | 2008-01-30 | 株式会社東芝 | Semiconductor integrated circuit device |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101027729A (en) * | 2004-07-29 | 2007-08-29 | 斯班逊有限公司 | Method for initializing non-volatile storage device, and non-volatile storage device |
| CN1828764A (en) * | 2004-12-03 | 2006-09-06 | 旺宏电子股份有限公司 | Memory array with low power pre-charged bit lines |
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Address after: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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