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CN102194770A - Ultrathin semiconductor package - Google Patents

Ultrathin semiconductor package Download PDF

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Publication number
CN102194770A
CN102194770A CN2010101288003A CN201010128800A CN102194770A CN 102194770 A CN102194770 A CN 102194770A CN 2010101288003 A CN2010101288003 A CN 2010101288003A CN 201010128800 A CN201010128800 A CN 201010128800A CN 102194770 A CN102194770 A CN 102194770A
Authority
CN
China
Prior art keywords
encapsulation
semiconductor element
lead
wire
planar horizontal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2010101288003A
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Chinese (zh)
Inventor
S·诺恩德哈希特希查埃
S·希里诺拉酷尔
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
YOUTE THAILAND CO Ltd
Original Assignee
YOUTE THAILAND CO Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by YOUTE THAILAND CO Ltd filed Critical YOUTE THAILAND CO Ltd
Priority to CN2010101288003A priority Critical patent/CN102194770A/en
Publication of CN102194770A publication Critical patent/CN102194770A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48095—Kinked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18165—Exposing the passive side of the semiconductor or solid-state body of a wire bonded chip

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention relates to an ultrathin semiconductor package and particularly provides a package and a manufacturing method thereof. The package comprises a first plating area, a second plating area, a tube core, a bond and a mold, wherein the tube core is attached to the first plating area, and is coupled to the first and/or second plating area through the bond; and the mold is used for packaging the tube core and bonding wiring and the top surfaces of the first plating area and the second plating area. Therefore, the bottom surfaces of the first plating area and the second plating area are exposed outside the package.

Description

Semiconductor packages as thin as a wafer
Related application
The application incorporates this application according to the benefit of priority that 35 U.S.C 119 (e) partly require the common unsettled U.S. Provisional Patent Application 60/795,929 of submission on April 28th, 2006 into by reference at this.
Technical field
The present invention relates to the field of semiconductor packages.More specifically, the present invention relates to the film, semiconductor encapsulation.Especially, this encapsulation is the thickness of lead frame basically.
Background technology
For the portability that strengthens, a lot of application that are used to use semiconductor device are just in ever-smaller with lighten.The common example of this type of application comprises small electronic appliances, such as cell phone, PDA and portable MP 3 player.Traditional semiconductor device package is drawn together lead frame, and semiconductor element is mounted thereon.Wire bond is coupling between the lead-in wire of semiconductor element and lead frame.Molded of resin material around tube core, wire bond and lead frame, is exposed simultaneously to the electrically contacting of lead frame, to form Plastic Package.In conventional package, molded resin is much thicker than lead frame usually.Part is owing to the volume and the thickness of resin in these conventional package, and the electronic device that obtains is bigger and heavy than expection.
And, the Market competition of semiconductor device.The departmental cost of semiconductor device is relevant with the quantity of material of existence in the encapsulation.Use the encapsulation of less material to have more competitive price than another encapsulation of using more material.
Need a kind of littler, thinner and lighter encapsulation that is used for semiconductor device.Also need to use the semiconductor packages of less material.
Summary of the invention
For semiconductor element provides a kind of encapsulation.Described encapsulation comprises established lead frame.This lead frame has a plurality of established lead-in wires.Go between to have and be positioned near still first end spaced away of first semiconductor element.First end of lead-in wire is in first planar horizontal basically.Second end of each lead-in wire is higher than first end, and is in second planar horizontal basically, and wherein second planar horizontal is higher than first planar horizontal.Pad on the semiconductor element (pad) is electrically coupled to one or more first ends of lead-in wire.Around first semiconductor element and between the lead-in wire, form resin, make encapsulation have the thickness that equates basically with the thickness of lead-in wire.Encapsulation and lead frame have the thickness in 127 to 500 micrometer ranges.
Provide numerous embodiments to be used for semiconductor element is installed to encapsulation.Semiconductor element can be inverted, and flip-chip (flip chip) is bonded to one or more first ends.The dorsal part of flip-chip semiconductor tube core can expose, and perhaps can be covered by resin.Semiconductor element can wire bond to the first end.In this case, the dorsal part of semiconductor element can come out from encapsulation.Alternatively, semiconductor element can be installed on the die attach pad of exposure.
Can stacked at least two semiconductor elements in the encapsulation.In this case, each of two or more tube cores all wire bond to suitable lead-in wire.And two or more encapsulation can be stacked on another.In this case, the lead-in wire alignment with exposing makes the stack package electric coupling together, with the formation system.
Can carry out plating to part lead-in wire, with the bonding that strengthens the bonding wiring or be used for the flip-chip bonding.Can also partly go between to strengthen the plate weldering (boardsoldering) of encapsulation by plating.
Encapsulation forms by new method.Particularly, lead frame is to form by the step that forms the photoresist mask on the lead frame piece.Can use traditional masks.Next, half lead frame piece etches away at least, to form lead frame.Then, remove the photoresist mask.At last, lead frame is used band (tape).Band has strengthened subsequent treatment.
Description of drawings
Put down in writing novel feature of the present invention in the claims.Yet,, in the following drawings, put down in writing a plurality of execution mode of the present invention for illustration purpose.
Fig. 1 shows the technology according to some execution mode of the present invention.
Figure 1A shows the example results of each step in the technology of Fig. 1.
Fig. 2 shows the technology that forms this step of lead frame that does not have the tube core pad that comprises in embodiments.
Fig. 2 A shows the example results of each step in the technology of Fig. 2.
Fig. 2 B shows the illustrative processes that is used to form lead frame according to plurality of embodiments of the present invention.
Fig. 3 shows controlled collapsible chip connec-tion in embodiments.
Fig. 3 A shows the example results of each step in Fig. 3 technology.
Fig. 4 shows the exemplary products of the method for some execution mode to Figure 25.
More specifically, Fig. 4 shows tube core pad with exposure and the encapsulation that is exposed to the lead-in wire of top and bottom.
Fig. 4 A shows has the encapsulation at the Fig. 4 at place, base angle of top and bottom-exposed lead-in wire and mold.
Fig. 4 B shows has the encapsulation at the Fig. 4 at drift angle place of top and bottom-exposed lead-in wire and mold.
Fig. 5 shows the encapsulation of tube core Fig. 4 on the adhesive phase top.
Fig. 5 A shows has the encapsulation at the Fig. 5 at place, base angle of top and bottom-exposed lead-in wire and mold.
Fig. 5 B shows has the encapsulation at the Fig. 5 at drift angle place of top and bottom-exposed lead-in wire and mold.
Fig. 6 shows Fig. 5 encapsulation that adhesive is coupled to tube core on the tube core pad.
Fig. 6 A shows has the encapsulation at the Fig. 6 at place, base angle of top and bottom-exposed lead-in wire and mold.
Fig. 6 B shows has the encapsulation at the Fig. 6 at drift angle place of top and bottom-exposed lead-in wire and mold.
Fig. 7 shows the encapsulation of flip-chip form, and wherein tube core is coupled to lead-in wire by soldered ball, and the apparent surface of tube core is exposed to the top of encapsulation.
Fig. 7 A shows has the encapsulation at the Fig. 7 at place, base angle of top and bottom-exposed lead-in wire and mold.
Fig. 7 B shows has the encapsulation at the Fig. 7 at drift angle place of top and bottom-exposed lead-in wire and mold.
Fig. 8 shows the Flip-Chip Using of Fig. 7, and its tube core does not expose.
Fig. 8 A shows has the encapsulation at the Fig. 8 at place, base angle of top and bottom-exposed lead-in wire and mold.
Fig. 8 B shows has the encapsulation at the Fig. 8 at drift angle place of top and bottom-exposed lead-in wire and mold.
Fig. 9 shows the encapsulation of Fig. 7, has the tube core that (top) exposes, and it is coupled to the tube core pad that is exposed to package bottom by soldered ball.
Fig. 9 A shows has the encapsulation at the Fig. 9 at place, base angle of top and bottom-exposed lead-in wire and mold.
Fig. 9 B shows has the encapsulation at the Fig. 9 at drift angle place of top and bottom-exposed lead-in wire and mold.
Figure 10 illustrates the encapsulation of Fig. 9, and wherein tube core is not exposed to the top of encapsulation.
Figure 10 A shows has the encapsulation at the Figure 10 at place, base angle of top and bottom-exposed lead-in wire and mold.
Figure 10 B shows has the encapsulation at the Figure 10 at drift angle place of top and bottom-exposed lead-in wire and mold.
Figure 11 shows top and bottom-exposed lead-in wire wire bond to the stacked die of tube core and realizes.
Figure 11 A shows has the encapsulation at the Figure 11 at place, base angle of top and bottom-exposed lead-in wire and mold.
Figure 11 B shows has the encapsulation at the Figure 11 at drift angle place of top and bottom-exposed lead-in wire and mold.
Figure 12-Figure 25 shows the stacked or laminate packaging (PoP) of using some above-mentioned encapsulation and realizes.
Especially, Figure 12 shows the encapsulation according to two Fig. 4 of stacked or laminate packaging configuration.
Figure 13 shows the encapsulation according to two Fig. 5 of stacked configuration.
Figure 14 shows the package stacking of Fig. 5 on the encapsulation top of another Fig. 5, but described another encapsulation is squeezed, makes the bottom of bottom contiguous second encapsulation of the encapsulation of winning.
Figure 15 shows the encapsulation according to two Fig. 6 of stacked configuration.
Figure 16 shows and is stacked in the encapsulation that not inverted Fig. 6 encapsulates the inverted Fig. 6 on the top, the end face adjacency that makes two encapsulation.
Figure 17 shows and is stacked in the encapsulation that Fig. 5 encapsulates the Fig. 4 on the top.
Figure 18 shows and is stacked in the encapsulation that Fig. 6 encapsulates the Fig. 7 on the top.
Figure 19 shows and is stacked in the encapsulation that Fig. 6 encapsulates the Fig. 9 on the top.
Figure 20 shows encapsulation on the encapsulation top that is stacked in Fig. 9, inverted Fig. 6, the end face adjacency that makes two encapsulation.
Figure 21 shows and is stacked in inverted Fig. 9 and encapsulates encapsulation on the top, inverted Fig. 6.
Figure 22 shows the encapsulation of Fig. 6 C on the encapsulation top that is stacked in Fig. 6.
Figure 23 shows the encapsulation of Fig. 6 D on the encapsulation top that is stacked in Fig. 6.
Figure 24 shows the encapsulation of Fig. 6 D on the encapsulation top that is stacked in Fig. 5.
Figure 25 shows the encapsulation of Fig. 6 C on the encapsulation top that is stacked in Fig. 6.
Figure 26 shows the package stacking of Fig. 6 D on the encapsulation top of Fig. 7, and the package stacking of Fig. 7 is on the encapsulation top of Fig. 6.
The package stacking that Figure 27 shows Fig. 6 C is on the encapsulation top of inverted Fig. 6, and inverted Fig. 6 package stacking is on the encapsulation top of inverted Fig. 6 not.
Figure 28 shows various difform lead frames, and the division process that forms the lead-in wire of some execution mode.
Figure 28 A shows some execution mode and is used for forming the method that encapsulates shown in Fig. 4 A.
Figure 28 B shows some execution mode and is used for forming the method that encapsulates shown in Fig. 4 B.
Embodiment
In describing hereinafter, a plurality of details and alternative have been put down in writing for illustration purpose.Yet, it will be recognized by those of ordinary skills, can under the situation of not using these specific detail, put into practice the present invention.In other cases, known structure and device illustrate with the form of block diagram, disturb the description of this invention to avoid unnecessary details.
I. method
A. the lead frame that has the tube core pad
Fig. 1 shows the technology 100 that is used to make semiconductor packages according to some execution mode of the present invention.Figure 1A shows the example results of each step in the technology 100 of Fig. 1.As shown in these figures, technology 100 starts from step 110, forms lead frame 102 at this.The technology that forms lead frame is described with reference to figure 2B hereinafter.Lead frame 102 generally includes copper, 42 alloys or other suitable materials, and has the typical thickness in 127 to 500 micrometer ranges.Alternatively, the part of lead frame or lead frame can be carried out plating.This type of plating preferably improves intensity, bonding, electrical conductance and/or heat and transmits.Shown in Figure 1A, form the lead frame 102 of intended shape usually, be placed on then and be with on 108.
Lead frame 102 comprises die attach pad 112, and one and common a plurality of lead-in wires 114.Die attach pad 112 is the plane basically preferably, and has basal surface and top surface.The top surface of die attach pad 112 is suitable for receiving semiconductor element 122.Each lead-in wire 114 comprises first end, and it forms in first planar horizontal, and basically with die attach pad 112 coplanes.Form lead-in wire 114 to comprise the shape of step, layering and/or multistage formation.Each lead-in wire 114 comprises second end, and it is in the level that is higher than die attach pad 112.Preferably, step is to use photoresist and partial etching technology (normally etching partially) to form.As discussed further below, these shapes have specific advantage.
No matter the mode of formation lead frame 102 how, after step 110, technology 100 goes to step 120, carries out die attach and/or wire bond at this.As mentioned above, lead frame 102 generally includes and is used for tube core pad 112 and/or 114 the zone of going between.Shown in Figure 1A, die attach generally includes by using adhesive 123 that tube core 122 is coupled to die attach pad 112, and wire bond comprises and uses wiring 124 that tube core 122 is coupled to tube core pad 112 and/or one or more lead-in wire 114.
After step 120 was carried out die attach and/or wire bond, technology 100 went to step 130, used mold 132 at this.Usually, mold 132 comprises plastic polymer or resin, and its plastic packaging tube core 122, wire bond 124 also go up the top surface to lead frame 102, comprise tube core pad 112 and/or go between 114.
In case used mold 132 in step 130, technology 100 goes to step 140, removes at this and is with 108.When being with 108 to be removed, expose the basal surface of lead frame 102 usually, comprise tube core pad 112 and/or go between 114.
After going to be with step 140, technology 100 goes to step 150, and the individual encapsulation unit that comprises in this cutting mold bar is to form individual semiconductor packages.Then, technology 100 finishes.Hereinafter will further describe the cutting step of specific implementations in conjunction with Figure 28.114 and parts die attach pad 112 coplanes of going between expose by the bottom of encapsulation, and 114 those parts that are raised and keep segmentation procedure after of going between are then in the exposure of the top of encapsulation.Thus, encapsulation is only the same with lead frame thick.The thickness of lead frame is preferably in 127 to 500 microns scope.This is much all thinner than any conventional package.
B. the lead frame that does not have the tube core pad
Fig. 2 shows the technology that comprises the step 210 that is used to form the lead frame 202 that does not have the tube core pad in embodiments.Fig. 2 A shows the example results of each step of technology among Fig. 2.As shown in these figures, technology 200 starts from step 210, forms lead frame 202 at this.Lead frame 202 generally includes copper, 42 alloys or other suitable materials.Be similar to the above step 110 of Fig. 1, form lead frame 202 and comprise alternatively plating is carried out in one or more zones of lead frame 202.Shown in Fig. 2 A, form the lead frame 202 of given shape usually, be placed on then and be with on 208.
Also shown in Fig. 2 A, the lead frame 202 of some execution mode comprises one or more lead-in wires 214, but does not comprise the die attach pad.In this way, the technology 200 of Fig. 2 and lead frame 202 are different from technology 100 and the lead frame 102 of Fig. 1.Yet similar with Fig. 1, lead-in wire 214 parts of lead frame 202 additionally comprise the shape of step, layering and/or multistage formation among Fig. 2.Step preferably uses photoresist and partial etching technology to form.Formation have the lead-in wire 214 but do not have the lead frame 202 of tube core pad after, additional belt layer 208.
Fig. 2 B shows the technology that is used to form lead frame 202.This technology is applicable to the lead frame that forms any execution mode of the present invention.The lead frame piece 270 of copper, alloy or other suitable materials is provided.Lead frame piece 270 is preferably in the scope of 127 to 500 micron thickness.Use traditional photoresist technology, the photoresist material is applied to each face of lead frame piece 270.In common mode photoresist is carried out mask, exposure and development, to form photoresist mask element 272.By photoresist mask element 272, lead frame piece 270 is etched into the part of its thickness, and preferably remove its thickness at least half.Preferably, etching is a wet-etching technology, and forms lead frame 271.
Alternatively, can carry out plating to strengthen bonding to the part of lead frame 271.Can utilize at least 1.27 microns silver (Ag) to come the zone 280 shown in plating Fig. 2 B to be used for bonding.Alternatively, can utilize three layers of plating of the gold (Au) of at least 0.5 micron nickel (Ni), at least 0.01 micron palladium (Pd) and at least 30 dusts to substitute silver and come plating zone 280, to be used for bonding.Usually after forming lead-in wire, be formed for strengthening the plating of bonding.
Equally, alternatively, part that can the plating lead frame is to strengthen the welding with circuit board.Can utilize at least 7.62 microns slicker solder (tin-lead) to come plating zone 282 to be used for the plate weldering.Alternatively, can utilize at least 7.62 microns inferior light tin (matte tin) to come plating zone 282 to be used for the plate weldering.As the 3rd alternative, can utilize three layers of plating of the gold (Au) of at least 0.5 micron nickel (Ni), at least 0.01 micron palladium (Pd) and at least 30 dusts to substitute silver and come plating zone 282, to be used for the plate weldering.These plating and alternative are applicable to the plating zone that forms any execution mode of the present invention.Preferably, being completed into encapsulation and removing and be with after 208, carry out the plating that is used for the reinforcement plate weldering.
Therefore, no matter the mode that forms lead frame 202 how, after step 210, technology 200 goes to step 220, preferably by adhesive 223 semiconductor element 222 is attached at this and is with 208.Then wire bond 224 is coupled between semiconductor element 222 and lead-in wire 214.As mentioned above, lead frame 202 generally includes and is used to go between 214 zone, but does not have the tube core pad.Valuably, because the lower position of tube core 222 for lead-in wire 214, the thickness of encapsulation is the thickness of lead frame 202.
After step 220 was carried out die attach and/or wire bond, technology 200 went to step 230, used mold 232 at this.Usually, mold 232 comprises plastic polymer or resin, and the top surface of its envelope pressure pipe core 222, wire bond 224 and lead frame 202 comprises lead-in wire 214.
In case used mold 232 in step 230, technology 200 goes to step 240, removes at this and is with 208.Be with at 208 o'clock removing, expose the basal surface of tube core adhesive 223 and lead frame 202 usually, comprise lead-in wire 214.
After going to be with step 240, technology 200 goes to step 250, and the individual encapsulation unit that is comprised in this cuts apart the mold bar is to form individual semiconductor packages.Then, technology 200 finishes.As mentioned above, will be discussed in more detail cutting apart in conjunction with Figure 28.Thus, encapsulation is only the same with lead frame thick.The thickness of lead frame is preferably in 127 to 500 micrometer ranges.
C. flip-chip (replacing the bonding wiring) by using soldered ball
Fig. 3 shows controlled collapsible chip connec-tion in embodiments.Fig. 3 A shows the example results of each step in the technology of Fig. 3.As shown in these figures, technology 300 starts from step 310, forms lead frame 302 at this.Lead frame 302 generally includes copper, 42 alloys or other suitable materials, and has the typical thickness in 127 to 500 micrometer ranges.Be similar to the above step 210 of Fig. 2, form lead frame 302 and comprise alternatively plating is carried out in one or more zones of lead frame 302.As shown in Figure 3A, form the lead frame 302 of given shape usually, be placed on then and be with on 308.
Also as shown in Figure 3A, the lead frame 302 of some execution mode comprises one or more lead-in wires 314, but does not comprise the die attach pad.Be similar to Fig. 2, lead-in wire 314 parts of lead frame 302 additionally comprise the shape of step, layering and/or multistage formation among Fig. 3.Thus, in step 310, the technology 300 of Fig. 3 and lead frame 302 are similar to technology 200 and the lead frame 202 of the Fig. 2 of step 210 place.Yet after step 310, technology 300 is different with technology 200.Thus, has lead-in wire 314 but after not having the lead frame 302 of tube core pad, technology 300 continues with the step that is different from above-described technology 200 in formation.
Thus, no matter the mode that forms lead frame 302 how, after step 310, technology 300 goes to step 320, carries out die attach at this.As mentioned above, lead frame 302 generally includes and is used to go between 314 zone, but does not have the tube core pad.Thus, as shown in Fig. 3 A, die attach generally includes with the flip-chip form and by using soldered ball 324 tube core 322 is coupled directly to lead-in wire 314.Thus, as shown in the figure, do not need wire bond.Thus, some execution mode does not need the above additional bond wiring gap of tube core, and this can further reduce the overall height of encapsulation.
After step 320 was carried out die attach and/or lead-in wire bonding, technology 300 went to step 330, uses mold 332 at this.Usually, mold 332 comprises plastic polymer or resin, and the top surface of its plastic packaging tube core 322, soldered ball 324 and lead frame 302 comprises lead-in wire 314.
In case used mold 332 in step 330, technology 300 goes to step 340, removes at this and is with 308.Be with at 308 o'clock removing, expose the basal surface of lead frame 302 usually, comprise lead-in wire 314.
After going to be with step 340, technology 300 goes to step 350, and the individual encapsulation unit that is comprised in this cuts apart the mold bar is to form individuality (the flip-chip pattern) semiconductor packages.Then, technology 300 finishes.To be described further cutting apart in conjunction with Figure 28.Thus, encapsulation is only the same with lead frame thick.The thickness of lead frame is preferably in 127 to 500 microns scope.
Those of ordinary skill in the art will recognize respectively to the technology 100,200 of Fig. 1-Figure 1A, Fig. 2-Fig. 2 A and Fig. 3-Fig. 3 A and 300 distortion.For example, in the step 310 of Fig. 3, alternatively, form the tube core pad along lead-in wire 314.In these execution modes, step 320 further comprises alternatively: by one or more soldered balls of use flip-chip pattern and/or by using one or more wire bond that tube core 322 is bonded to the tube core pad.According to the various exemplary encapsulating products of being discussed in the following trifle, will be further understood that these process distortions.
II. example package configuration
Fig. 4-Figure 11 shows the example package that the method for execution mode is produced in more detail.More specifically, Fig. 4 shows encapsulation 400, and it has the tube core 422 of exposure, and is exposed to the top of encapsulation 400 and the lead-in wire 414 of bottom.Because encapsulation 400 does not have die attach pad 412, so some execution mode generates encapsulation 400 by the distortion of using above the technology of describing in conjunction with Fig. 2 and Fig. 2 A 200.As shown in Figure 4, encapsulation 400 does not comprise die attach pad 412 and tube core adhesive.Thus, tube core 422 directly is exposed to encapsulation 400 bottom, but is the bonding wirings 424 that tube core 422 are coupled to lead-in wire 414 to encapsulating only other contributions of total height of 400.As shown in the figure, the lead-in wire 414 of this execution mode comprises step or sandwich construction, makes connect up 424 height of height and the tube core 422 and the bonding of lead-in wire 414 be complementary, and does not add or contribute encapsulating 400 height.Particularly, lead-in wire 414 ground floor is approximately the height of tube core 422, and the second layer is approximately the bonding that tube core 422 the is coupled to lead-in wire 414 424 required interval height that connect up.And bonding wiring 424 also comprises slim design, and such as by comprising bent angle, it for example minimizes its height valuably.
Fig. 4 comprises top, bottom and sidepiece (section) view of encapsulation 400.Fig. 4 A and Fig. 4 B show additional sidepiece (section) view at the alternative of the lead-in wire 414 of different execution modes.
More specifically, Fig. 4 A shows lead-in wire 414 and mold 432 Fig. 4 at place, encapsulation 400 base angles with top and bottom-exposed and encapsulates 400.
Fig. 4 B shows lead-in wire 414 and mold 432 Fig. 4 at encapsulation 400 drift angle places with top and bottom-exposed and encapsulates 400.The alternative configurations of the mold 432 shown in Fig. 4, Fig. 4 A and Fig. 4 B is by using specific distortion to generate in the step of above-described technology (100,200,300).These distortion will further be discussed in conjunction with Figure 28 hereinafter.The distortion of the package design shown in Fig. 4 A and Fig. 4 B helps to make the mold 432 interior lead frame of grappling potting resin better.
Fig. 5 shows the encapsulation of tube core 522 Fig. 4 on adhesive phase 523 tops.Thus, some execution mode adopts the distortion of the technology 200 of above-described Fig. 2 to produce the encapsulation 500 shown in Fig. 5.Similarly, Fig. 5 A shows and has the encapsulation 500 at the Fig. 5 at place, encapsulation 500 base angles of top and bottom-exposed lead-in wire 514 and mold 532.Fig. 5 B shows has the encapsulation 500 at the Fig. 5 at drift angle place of top and bottom-exposed lead-in wire 514 and mold 532.
Fig. 6 shows has the encapsulation of Fig. 5 that tube core 622 is coupled to the die attach welding block 623 of tube core pad 612.Because the encapsulation 600 of Fig. 6 comprises tube core pad 612, some execution mode adopts the encapsulation 600 of above producing Fig. 6 in conjunction with the technology 100 of Fig. 1 description.
Fig. 6 A shows has top and bottom-exposed lead-in wire 614 and mold 632 Fig. 6 at the place, base angle encapsulates 600.Fig. 6 B shows has the encapsulation 600 at the Fig. 6 at drift angle place of top and bottom-exposed lead-in wire 614 and mold.
Fig. 7 shows the encapsulation 700 of flip-chip form, and it has the tube core 722 that is coupled to lead-in wire 714 by soldered ball 724 (and nonbonding wiring).As shown in the drawing, tube core 722 is exposed to the soldered ball facing surfaces and encapsulates 700 top.By exposed die 722, the heat extraction of tube core 722 is enhanced.Because the encapsulation that encapsulation 700 utilizes the flip-chip form, some execution mode adopt above the distortion of the technology of describing in conjunction with Fig. 3 300 to produce encapsulation 700.
Fig. 7 A shows has the encapsulation 700 at the Fig. 7 at place, base angle of top and bottom-exposed lead-in wire 714 and mold 732.Fig. 7 B shows has the encapsulation 700 at the Fig. 7 at drift angle place of top and bottom-exposed lead-in wire 714 and mold 732.
Fig. 8 shows the Flip-Chip Using that tube core 822 does not have Fig. 7 of exposure.Use pad or supporting disk (pillar bump) 824 that tube core 822 is coupled to lead-in wire 814.Fig. 8 A shows has top and bottom-exposed lead-in wire 814 and mold 832 Fig. 8 at the place, base angle encapsulates 800.Fig. 8 B shows has top and bottom-exposed lead-in wire 814 and mold 832 Fig. 8 at the drift angle place encapsulates 800.
Fig. 9 shows the Flip-Chip Using of Fig. 7, has the tube core 922 that (top) exposes, and it is coupled to the tube core pad 912 that is exposed to encapsulation 900 bottoms via soldered ball 924.Fig. 9 A shows has the encapsulation 900 at the Fig. 9 at place, base angle of top and bottom-exposed lead-in wire 914 and mold 932.Fig. 9 B shows has the encapsulation 900 at the Fig. 9 at drift angle place of top and bottom-exposed lead-in wire 914 and mold 932.
Figure 10 shows the encapsulation of Fig. 9, and wherein tube core 1022 is not exposed to the top of encapsulation 1000.Figure 10 A shows has top and bottom-exposed lead-in wire 1014 and mold 1032 Figure 10 at the place, base angle encapsulates 1000.Figure 10 B shows has the encapsulation 1000 at the Figure 10 at drift angle place of top and bottom-exposed lead-in wire 1014 and mold 1032.
The stacked die that shows Figure 11 realizes 1100, and it has the lead-in wire 1114 of top and bottom-exposed, its (by bonding wiring 1124) wire bond to two tube core 1122 and 1125 each.Figure 11 A shows has the encapsulation 1100 at the Figure 11 at place, base angle of top and bottom-exposed lead-in wire 1114 and mold 1132.Figure 11 B shows has the encapsulation 1100 at the Figure 11 at drift angle place of top and bottom-exposed lead-in wire 1114 and mold 1132.
As shown in figure 11, some execution mode supports the slim encapsulation of a plurality of and/or stacked die to realize.Some execution mode is also supported the realization according to a plurality of slim encapsulation of stacked or " laminate packaging (package-on-package) " configuration.These configurations have additional special characteristic.For example, some execution mode is included in the tube core of one or more exposures of slim encapsulation and/or the lead-in wire of exposure, and this allows the ad-hoc location (although encapsulation is stacked) in the visit encapsulation, and/or promotes the stacked of encapsulation.These features will further describe in conjunction with following accompanying drawing.Example among Fig. 4-Figure 11 is exclusive absolutely not, and within the spirit and scope of the present invention, much other distortion are feasible.
III. exemplary stacked or laminate packaging configuration
Because above the example package 400-1100 that describes in conjunction with Fig. 4-Figure 11 has a plurality of advantages that comprise little shape factor and/or slim dimension, therefore when combination realizes and/or be specific, technology (100,200,300) and encapsulation 400-1000 will have further advantage.This type of execution mode for example comprises stacked and/or the laminate packaging configuration.Figure 12-Figure 25 shows the stacked or laminate packaging (PoP) of using some above-mentioned encapsulation and realizes.
Particularly, Figure 12 shows the encapsulation 400 according to two Fig. 4 of stacked and/or laminate packaging configuration.As shown in the drawing, two encapsulation 400U (on) and 400L (descend) vertically stacked, the bottom contiguous of exposed leads 414U of the top of exposed leads 414L of the low 400L of encapsulation and the higher 400U of encapsulation made.Yet other features of this execution mode (such as tube core 422 and bonding wiring 424) are remained by mold 432 and separate.Valuably, some execution mode provides electricity, heat and/or other connections between lead-in wire 414U and 414L.
Similarly, Figure 13 shows encapsulation 500U and the 500L according to two Fig. 5 of stacked configuration, and the exposed surface of wherein go between 514U and 514L is contiguous.
The encapsulation 500U that Figure 14 shows Fig. 5 is stacked and placed on the encapsulation 500L top of another Fig. 5.Yet lower encapsulation 500L is inverted, and makes to hang down the bottom of encapsulation 500L and the bottom contiguous of the higher 500U of encapsulation.In this configuration, two tube core adhesive 523U and 523L that encapsulate the bottom-exposed of 500U and 500L are coupled in opposite directions and/or alternatively.And the bottom surface of exposed leads 514U and 514L is contiguous.
Figure 15 shows the encapsulation 600 according to two Fig. 6 of stacked configuration.
The encapsulation 600U that Figure 16 shows inverted Fig. 6 is stacked on the encapsulation 600L top of inverted Fig. 6 not, the top surface adjacency that makes two encapsulation (600U and 600L).In this configuration, the top of exposed leads 614U and 614L is adjacent to each other and/or is communicated with.As mentioned above, connection comprises electricity, heat or other useful connections.
Individuality encapsulation a plurality of, stacked or the laminate packaging configuration comprises identical and/or different forms and type.For example, Figure 17 shows Fig. 4 and encapsulates 400U and be stacked in Fig. 5 and encapsulate on the 500L top.In another example, Figure 18 shows Fig. 7 and encapsulates 700U and be stacked in Fig. 6 and encapsulate on the 600L top.In addition, Figure 19 shows Fig. 9 and encapsulates 900U and be stacked in Fig. 6 and encapsulate on the 600L top.
In other configurations, the encapsulation 600U that Figure 20 shows Fig. 6 is inverted and is stacked on the encapsulation 900L top of Fig. 9, makes two top surface adjacency that encapsulate 600U and 900L.The encapsulation 600U that Figure 21 shows Fig. 6 is inverted and is stacked on the encapsulation 900L top of inverted Fig. 9.The encapsulation 600U that Figure 22 shows Fig. 6 is stacked in the distortion on the encapsulation 600L top of Fig. 6.As shown in the drawing, encapsulation 600U has the tube core pad 612U and/or the lead-in wire 614U of given shape.Alternatively, this given shape by Fig. 1, Fig. 2 and Fig. 3 separately technology 100,200 and/or the distortion in 300 processes form.
The encapsulation 600U that Figure 23 shows Fig. 6 is stacked in another distortion on the encapsulation 600L top of Fig. 6.Be similar to Figure 23, the encapsulation 600U that Figure 24 shows Fig. 6 is stacked in the distortion on the encapsulation 500L top of Fig. 5.
Be similar to Figure 22, the encapsulation 600U that Figure 25 shows Fig. 6 is stacked in the distortion on the encapsulation 600L top of Fig. 6.In Figure 25, be inverted lower encapsulation 600L, make the exposure adjacency of two tube core 612U and 612L and lead-in wire 614U and 614L.
In addition, above-described laminate packaging configuration is not limited to two stack package.For example, Figure 26 shows a kind of like this distortion, and wherein the encapsulation 600U of Fig. 6 is stacked on the encapsulation 700M top of Fig. 7, and encapsulation 700M is stacked on the encapsulation 600L top of Fig. 6.In these execution modes, because having, middle encapsulation 700M is exposed to the two lead-in wire 714M of top and bottom, therefore lead-in wire 614U, 714M and the 614L of all three encapsulation (higher 600U, middle 700M and lower 600L) communicate with each other valuably.
Similarly, Figure 27 shows a kind of like this distortion, and wherein Fig. 6 encapsulates on the encapsulation 600M top that 600U is stacked in inverted Fig. 6, and encapsulation 600M is stacked on the encapsulation 600L top of inverted Fig. 6 not.As shown in the drawing, lead-in wire 614U, 614M and 614L are communicated with.In addition, higher 600U and middle 600M packaged die pad 612U and 612M are also toward each other and/or be communicated with.Example among Figure 12-Figure 27 is exclusive absolutely not, and within the spirit and scope of the present invention, multiple other distortion are feasible.
IV. advantage
As mentioned above, technology 100,200 produces different encapsulation with 300, and every kind of encapsulation has different attributes and advantage.In each case, the height of encapsulation is identical with lead frame.Technology 200 forms the encapsulation that step 310 produces does not have the die attach pad at lead frame.Some execution mode also forms step (110,210,310) or provides distortion to encapsulation such as other steps of segmentation procedure (150,250,350) at lead frame.Particularly, Figure 28 shows some execution mode and is used for shown in the production drawing 4 method of encapsulation.Figure 28 A shows some execution mode and is used for forming the method that encapsulates shown in Fig. 4 A.Figure 28 B shows some execution mode and is used for forming the method that encapsulates shown in Fig. 4 B.Shown in Figure 28, Figure 28 A and Figure 28 B, these execution modes form the encapsulation of cutting apart by using various means, for example, have the lead frame of different shape by initial formation.Then, the lead frame of envelope being pressed in different positions is cut apart, and presses shape with the envelope that produces expectation.
In addition, Fig. 4-Figure 27 shows various top views, bottom view and/or the end view according to the configuration of numerous embodiments of the present invention.In these execution modes some forms by using above-described technology 100,200 and/or 300.As mentioned above, these encapsulation 400-2700 has a plurality of advantages.
(1) for example, as mentioned above, the manufacturing step that technology (100,200,300) has is less than conventional method known in the art.Therefore technology (100,200,300) has less step, so it is than technology cheapness known in the art.And because technology (100,200,300) has less step, it is also fast than other technologies usually, perhaps in other words, has higher output.
(2) technology (100,200,300) can access the package dimension near the yardstick of packaged tube core in the encapsulation.It will be appreciated by those skilled in the art that the advantage that reduces package dimension.For example, floor space be similar to the erection space required on the circuit board that is encapsulated in of its die-size can be more not too many greatly than the approx. dimension of tube core.Thus, this advantage allows more semiconductor device is placed on the plate, or uses less circuit board, and this will obtain the application of less shape factor usually, and additional size and/or cost savings, such as shipment and the manufacturing cost owing to reduction.
(3) in addition, thickness uses the slim realization of this type of little profile and/or slim encapsulation near the encapsulation support of the die thickness of the inner envelope pressure of encapsulation.
(4) because the key factor relevant with the height of technology 100 formed encapsulation normally height or other factors of tube core, therefore the height of lead-in wire does not influence for the height of encapsulation or has an insignificant influence.In fact, compare lead-in wire with the height of encapsulation and/or tube core and have zero or almost nil height.
(5) and, because technology 100 has less step, and the approaching dimensionally usually little plastic packaging tube core of its product, therefore encapsulation shown and described herein provides the saving of the volume of the constituent material of consumption in time, perhaps in other words, provide higher output.And various a plurality of possible package arrangements that above-mentioned technology 100,200 and 300 is supported have obtained other advantages.
Although described the present invention with reference to a plurality of specific detail, it will be recognized by those of ordinary skills, can under the situation that does not break away from spirit of the present invention, specialize the present invention with other concrete forms.Thus, one of ordinary skill in the art will appreciate that the present invention is not subjected to the restriction of preamble illustrative details, but limit by claims.

Claims (36)

1. encapsulation comprises:
(a) first semiconductor element;
(b) have a plurality of lead frames of formation that formed lead-in wire, each lead-in wire has first end and second end, it is neighbouring but spaced away that described first end is positioned at described first semiconductor element, and be in first planar horizontal basically, and described second end is in second planar horizontal basically, and wherein said second planar horizontal is higher than described first planar horizontal;
(c) electric coupling device is used for carrying out electric coupling between at least one pad on described first semiconductor element and at least one described first end; And
(d) around described first semiconductor element and the resin that between described lead-in wire, forms, make described encapsulation have the thickness that equates basically with the thickness of described lead frame.
2. encapsulation according to claim 1, wherein said lead frame and described encapsulation have the thickness in 127 to 500 micrometer ranges.
3. encapsulation according to claim 1, wherein said second end in the top of described encapsulation and bottom-exposed in the edge of described encapsulation.
4. encapsulation according to claim 1, wherein said second end is at the top of described encapsulation, still not at the edge of its bottom-exposed in described encapsulation.
5. encapsulation according to claim 1, wherein said second end in the bottom of described encapsulation, but be not exposed to the edge of described encapsulation at its top.
6. the amount that encapsulation according to claim 1, wherein said second planar horizontal are higher than described first planar horizontal is thicker than described first semiconductor element.
7. the amount that encapsulation according to claim 1, wherein said second planar horizontal are higher than described first planar horizontal is thinner than described first semiconductor element.
8. the amount that encapsulation according to claim 1, wherein said second planar horizontal are higher than described first planar horizontal is the same thickness of described first semiconductor element basically.
9. encapsulation according to claim 1, wherein said first semiconductor element is squeezed, and flip-chip is bonded to one or more described first ends.
10. encapsulation according to claim 9, the dorsal part of wherein said first semiconductor element exposes.
11. encapsulation according to claim 9, wherein said bonding is formed by soldered ball.
12. encapsulation according to claim 9, wherein said bonding is formed by supporting disk.
13. encapsulation according to claim 9, the dorsal part of wherein said first semiconductor element is covered by described resin.
14. encapsulation according to claim 1, the dorsal part of wherein said semiconductor element are exposed between described first end, and described electric coupling device comprises wire bond.
15. encapsulation according to claim 14 further comprises: second semiconductor element, at least one pad of wherein said second semiconductor element and at least one the described lead-in wire electric coupling that are stacked on described first semiconductor element and isolate with its electricity.
16. encapsulation according to claim 1 further comprises: with described first end die attach pad of coplane basically, wherein said semiconductor element is installed on the described die attach pad, and described electric coupling device comprises wire bond.
17. encapsulation according to claim 1 further comprises:, make the described lead-in wire of an encapsulation and the described lead-in wire positioned adjacent and the electric coupling of another encapsulation by stacked at least two systems of forming of encapsulation.
18. encapsulation according to claim 1 further comprises: in order to strengthen plating face bonding, on the described lead-in wire.
19. encapsulation according to claim 1 further comprises: in order to plating face reinforcement plate weldering, on the described lead frame.
20. a method that forms encapsulation comprises:
(a) provide first semiconductor element;
(b) formation has a plurality of lead frames that formed lead-in wire, each lead-in wire has first end and second end, it is neighbouring but spaced away that described first end is positioned at described first semiconductor element, and be in first planar horizontal basically, and described second end is in second planar horizontal basically, and wherein said second planar horizontal is higher than described first planar horizontal;
(c) between at least one pad on described first semiconductor element and at least one described first end, carry out electric coupling; And
(d) around described first semiconductor and between described lead-in wire, form resin, make described encapsulation have the thickness that equates basically with the thickness of described lead frame.
21. method according to claim 20, wherein said lead frame and described encapsulation have the thickness in 127 to 500 micrometer ranges.
22. method according to claim 20, described second end in the top of described encapsulation and bottom-exposed in the edge of described encapsulation.
23. method according to claim 20, described second end is at the top of described encapsulation, still not at the edge of its bottom-exposed in described encapsulation.
24. method according to claim 20, described second end in the bottom of described encapsulation, but be not exposed to the edge of described encapsulation at its top.
25. it is thicker than described first semiconductor element that method according to claim 20, wherein said second planar horizontal are higher than the amount of described first planar horizontal.
26. it is thinner than described first semiconductor element that method according to claim 20, wherein said second planar horizontal are higher than the amount of described first planar horizontal.
27. it is the same thickness of described first semiconductor element basically that method according to claim 20, wherein said second planar horizontal are higher than the amount of described first planar horizontal.
28. method according to claim 20, wherein said first semiconductor element is squeezed, and flip-chip is bonded to one or more described first ends.
29. method according to claim 28 wherein exposes the dorsal part of described first semiconductor element.
30. method according to claim 28 wherein utilizes resin to cover the dorsal part of described first semiconductor element.
31. method according to claim 20, the dorsal part of wherein said first semiconductor element are exposed between described first end, and use wire bond to be used for electric coupling.
32. method according to claim 31 further comprises: second semiconductor element, at least one pad of wherein said second semiconductor element and at least one the described lead-in wire electric coupling that are stacked on described first semiconductor element and isolate with its electricity.
33. method according to claim 20 further comprises: with described first end die attach pad of coplane basically, wherein said semiconductor element is installed on the described die attach pad, and uses wire bond to be used for electric coupling.
34. method according to claim 20 further comprises:, make the described lead-in wire of an encapsulation and the described lead-in wire positioned adjacent and the electric coupling of another encapsulation by stacked at least two systems of forming of encapsulation.
35. method according to claim 20 further comprises: the face on the described lead-in wire of plating is to strengthen bonding.
36. method according to claim 20 further comprises: the face on the described lead frame of plating welds with reinforcement plate.
CN2010101288003A 2010-03-08 2010-03-08 Ultrathin semiconductor package Pending CN102194770A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108630654A (en) * 2017-03-23 2018-10-09 恩智浦美国有限公司 Semiconductor device and forming method thereof with ripple lead

Citations (1)

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Publication number Priority date Publication date Assignee Title
CN101512762A (en) * 2006-08-28 2009-08-19 爱特梅尔公司 Stackable packages for three-dimensional packaging of semiconductor dice

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101512762A (en) * 2006-08-28 2009-08-19 爱特梅尔公司 Stackable packages for three-dimensional packaging of semiconductor dice

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108630654A (en) * 2017-03-23 2018-10-09 恩智浦美国有限公司 Semiconductor device and forming method thereof with ripple lead

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Application publication date: 20110921