CN102195574A

CN102195574A - Power amplifier device

Info

Publication number: CN102195574A
Application number: CN2011100487837A
Authority: CN
Inventors: 川上刚史; 西川和康
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2010-02-26
Filing date: 2011-02-25
Publication date: 2011-09-21
Also published as: TW201203842A; US8183930B2; US8416022B2; JP2011182107A; US20120262237A1; US20110210792A1

Abstract

The present invention provides a power amplifier device, which simultaneously satisfies the requirements of providing high output and reducing the chip area occupied by the power amplifier device. A power amplifier device formed over a substrate includes a primary inductor, a ground pattern, a transistor pair, and a secondary inductor arranged in a generally ring-shaped geometric pattern. The ground pattern is arranged to extend from a portion of an area inside the annular primary inductor to an area outside the primary inductor when viewed from a direction perpendicular to the substrate and to ground at multiple points in the area. First main electrodes of a first transistor and a second transistor forming a pair of transistors connected to the primary inductors are respectively coupled to two ends of each primary inductor. Second main electrodes of the first and second transistors are coupled to the ground pattern in a region inside the primary inductor and are in electrical conduction with the corresponding plurality of ground points.

Description

Power amplifier element

The cross reference of related application

By with reference to whole disclosures of introducing the 2010-42840 Japanese patent application of submitting on February 26th, 2010, comprise specification, accompanying drawing and summary at this.

Technical field

The present invention relates to input signal is amplified to the power amplifier element of required voltage level.

Background technology

For for the communication equipment the mobile telephone terminal, important challenge is the shared area of reduction power amplifier element and other installed with built-in component and reduces its cost.For example, unexamined 2005-503679 Japanese Patent Application Publication text (cypher text of PCT application) (patent documentation 1) discloses the distributed power amplifier device that is used for amplifying effectively and at low cost radio frequency (RF) signal.

Power amplifier element according to top document comprises a plurality of push-pull amplifiers, and described a plurality of push-pull amplifiers are coupled to each other to form circular geometry.Amplitude equates but the opposite input signal of phase place inputs to the contiguous amplifier (transistor) in each push-pull amplifier.The closed loop that is formed by the described a plurality of push-pull amplifiers of coupling plays elementary winding.Described power amplifier element also comprises the geometric secondary winding that is suitable for described elementary winding.The power of synthetic effectively each the described push-pull amplifier output of described secondary winding.

[prior art document]

[patent documentation]

[patent documentation 1]

Unexamined 2005-503679 Japanese Patent Application Publication text (cypher text of PCT application)

Summary of the invention

In the power amplifier element of describing in the superincumbent patent documentation, described transistor is arranged in the zone of transformer outside.Yet, consider that power amplifier element provides the power output of several watts of magnitudes, be used to settle the described transistorized gross area to become big.Top layout runs into the shared chip area of whole power amplifier element and becomes big problem.

A target of the present invention provides a kind of power amplifier element of following type, the right output of a plurality of transistors of the synthetic differential operation of this power amplifier element, described power amplifier element are satisfied simultaneously provides high output and reduction by the shared chip area of described device.

The present invention is summarized as follows.Power amplifier element is formed on the substrate, comprise primary inductor, grounding pattern, a plurality of transistor to and secondary inductor.Described primary inductor comprises and being set to when being a plurality of inductor elements of circular geometry substantially when observing perpendicular to the direction of described substrate.Described grounding pattern is configured to extend in the zone of described primary inductor outside when the part from the zone of the described primary inductor inside of ring-type when observing perpendicular to the direction of described substrate, and a plurality of somes place ground connection in the zone of described primary inductor outside.Right each of described a plurality of transistor is connected with in described a plurality of inductor elements each being configured to.First main electrode that forms right the first transistor of the transistor be connected with described inductor element and transistor seconds is coupled respectively to each two ends of described a plurality of inductor elements.Second main electrode of described the first transistor and transistor seconds is coupled to the described grounding pattern in the zone of described primary inductor inside, and conducts with corresponding a plurality of points.Provide as the first paired signal of differential input signal and secondary signal to control the electrode of described the first transistor and transistor seconds respectively.Provide the secondary inductor that comprises a circle winding or multicircuit winding to make annularly, and secondary inductor also synthesize and export described first signal that synthesizes and the composite signal of secondary signal in each described inductor element by magnetic coupling to described primary inductor around described primary inductor.

According to the present invention, a plurality of transistors are to being arranged in the zone in the transformer, and described transformer is made of primary inductor and secondary inductor, and perhaps described a plurality of transistors are in the zone that is arranged in described transistor pair and these inductors and overlaps.Therefore, the shared chip area of described power amplifier element can be made into less than the known up to now shared chip area of the power amplifier that contrasts.In addition, according to the present invention, be coupled to a plurality of somes place ground connection of grounding pattern in the zone of described transformer outside of described transistorized second electrode.Therefore, can reduce dead resistance and stray inductance in the path between described second electrode and the described ground connection node.Can prevent the reducing of output of described power amplifier element.

Description of drawings

Fig. 1 shows the circuit diagram based on the power amplifier of transformer, and wherein, turn ratio is 1: the n level of m is together transformer coupled;

Fig. 2 shows the plane graph of configuration of the power amplifier element 300 of first embodiment of the invention;

Fig. 3 A, Fig. 3 B and Fig. 3 C show the plane graph of each assembly of the power amplifier element 300 among Fig. 2;

Fig. 4 shows the plane graph of primary inductor 104 parts of choosing from Fig. 3 A;

Fig. 5 is the schematic cross section in order to the cross-sectional structure that power amplifier element 300 shown in Figure 2 is described;

Fig. 6 A and Fig. 6 B are the plane graphs that illustrates in greater detail transistor Q1p structure;

Fig. 7 is the equivalent circuit diagram of the power amplifier element 300 of Fig. 2;

Fig. 8 shows the figure of conduct at the configuration of first comparative example's of described first execution mode power amplifier element 300A;

Fig. 9 shows the figure of conduct at the configuration of second comparative example's of described first execution mode power amplifier element 300B;

Figure 10 shows the circuit diagram as the configuration of the power amplifier element of first embodiment that described first execution mode is made amendment;

Figure 11 shows the plane graph as the grounding pattern 102a of second embodiment that described first execution mode is made amendment;

Figure 12 shows the plane graph as the grounding pattern 102b of the 3rd embodiment that described first execution mode is made amendment;

Figure 13 shows the plane graph according to the configuration of the power amplifier element 301 of second embodiment of the invention;

Figure 14 shows the primary inductor plane graph of choosing from Figure 13 partly;

Figure 15 shows the grounding pattern plane graph of choosing from Figure 13 partly;

Figure 16 shows the plane graph as the configuration of the grounding pattern 202a of the embodiment that grounding pattern among Figure 15 202 is made amendment;

Figure 17 shows the plane graph as the configuration of the grounding pattern 202b of another embodiment that grounding pattern among Figure 15 202 is made amendment;

Figure 18 shows the plane graph according to the configuration of the power amplifier element 302 of first embodiment that second execution mode of the present invention is made amendment;

Figure 19 shows the primary inductor plane graph of choosing from Figure 18 partly;

Figure 20 shows the grounding pattern plane graph of choosing from Figure 18 partly;

Figure 21 shows the plane graph as the configuration of the grounding pattern 212a of the embodiment that grounding pattern among Figure 20 212 is made amendment;

Figure 22 shows the plane graph as the configuration of the grounding pattern 212b of another embodiment that grounding pattern among Figure 20 212 is made amendment;

Figure 23 shows the plane graph according to the configuration of the power amplifier element 303 of second embodiment that second execution mode of the present invention is made amendment;

Figure 24 shows the plane graph according to the configuration of the power amplifier element 304 of third embodiment of the invention;

Figure 25 shows the grounding pattern of choosing from Figure 24 150;

Figure 26 A and Figure 26 B are the figure that further specifies the effect of grounding pattern 150 among Figure 25;

Figure 27 shows the plane graph as the configuration of the grounding pattern 150a of the embodiment that grounding pattern among Figure 25 is made amendment;

Figure 28 A, Figure 28 B and Figure 28 C show the plane graph as the configuration of the power amplifier element of second embodiment that the 3rd execution mode of the present invention is revised;

Figure 29 shows the plane graph according to the configuration of the power amplifier element 306 of four embodiment of the invention; And

Figure 30 shows the plane graph of grounding pattern 109 parts of choosing from Figure 29.

Embodiment

Hereinafter, describe preferred implementation of the present invention with reference to the accompanying drawings in detail.Designated identical reference number of identical or corresponding part or identifier, and they are not repeated in this description.

＜the first execution mode 〉

[based on the principle of the power amplifier of transformer]

At first, describe to constitute the principle based on the power amplifier of transformer on basis of the present invention.

Fig. 1 shows the circuit diagram based on the power amplifier of transformer, and wherein having turn ratio is 1: the n level of m is together transformer coupled.Referring to Fig. 1, (AP1 is AN1) to (APn ANn), provides every pair of transistor to be used for being connected with each of transformer XF1 to XFn to transistor to comprise n (n is the integer more than 2 or 2) transformer XF1 to XFn and n based on the power amplifier of transformer.Transistor AP in the every pair of transistor, AN are coupled respectively to two ends with the elementary winding of the described transformer XF that this is connected transistor.The secondary winding of described transformer XF1 to XFn is coupled in series to load resistance RL.

Each amplifier is to AP, and AN is made of the NMOS of source ground (N NMOS N-channel MOS N) transistor (N channel insulated gate field).Hereinafter, amplifier is to AP, and AN also can be described as transistor to AP, AN.To AP, each grid of AN is imported differential wave to transistor, that is, but two opposite signal IN+ of the identical phase place of amplitude, IN-(first signal and secondary signal).

In the circuit arrangement of Fig. 1, be 1 by the coupling turn ratio: the n level transformer XF of m, can make described transistorized output voltage is 1/ (2mn).For example, suppose that the output of described power amplifier based on transformer is that 4W and load resistance RL are 50 Ω, the output voltage amplitude (0 to peak value) of the described transformer XF1 to XFn of its secondary windings in series coupling is 20V.In this case, the voltage amplitude at each transistor drain place becomes 10/mn V.At this moment, because the conversion amplitude (load impedance) of the load resistance RL at the elementary winding place of each transformer XF is 50/ (2m ²N) Ω, so each transistor drain current amplitude becomes 0.4mA, this does not depend on progression n.Therefore, the power amplifier based on transformer becomes the useful means that are used for providing by little CMOS technology realization the power amplifier element of several watts of magnitude power outputs.

[configuration of the power amplifier element 300 of first execution mode]

Fig. 2 shows the plane graph according to the configuration of the power amplifier element 300 of first execution mode of the present invention.Power amplifier element 300 shown in Figure 2 is formed on the substrate and comprises primary inductor (representing with reference number 104), secondary inductor 3, grounding pattern (representing with reference number 102) and two couples of transistor (Q1p in Fig. 3 in Fig. 3, Q1n) and (Q2p, Q2n), described primary inductor is made of inductor element 1,2.Hereinafter, the plane that is parallel to described substrate is assumed to the XY plane, and is assumed to the Z direction perpendicular to the direction of described substrate.In order to distinguish both direction along reference axis, make them be marked with positive sign and negative sign, for example+the Z direction and-the Z direction.

Fig. 3 A), Fig. 3 B and Fig. 3 C show the plane graph of each assembly of Fig. 2 intermediate power amplifier device 300.Fig. 3 A is the plane graph of the transformer 101 that is made of primary inductor 104 and secondary inductor 3.Fig. 3 B is the plane graph of grounding pattern 102.Fig. 3 C be schematically illustrated transistor to Q1p, Q1n and Q2p, the figure of the layout of Q2n (being referred to as amplifier 103).In the situation of described first execution mode, suppose that each transformer had turn ratio 1: 1 and the supposition two-stage is coupled.

Fig. 4 shows the plane graph of primary inductor 104 parts of choosing from Fig. 3 A.With reference to Fig. 4, primary inductor 104 is made of

inductor element

1,2, and the central shaft CP that described

inductor element

1,2 is set to wind perpendicular to described substrate is circular geometry substantially.The monnolithic case of elementary winding 104 is twice rotation (two-turn) symmetry around described central shaft CP, and is the minute surface symmetry about in symmetrical plane 9 and the symmetrical plane 10 each, and described symmetrical plane 9 and symmetrical plane 10 all are parallel to the XZ plane.An one end 1p of inductor element 1 and an end 2n of inductor element 2 are arranged as that to stride symmetrical plane 10 close to each other, and the other end 1n of inductor element 1 and the other end 2p of inductor element 2 are arranged as that to stride symmetrical plane 10 close to each other.

Referring again to Fig. 2 and Fig. 3 A, secondary inductor 3 is set annularly makes around primary inductor 104.The synthetic output that secondary inductor 3 produces the signal that has inputed to described inductor element by magnetic coupling to primary inductor 104.Provide in the situation of differential output at power amplifier element 300, differential wave is from two end 3p of

secondary inductor

3, and 3n exports.Provide in the situation of single-phase output at power amplifier 300, an end 3n ground connection, another end 3p exports single-phase output signal OUT.In a kind of situation in back, can be by end 3n is coupled to grounding pattern 102 via contact hole e with end 3n ground connection.Although the secondary inductor 3 shown in Fig. 2 and Fig. 3 A has a circle winding, secondary inductor 3 can have multicircuit winding.

Grounding pattern 102 comprises wiring portion 4 to 7 and bonding part 8.When observing perpendicular to the direction of described substrate, wiring portion 4 extends to the zone of transformer 111 outsides at directions X from central shaft CP vicinity along the symmetrical plane Fig. 49, and the end terminal ground connection of wiring portion 4.When observing perpendicular to the direction of described substrate, wiring portion 5 extends to the zone of transformer 101 outsides in the Y direction from central shaft CP vicinity along the symmetrical plane Fig. 4 10, and the end terminal ground connection of wiring portion 5.When observing perpendicular to the direction of described substrate, wiring portion 6 extends to the zone of transformer 101 outsides at directions X from central shaft CP vicinity along the symmetrical plane Fig. 49, and the end terminal ground connection of wiring portion 5.When observing perpendicular to the direction of described substrate, wiring portion 7 extends to the zone of transformer 101 outsides in the Y direction from central shaft CP vicinity along the symmetrical plane Fig. 4 10, and the end terminal ground connection of wiring portion 7.Bonding part 8 is arranged near the central shaft CP and connecting wiring part 4 to 7.

Transistor Q1p, Q1n, Q2p, Q2n realize by nmos pass transistor and be arranged to when from perpendicular to the direction observation of described substrate the time in inside, transformer 101 edge.When observing perpendicular to the direction of described substrate, the wiring of transformer 101 and each transistor can partly overlap.Right transistor is not limited to nmos pass transistor to form described transistor; But for example, they can be bipolar transistors.Each transistorized concrete coupling is as follows.

The drain electrode 1pd of transistor Q1p is coupled to the end 1p of inductor element 1 by contact hole f, and the source electrode 1ps of transistor Q1p is coupled to bonding part 8 by contact hole a.The drain electrode 1nd of transistor Q1n is coupled to the end 1n of inductor element 1 by contact hole g, and the source electrode 1ns of transistor Q1n is coupled to bonding part 8 by contact hole b.The drain electrode 2pd of transistor Q2p is coupled to the end 2p of inductor element 2 by contact hole h, and the source electrode 2ps of transistor Q2p is coupled to bonding part 8 by contact hole c.The drain electrode 2nd of transistor Q2n is coupled to the end 2n of inductor element 2 by contact hole i, and the source electrode 2ns of transistor Q2n is coupled to bonding part 8 by contact hole d.

By with each transistor to the inductor element that is connected to this transistor to Dc bias is provided.Particularly, as shown in Figure 2, to transistor Q1p, the Dc bias Vd that Q1n provides is applied near the centre cap 1c of mid point of inductor element 1.To transistor Q2p, the Dc bias Vd that Q2n provides is applied near the centre cap 2c of mid point of inductor element 2.

As the input signal IN+ of differential input signal, IN-inputs to transistor Q1p respectively, the gate electrode of Q1n and transistor Q2p, the gate electrode of Q2n.Thus, input signal IN+, IN-is by transistor Q1p, and Q1n is exaggerated, and is synthetic by inductor element 1 then.Similarly, input signal IN+, IN-is by transistor Q2p, and Q2n is exaggerated, and is synthetic by inductor element 2 then.Therefore further synthesize by secondary inductor 3 by

inductor element

1 and 2 synthetic signals, export from terminal 3p then.

Fig. 5 is the schematic cross section in order to the cross-sectional structure that power amplifier element 300 shown in Figure 2 is described.The schematic cross section of Fig. 5 is intended to illustrate the position of metal level and the coupling by contact hole, not strict plane graph corresponding to Fig. 2.

Referring to Fig. 5, use the first metal layer on substrate S UB to form transistor Q1p, Q1n, Q2p and Q2n.Second metal level of use on described the first metal layer forms grounding pattern 102.Three metal level of use on described second metal level forms transformer 101.

Form contact hole a, b, c and d come coupled transistor Q1p, Q1n, Q2p, Q2n and grounding pattern 102.Form contact hole f, g, h and i come coupled transistor Q1p, Q1n, Q2p, Q2n and inductor element 1.In this case, form the opening 7A shown in Fig. 3 B, 5A, 5B and 7B to be allowing contact hole f, g, and h and i are by described opening.

Fig. 6 A and Fig. 6 B are the plane graphs that illustrates in greater detail the structure of transistor Q1p.Fig. 6 A shows the position of drain electrode 1pd, source electrode 1ps and gate electrode 1pg, and Fig. 6 B shows p type impurity range 74, n type impurity range 75 and the channel separating zone 73 lip-deep position at described substrate S UB.Use the channel region of p type impurity range 74, and use n type impurity range 75 alternately as source area or drain region as nmos pass transistor.In Fig. 6 A and Fig. 6 B, the structure that transistor Q1p is shown is as representative; Apparently, other transistors Q1n, Q2p and Q2n have with at the same structure shown in this.

The aluminium wiring 70 that forms drain electrode 1pd is coupled to described drain region by a plurality of contact hole CT2.The aluminium wiring 71 that forms source electrode 1ps is coupled to described source area by a plurality of contact hole CT1.Form the transistor Q1p among Fig. 2 respectively, Q1n, the aluminium of the source electrode 1ps of Q2p and Q2n wiring 71 can form and intercouple together and for one.

Gate electrode 1pg comprises polysilicon layer 72 and is coupled to the aluminium wiring 77 of polysilicon layer 72 by contact hole CT3 that polysilicon layer 72 is stacked and placed on the top of the gate insulating film on the described channel region.Use the described the first metal layer of Fig. 5 to form aluminium wiring 77.In Fig. 6 A, illustrate for clear, mark described polysilicon layer with hacures.

[beneficial effect of power amplifier element 300]

According to above-mentioned power amplifier element 300, at first, by with transistor Q1p, Q1n, Q2p, Q2n is arranged in the zone of inside, transformer 101 edge, can make less than the known up to now shared chip area of the power amplifier element that contrasts by the chip area that described power amplifier element is shared.

Secondly, four wiring portion 4 to 7 provide transistor Q1p, Q1n, Q2p, the parallel coupled between the source electrode of Q2n and the ground connection node GND.Consequently, can reduce, and can suppress the reducing of output of power amplifier element 300 from the dead resistance and the stray inductance of described transistorized source electrode to the path of described ground connection node GND.

Once more, the wiring portion 4 to 7 that forms grounding pattern 102 runs through the minute surface

symmetrical plane

9 and 10 in the primary inductor 104 shown in Figure 4.Because minute surface

symmetrical plane

9 and 10 serves as and virtually in the difference operation exchanges ground connection, so the RF characteristic of transformer 101 less is subjected to the influence of wiring portion 4 to 7.Therefore, the width of described earth connection can be made into is wider than the width that described earth connection places the situation of other positions, and, the dead resistance can further reducing from described transistorized earth terminal to the path of ground connection.In addition, because grounding pattern 102 its integral body have the mirror symmetry matter that is similar to primary inductor 104, so unbalance differential operation is difficult to take place.Hereinafter, when providing specific embodiment and comparative example, the beneficial effect of power amplifier element 300 will be further described.

Fig. 7 is the equivalent circuit diagram of Fig. 2 intermediate power amplifier device 300.In Fig. 7, the transistor that shows inductor element 1 and be coupled to inductor element 1 is to Q1p, Q1n.

In Fig. 7, transistor Q1p, the conducting resistance of Q1n is expressed as Ron, and the ohmmeter of the wiring portion 4 to 7 of 8 to ground connection node GND parallel connection is shown Rs from the bonding part, and the inductance meter of wiring portion in parallel is shown Ls.In this case, be applied to each transistor Q1p, the direct voltage Vds (drain electrode-source voltage) of Q1n is expressed as following equation:

Vds＝Vd×(Ron/2)×(Ron/2+Rs)…(1)

From equation (1) as seen, along with dead resistance Rs increases, be applied to described transistorized direct voltage Vds and reduce.Consequently, the output OUT of described power amplifier element reduces.Yet, in the situation of the power amplifier element 300 of first execution mode, by several wiring portion 4 to 7 are provided, dead resistance Rs is made as much as possible little, thereby can suppress to export reducing of OUT.

In Fig. 7, the stray inductance Ls of described earth connection does not influence direct voltage, but described stray inductance has the so big impedance influences of ω Ls (wherein ω is an angular frequency) to the RF signal.In the situation of described first execution mode, if the differential operation of described power amplifier element is desirable, because virtual interchange ground connection is served as in bonding part 8, so stray inductance Ls is to the not influence of output OUT of power amplifier element 300.Yet if differential input signal IN+, IN-is asymmetric, if perhaps described characteristics of transistor changes in PCB surface, it is unbalance that the differential operation of described power amplifier element will become.In this case, as much as possible little by stray inductance Ls is made, can suppress to export reducing of OUT.

Fig. 8 shows the figure of conduct at the configuration of first comparative example's of described first execution mode power amplifier element 300A.In Fig. 8, show transistor Q1p, Q1n, Q2p, Q2n are arranged on the embodiment in the zone of transformer 101 outsides.

In this type of power amplifier element that right output is synthesized to the transistor of a plurality of differential operations, usually with transistor Q1p, Q1n, Q2p, Q2n are arranged in outside the described transformer, as shown in Figure 8.In this case, the common source electrode 81 of transistor Q1p and Q2n can be coupled to ground connection node GND by bonding line 80B, and the common source electrode 82 of transistor Q1n and Q2p can be coupled to ground connection node GND by bonding line 80A.Therefore, can reduce transistor Q1p, Q1n, Q2p, dead resistance and stray inductance in the path between the source electrode of Q2n and the ground connection node GND.Yet, owing to need bigger area to be used to provide the transistor of the power amplifier element of several watts of magnitude power outputs, so the chip area that becomes more shared than the power amplifier element of described first execution mode by as shown in Figure 8 the shared chip area of whole power amplifier element is bigger with arrangement.

In the power amplifier element 300 of described first execution mode, whole power amplifier element be designed to by with described transistor layout in the inside of described transformer to occupy littler chip area.In addition, the wiring portion 4 to 7 by being provided for ground connection makes about

symmetrical plane

9 and 10 minute surface symmetry vertically, can make dead resistance and stray inductance as much as possible little.

Fig. 9 shows the figure of conduct at the configuration of second comparative example's of described first execution mode power amplifier 300B.In Fig. 9, show transistor Q1p, Q1n, Q2p, the embodiment of Q2n are set in the zone in transformer 101.Yet, in the situation of Fig. 9,, bonding part 8 is coupled to ground connection node GND by single wiring portion 83 and bonding line 80D.

In the situation of Fig. 9, dead resistance that wiring portion 83 has and stray inductance are total dead resistance of the wiring portion 4 to 7 shown in Fig. 2 and at least 4 times of stray inductance.In addition, wiring portion 83 is placed as and is not in relation to

symmetrical plane

9 and 10 one-tenth minute surface symmetries.So it is lower than the output of the power amplifier element 300 of described first execution mode of foundation that output OUT will become.

[embodiment that described first execution mode is made amendment]

Figure 10 shows the circuit diagram as the configuration of the power amplifier element of first embodiment that described first execution mode is made amendment.In Figure 10, show differential to comprising the embodiment of n to parallel transistor.In the circuit diagram of Figure 10, only show the transistor of the inductor element 1 that is used for Fig. 2, but being used for the transistor of inductor element 2, hypothesis also provides like that as shown in this figure.

The power amplifier element of Figure 10 is included in n transistor Q1p_1 to Q1p_n of parallel coupled between the end 1p of inductor element 1 and the bonding part 8 and n transistor Q1n_1 to Q1n_n of parallel coupled between the end of inductor element 1 1n and bonding part 8.The first signal IN+ inputs to the gate electrode of Q1p_1 to Q1p_n, and secondary signal IN-inputs to the gate electrode of transistor Q1n_1 to Q1n_n.

In this case, be applied to the transistorized direct voltage Vds of a described n parallel coupled (drain electrode-source voltage) and be expressed as following equation:

Vds＝Vd×(Ron/2n)×(Ron/2n+Rs)…(2)

From equation (2) as seen, doubly (also promptly, be used to settle the described transistorized gross area to increase to n doubly) along with the parallel transistor number increases to n, described transistorized conducting resistance Ron is decreased to 1/n.So because resistance is cut apart, the dead resistance Rs the path from bonding part 8 to ground connection node GND causes bigger voltage to descend.Compare with the situation that is mounted with single transistor, this will reduce significantly and be applied to described transistorized direct voltage Vds.

As shown in Figure 2, if several wiring portion 4 to 7 provide the parallel coupled between bonding part 8 and the ground connection node GND, then can suppress to be applied to the reduction of described transistorized direct voltage.Other aspects among Figure 10 are identical with the circuit diagram of Fig. 7, therefore, and the designated identical reference number of identical or corresponding part, and no longer it is repeated in this description.

Figure 11 shows the plane graph as the grounding pattern 102a of second embodiment that described first execution mode is made amendment.In Figure 11, also show

primary inductor

1 and 2 and the layout of secondary inductor 3.

As shown in Figure 11, grounding pattern 102a can only dispose wiring portion 4, wiring portion 6 and bonding part 8 along the minute surface symmetrical plane 9 among Fig. 4.In this case, dead resistance and stray inductance in the path between bonding part 8 and the ground connection node GND become greater than dead resistance in Fig. 2 situation and stray inductance, but can make less than dead resistance and stray inductance in the comparative example's of Fig. 9 the situation.

Figure 12 shows the plane graph as the grounding pattern 102b of the 3rd embodiment that described first execution mode is made amendment.In Figure 12, also show the layout of

primary inductor

1,2 and secondary inductor 3.

As shown in Figure 12, grounding pattern 102b can only dispose wiring portion 5, wiring portion 7 and bonding part 8 along the minute surface symmetrical plane 10 among Fig. 4.In this case, dead resistance and stray inductance in the path between bonding part 8 and the ground connection node GND become greater than dead resistance in Fig. 2 situation and stray inductance, but can make less than dead resistance and stray inductance in comparative example's situation of Fig. 9.

＜the second execution mode 〉

Although described first execution mode shows the wherein embodiment of the power amplifier element of the synthetic two pairs of transistorized outputs of differential operation of transformer,, also can realize identical functions/effect even this transistorized logarithm changes to some extent.

Figure 13 shows the plane graph according to the configuration of the power amplifier element 301 of second embodiment of the invention.As shown in figure 13, comprise primary inductor (in Figure 14, representing), secondary inductor 20, grounding pattern (in Figure 15, representing) and three couples of transistor (Q1p at the power amplifier element 301 that provides on the substrate with reference number 202 with reference number 201, Q1n), (Q2p, Q2n), (Q3p, Q3n), described primary inductor is made of

inductor element

21,22 and 23.

Figure 14 shows the primary inductor plane graph of choosing from Figure 13 partly.With reference to Figure 14, primary inductor 201 is made of

inductor element

21,22 and 23, and the central shaft CP that inductor

element

21,22 and 23 winds perpendicular to described substrate is arranged to circular geometry substantially.The monnolithic case of primary inductor 201 around central shaft CP be three rotations (three-turn) symmetry and all be the minute surface symmetry about in

symmetrical plane

25,26 and 27 each, each in the

symmetrical plane

25,26 and 27 all comprises central shaft CP.

Figure 15 shows the grounding pattern plane graph of choosing from Figure 13 partly.With reference to Figure 15, grounding pattern 202 comprises wiring portion 25a, 25b, 26a, 26b, 27a, 27b and bonding part 24.When observing perpendicular to the direction of described substrate, wiring portion 25a, 25b place along the symmetrical plane among Figure 14 25, and are coupled near the bonding part 24 the central shaft CP in Figure 14.Wiring portion 25a, 25b be ground connection in the outside zone of ring-type primary inductor 201 (21,22,23) respectively.When observing perpendicular to the direction of described substrate, wiring portion 26a, 26b place along the symmetrical plane among Figure 14 26, and are coupled in bonding part 24.Wiring portion 26a, 26b be ground connection in the zone of ring-type primary inductor 201 outsides respectively.When observing perpendicular to the direction of described substrate, wiring portion 27a, 27b place along the symmetrical plane among Figure 14 27, and are coupled in bonding part 24.Wiring portion 27a, 27b be ground connection in the zone of ring-type primary inductor 201 outsides respectively.Provide among wiring portion 25a in Figure 15,25b, 26a, 26b, 27a, the 27b further and be similar to the opening shown in Fig. 3 B, but omitted this opening in the diagram herein.For primary inductor 201, grounding pattern 202 has rotational symmetry about identical rotation axes of symmetry CP, and has mirror symmetry about identical minute surface symmetrical plane 25,26 and 27.

Referring again to Figure 13, secondary inductor 20 is arranged so that annularly around primary inductor 201 (21,22 and 23).Secondary inductor 20 generates the synthetic output of the signal that has inputed to described inductor element to primary inductor 201 by magnetic coupling.Provide in the situation of differential output at power amplifier element 301, from two the end 20p and the 20n output differential wave of secondary inductor 20.Provide in the situation of single-phase output at power amplifier element 301, an end 20n ground connection, and export single-phase output signal OUT from the other end 20p.Although the secondary inductor shown in Figure 13 20 has a circle winding, secondary inductor 20 can have multicircuit winding.

The drain electrode of transistor Q1p, Q1n is coupled respectively to the end 21p and the 21n of inductor element 21, and the source electrode of transistor Q1p, Q1n is coupled to bonding part (representing with reference number 24) in Figure 15.The first signal IN+ and secondary signal IN-as differential input signal input to the gate electrode of transistor to Q1p and Q1n.The bias voltage Vd that is used for transistor Q1p and Q1n is applied near the centre cap 21c of mid point of inductor element 21.

The drain electrode of transistor Q2p, Q2n is coupled respectively to end 22p, the 22n of inductor element 22, and the source electrode of transistor Q2p, Q2n is coupled to bonding part (representing with reference number 24) in Figure 15.The first signal IN+ and secondary signal IN-as differential input signal input to the gate electrode of transistor to Q2p, Q2n.The bias voltage Vd that is used for transistor Q2p, Q2n is applied near the centre cap 22c of mid point of inductor element 22.

The drain electrode of transistor Q3p, Q3n is coupled respectively to end 23p, the 23n of inductor element 23, and the source electrode of transistor Q3p, Q3n is coupled to bonding part (representing with reference number 24) in Figure 15.The first signal IN+ and secondary signal IN-as differential input signal input to the gate electrode of transistor to Q3p, Q3n.The bias voltage Vd that is used for transistor Q3p, Q3n is applied near the centre cap 23c of mid point of inductor element 23.

Than the comparative example of Fig. 9, by using grounding pattern 202, dead resistance and stray inductance from described transistorized source electrode to the path of ground connection node GND are reduced to 1/6 roughly.

[embodiment that grounding pattern is made amendment]

Figure 16 shows the plane graph as the configuration of the grounding pattern 202a of the embodiment that the grounding pattern among Figure 15 202 is made amendment.In Figure 16, also show the layout of primary inductor 201 (21,22,23).

As shown in figure 16, grounding pattern 202a can only dispose

wiring portion

25a, 26a, 27a and the bonding part 24 among Figure 15.The monnolithic case of grounding pattern 202a about the central shaft CP among Figure 14 be three times rotational symmetric, and be the minute surface symmetry about in

symmetrical plane

25,26 and 27 each.In this case, than the situation of Figure 13, dead resistance and stray inductance in the path between bonding part 24 and the ground connection node GND become twice, but can be made into the situation less than the comparative example among Fig. 9.

Figure 17 shows the plane graph as the configuration of the grounding pattern 202b of another embodiment that the grounding pattern among Figure 15 202 is made amendment.In Figure 17, also show the layout of primary inductor 201 (21,22,23).

As shown in figure 17, grounding pattern 202b can only dispose

wiring portion

25b, 26b, 27b and the bonding part 24 among Figure 15.The monnolithic case of grounding pattern 202b about the central shaft CP among Figure 14 be three times rotational symmetric, and be the minute surface symmetry about in

symmetrical plane

[configuration of power amplifier element 302]

Figure 18 shows the plane graph according to the configuration of the power amplifier element 302 of first embodiment that second execution mode of the present invention is made amendment.Power amplifier element 302 shown in Figure 18 is provided on the described substrate, and comprise primary inductor (in Figure 19, representing), secondary inductor 30, grounding pattern (in Figure 20, representing) and four couples of transistor (Q1p of constituting by

inductor element

31,32,33 and 34 with reference number 212 with reference number 211, Q1n), (Q2p, Q2n), (Q3p, Q3n) and (Q4p, Q4n).

Figure 19 shows the primary inductor plane graph of choosing from Figure 18 partly.With reference to Figure 19, primary inductor 211 is substantially by being set to wind central shaft CP perpendicular to substrate that the

inductor element

31,32,33 and 34 of circular geometry constitutes.The monnolithic case of primary inductor 211 is four rotations (four-turn) symmetries around central shaft CP, and is the minute surface symmetry about in

symmetrical plane

36,37,38 and 39 each,

symmetrical plane

36,37,38 and 39 each comprise central shaft CP.

Figure 20 shows the grounding pattern plane graph of choosing from Figure 18 partly.With reference to Figure 20, grounding pattern 212 comprises wiring portion 36a, 36b, 37a, 37b, 38a, 38b, 39a, 39b and bonding part 35.When observing perpendicular to the direction of described substrate, wiring portion 36a, 36b place along the symmetrical plane among Figure 19 36, and are coupled near the bonding part 35 the central shaft CP in Figure 19.Wiring portion 36a, 36b be ground connection in the outside zone of ring-type primary inductor 211 (31,32,33 and 34) respectively.When observing perpendicular to the direction of described substrate, wiring portion 37a, 37b place along the symmetrical plane among Figure 19 37, and are coupled in bonding part 35.Wiring portion 37a, 37b be ground connection in the zone of ring-type primary inductor 211 outsides respectively.When observing perpendicular to the direction of described substrate, wiring portion 38a, 38b place along the symmetrical plane among Figure 19 38, and are coupled in bonding part 35.Wiring portion 38a, 38b be ground connection in the zone of ring-type primary inductor 211 outsides respectively.When observing perpendicular to the direction of described substrate, wiring portion 39a, 39b place along the symmetrical plane among Figure 19 39, and are coupled in bonding part 35.Wiring portion 39a, 39b be ground connection in the zone of ring-type primary inductor 211 outsides respectively.Further provide among wiring portion 36a in Figure 20,36b, 37a, 37b, 38a, 38b, 39a and the 39b and be similar to the opening shown in Fig. 3 B, but omitted this opening in the diagram herein.For primary inductor 211, grounding pattern 212 has mirror symmetry about identical rotation axes of symmetry CP and minute surface symmetrical plane 36,37,38 and 39.

Refer again to Figure 18, secondary inductor 30 is set annularly makes around primary inductor 211 (31,32,33 and 34).Secondary inductor 30 generates the synthetic output of the signal that has inputed to described inductor element to primary inductor 211 by magnetic coupling.Provide in the situation of differential output at power amplifier element 302, differential wave is from two the end 30p and the 30n output of secondary inductor 30.Provide in the situation of single-phase output at power amplifier element 302, an end 30n ground connection, and single-phase output signal OUT exports from another end 30p.Though the secondary inductor 30 shown in Figure 18 has a circle winding, secondary inductor 30 can have multicircuit winding.

The drain electrode of transistor Q1p, Q1n is coupled respectively to end 31p, the 31n of inductor element 31, and the source electrode of transistor Q1p, Q1n is coupled to bonding part (representing with reference number 35) in Figure 20.The first signal IN+ and secondary signal IN-as differential input signal input to the gate electrode of transistor to Q1p, Q1n.The bias voltage Vd that is used for transistor Q1p, Q1n is applied near the centre cap 31c of mid point of inductor element 31.

The drain electrode of transistor Q2p, Q2n is coupled respectively to end 32p, the 32n of inductor element 32, and the source electrode of transistor Q2p, Q2n is coupled to bonding part (representing with reference number 35) in Figure 20.The first signal IN+ and secondary signal IN-as differential input signal input to the gate electrode of transistor to Q2p, Q2n.The bias voltage Vd that is used for transistor Q2p, Q2n is applied near the centre cap 32c of mid point of inductor element 32.

The drain electrode of transistor Q3p, Q3n is coupled respectively to end 33p, the 33n of inductor element 33, and the source electrode of transistor Q3p, Q3n is coupled to bonding part (representing with reference number 35) in Figure 20.The first signal IN+ and secondary signal IN-as differential input signal input to the gate electrode of transistor to Q3p, Q3n.The bias voltage Vd that is used for transistor Q3p, Q3n is applied near the centre cap 33c of mid point of inductor element 33.

The drain electrode of transistor Q4p, Q4n is coupled respectively to end 34p, the 34n of inductor element 34, and the source electrode of transistor Q4p, Q4n is coupled to bonding part (representing with reference number 35) in Figure 20.The first signal IN+ and secondary signal IN-as differential input signal input to the gate electrode of transistor to Q4p, Q4n.The bias voltage Vd that is used for transistor Q4p, Q4n is applied near the centre cap 34c of mid point of inductor element 34.

Than the comparative example of Fig. 9, by using grounding pattern 212, dead resistance and stray inductance the path from transistorized source electrode to ground connection node GND are reduced to 1/8 roughly.

[embodiment that grounding pattern is made amendment]

Figure 21 shows the plane graph as the configuration of the grounding pattern 212a of the embodiment that the grounding pattern among Figure 20 212 is made amendment.In Figure 21, also show the layout of primary inductor 211 (31,32,33 and 34).

As shown in figure 21, grounding pattern 212a can only dispose

wiring portion

36a, 36b, 38a, 38b and the bonding part 35 among Figure 19.The monnolithic case of grounding pattern 212a about the central shaft CP among Figure 19 be four times rotational symmetric, and be the minute surface symmetry about in

symmetrical plane

36,37,38 and 39 each.In this case, than the situation of Figure 18, dead resistance and stray inductance in the path between bonding part 35 and the ground connection node GND become twice, but can be made into the situation less than the comparative example among Fig. 9.

Figure 22 shows the plane graph as the configuration of the grounding pattern 212b of another embodiment that grounding pattern among Figure 20 212 is made amendment.In Figure 22, also show the layout of primary inductor 211 (31,32,33 and 34).

As shown in figure 22, grounding pattern 212b can only dispose

wiring portion

37a, 37b, 39a, 39b and the bonding part 35 among Figure 19.The monnolithic case of grounding pattern 212b about the central shaft CP among Figure 19 be four times rotational symmetric, and be the minute surface symmetry about in

symmetrical plane

[configuration of power amplifier element 303]

Figure 23 shows the plane graph according to the configuration of the power amplifier element 303 of second embodiment that second execution mode of the present invention is made amendment.Power amplifier element 303 shown in Figure 23 is provided on the described substrate, and comprise primary inductor 40, secondary inductor 41, grounding pattern 43 and pair of transistor (Q1p, Q1n).

The central shaft CP that winds perpendicular to described substrate provides primary inductor 40 with being the cardinal principle circular geometry.The monnolithic case of primary inductor 40 is minute surface symmetries about the symmetrical plane 42 that comprises central shaft CP.

When observing perpendicular to the direction of described substrate, grounding pattern 43 is the wirings of placing along symmetrical plane 42, and extends to from the zone of the outside of primary inductor 40 1 sides in the zone of outside of opposite side of primary inductor 40.Grounding pattern 43 is located equal ground connection two ends.Grounding pattern 43 can be considered to wherein along the structure that is coupled near two bonding parts of wiring portion central shaft CP of symmetrical plane 42.

Provide secondary inductor 41 to make annularly around primary inductor 40.Secondary inductor 41 has inputed to the signal of primary inductor 40 to primary inductor 40 outputs by magnetic coupling.Provide in the situation of differential output at power amplifier element 303, from two the end 41p and the 41n output differential wave of secondary inductor 41.Provide in the situation of single-phase output at power amplifier element 303, an end 41n ground connection, and export single-phase output signal OUT from another end 41p.Though primary inductor 40 shown in Figure 23 and secondary inductor 41 have a circle winding, they can have multicircuit winding.

The drain electrode of transistor Q1p, Q1n is coupled respectively to end 40p, the 40n of primary inductor 40, and the source electrode of transistor Q1p, Q1n is coupled to grounding pattern 43.The first signal IN+ and secondary signal IN-as differential input signal input to the gate electrode of transistor to Q1p, Q1n.The bias voltage Vd that is used for transistor Q1p, Q1n is applied near the centre cap 40c of mid point of primary inductor 40.

Than the comparative example of Fig. 9, by using grounding pattern 43, dead resistance and stray inductance the path from transistorized source electrode to ground connection node GND are reduced to 1/2 roughly.

＜the three execution mode 〉

[configuration of power amplifier element 304]

Figure 24 shows the plane graph according to the configuration of the power amplifier element 304 of third embodiment of the invention.

Figure 25 shows the grounding pattern of choosing from Figure 24 150.With reference to Figure 24 and Figure 25, grounding pattern 150 is regarded as the earth shield 150 of patterning, earth shield 150 is by adding to the grounding pattern shown in Fig. 3 B 102 with 45 ° or 90 ° of a plurality of open-circuit lines (open stub) (wiring portion) 50 formation of intersecting with described transformer (

primary inductor

1,2 and secondary inductor 3).The monnolithic case of a plurality of open-circuit lines (wiring portion) 50 around central shaft CP be four times rotational symmetric, and about the symmetrical plane 9,10th of the

primary inductor element

1,2 shown in Fig. 4, the minute surface symmetry.Preferably, when when observing perpendicular to the direction of described substrate, the overall dimensions of grounding pattern 150 is less times greater than the overall dimensions of described transformer.

When transistor Q1p, Q1n, Q2p, Q2n are arranged in described transformer (

primary inductor

1,2 and secondary inductor 3) when interior, because described transistor is arranged in the fact in the zone that the flux of described transformer enters, so the current-carrying part in the described transistor (aluminum lead and impurity range) magnetic coupling to the wiring portion of described transformer is paid close attention to.Magnetic coupling between described transformer and the described transistor causes the reverse current do not expected, this reverse current then to cause the reducing of output of described power amplifier element.Therefore, in the power amplifier element 304 of the 3rd execution mode, described transformer (

primary inductor

1,2 and secondary inductor 3) and transistor Q1p, Q1n, Q2p, Q2n is separated from the space by the earth shield 150 of patterning, and therefore the magnetic coupling between described transformer and the described transistor is stopped to a certain extent.

Use have as shown in figure 25 geometric grounding pattern 150 still can keep remarkable reduction from described transistorized source electrode to the path of ground connection node GND dead resistance and the effect of stray inductance.Yet than the situation of described first execution mode, the influence of the RF characteristic of 150 pairs of described transformers of earth shield of use patterning is also not little.Generally speaking, use this shielding to cause the reduction of substrate loss, also, the Q value increases and disposes the reduction of self-resonant frequency of the inductor of described transformer.

Identical among other aspects among Figure 24 and Figure 25 and Fig. 2 and Fig. 3 A to Fig. 3 C, therefore, the designated identical reference number of identical or counterpart, and no longer it is repeated in this description.

Figure 26 A and Figure 26 B are the figure that further explains grounding pattern 150 effects among Figure 25.Figure 26 A illustrates comparative example's the figure that wherein replaces grounding pattern 150 and the screened film 150 of single full slice system is provided.The grounding pattern 150 that Figure 26 B has described Figure 25 forms contrast with the screened film 151 with Figure 26 A.

Generally speaking, provide the earth shield of patterning to suppress the coupling between inductor (comprising transformer) and the loss substrate by oxidation film.Yet when the screened film 151 of full slice system was provided, induced electromotive force generated big vortex current EC in screened film 151, and produces big energy loss.This is because because screened film 151 has the fact of limited resistance, so can not realize being completely fixed the screened film to ground potential.

Therefore, shown in Figure 26 B, by make a plurality of slits 55 in described screened film, except that near the zone the central shaft CP, the path that vortex current is flowed through (around the circular path of central shaft CP) is cut off.Even,, can reduce the energy loss that causes because of vortex current than the situation of Figure 26 A although in the earth shield 150 of patterning, in fact also generated little vortex current.

The Magnetic Shielding Effectiveness that the screened film 151 of full slice system produces is higher, in the screened film 151 of full slice system, along with big vortex current has generated reverse big magnetic flux (to offset original magnetic flux).Yet, because energy loss can not be used screened film 151.Therefore, even Magnetic Shielding Effectiveness is weaker than the screened film 151 of full slice system, also use the earth shield 150 of patterning.

In addition,, can suppress by described transformer (

primary inductor

1,2 and secondary inductor 3) and transistor Q1p by the earth shield 150 that patterning is provided, Q1n, Q2p, what the parasitic capacitance between the Q2n produced crosstalks.Thisly crosstalk that to suppress effect be significant, especially when described transformer and described transistor are arranged to the part overlapping.

Referring again to Figure 24 and Figure 25, preferably open-circuit line (wiring portion) 50 is oriented when when observing and wiring portion (conductor) quadrature (words as possible) of described transformer (

primary inductor

1,2 and secondary inductor 3) perpendicular to the direction of described substrate.

If the width of open-circuit line (wiring portion) 50 is too wide, the effect of path reduces because the cut-out vortex current is flowed through, and energy loss just will increase so.On the other hand, if the width of open-circuit line (wiring portion) 50 is narrow, then the dead resistance of described open-circuit line increases.This has increased the wiring portion (conductor) of described transformer and the path between the ground connection node GND (also is, extend to open-circuit line (wiring portion) 50 from the wiring portion (conductor) of described transformer by capacitive coupling, and extend path until ground connection node GND by open-circuit line (wiring portion) 50) in the loss of RF signal.Therefore, this has weakened the effect of crosstalking that suppresses by the generation of the parasitic capacitance between described transformer and the described transistor.Therefore, should select the optimum width of open-circuit line (wiring portion) 50.

Preferably, the width of slit 55 (two open-circuit line between interval) usually should be narrower to improve the ratio that described shielding covers described transformer.

The number of described open-circuit line is determined by following factor: cover described transformer to the minimum interval between two open-circuit lines of the optimum width of the required area of sufficient degree, open-circuit line, design rule decision.

[first embodiment that described the 3rd execution mode is made amendment]

Figure 27 shows the plane graph as the configuration of the grounding pattern 150a of the embodiment that grounding pattern among Figure 25 is made amendment.The geometric figure of grounding pattern 150a among Figure 27 is identical with grounding pattern 150 among Figure 25, but it is different to be coupled to the mode of ground connection node GND.In the situation of Figure 27, the further ground connection in end of the

wiring portion

51,52,53,54 that in bonding part 8, is coupled.Thus, can further reduce transistor Q1p, Q1n, Q2p, dead resistance and stray inductance in the path between the source electrode of Q2n and the ground connection node GND.More earth point can be provided, and can be with the end ground connection of all wiring portion 50.

[second embodiment that described the 3rd execution mode is made amendment]

Figure 28 A, Figure 28 B and Figure 28 C show the plane graph as the configuration of the power amplifier element of second embodiment that third embodiment of the invention is made amendment.

Figure 28 A shows the configuration of the transformer 106 that is made of

primary inductor

1,2 and secondary inductor 3.The configuration of transformer 106 is identical with transformer 101 among Fig. 3 A, therefore, no longer it is repeated in this description.

Figure 28 B shows the geometric plane graph of grounding pattern 107.Grounding pattern 107 comprises the pectination local pattern of separating by slit each other 61 to 64 (being called pars pectinata).Pars pectinata 61 to 64 comprises the root 61a to 64a that is coupled respectively to ground connection node GND.A plurality of wiring portion are engaged to each root of pars pectinata 61 to 64.In other words, grounding pattern 107 has the geometric figure of being made by single plane pattern, and when when observing perpendicular to the direction of described substrate, described single plane pattern extends to the zone of transformer 106 outsides from the zone of transformer 106 inside.In described plane pattern, on the direction that intersects with

primary inductor

1,2, make a plurality of slit openings, make not form closed circular path around central shaft CP.

Pars pectinata 64 is coupled to an end 3n of secondary inductor 3 by contact hole e.The geometric figure of grounding pattern 107 has the rotational symmetry and the mirror symmetry of the primary inductor of being similar to 1,2 among Figure 28 B.

Figure 28 C schematically shows transistor Q1p, Q1n, Q2p, the figure of the layout of Q2n.

Shown in Figure 28 C, the drain electrode of transistor Q1p is coupled to an end 1p of inductor element 1 by contact hole f, and the drain electrode of transistor Q1n is coupled to another end 1n of inductor element 1 by contact hole g.The drain electrode of transistor Q2p is coupled to an end 2p of inductor element 2 by contact hole h, and the drain electrode of transistor Q2n is coupled to another end 2n of inductor element 2 by contact hole i.

Transistor Q1p, Q1n, Q2p, the source electrode of Q2n intercouple together and by integrated.Incorporate source electrode is coupled to the wiring portion 61b of pars pectinata 61 by contact hole aa, be coupled to the wiring portion 62b of pars pectinata 62 by contact hole bb, be coupled to the wiring portion 63b of pars pectinata 63 by contact hole cc, and be coupled to the wiring portion 64b of pars pectinata 64 by contact hole dd.Thus, between source electrode and ground connection node GND, provide and conduct.

＜the four execution mode 〉

Figure 29 shows the plane graph according to the configuration of the power amplifier element 306 of the 4th execution mode of the present invention.

Figure 30 shows the plane graph of grounding pattern 109 parts of choosing from Figure 29.In Figure 30, also show the layout of

primary inductor

1,2 and secondary inductor 3.

In described first execution mode, use the metal wiring layer that differs from one another to form transformer 101, grounding pattern 102 and transistor Q1p, Q1n, Q2p, the electrode of Q2n (metal lead wire).In the power amplifier element 306 of described the 4th execution mode, except the part that overlaps each other, use identical metal wiring layer to form described transformer (

primary inductor

1,2 and secondary inductor 3) and grounding pattern 109.Because the top metal wiring layer has lower sheet resistance with respect to other metal wiring layers, so can further reduce dead resistance in the path between transistorized source electrode and the ground connection node.

Referring to Figure 29, use at the first metal layer that provides on the described substrate and second metal level that on described the first metal layer, provides, form power amplifier element 306.Illustrate for clear, the wiring portion of using the first metal layer to form marks with hacures.

Primary inductor comprises

inductor element

1,2, uses second metal level to form

inductor element

1,2 at the top.Secondary inductor comprises

wiring portion

3a, 3b, 3c, 3d and the wiring portion 3e that uses the first metal layer to form, 3f, 3g.Provide wiring portion 3e in the position that overlaps with the wiring portion 7 that is contained in the grounding pattern 109, wiring portion 3e is coupled to wiring portion 3a, 3b by contact hole.Provide wiring portion 3f in the position that the centre cap 1c with inductor element 1 overlaps, wiring portion 3f is coupled to

wiring portion

3b, 3c by contact hole.Provide wiring portion 3g in the position that overlaps with the wiring portion 5 that is contained in the grounding pattern 109, wiring portion 3g is coupled to

wiring portion

3c, 3d by contact hole.

Referring to Figure 30, grounding pattern 109 comprises

wiring portion

4a, 5,6a, 7,4c and bonding part 8 of using described second metal level formation and the wiring portion 4b that uses described the first metal layer to form, 6b.Bonding part 8 is formed near the central shaft of primary inductor and engages

wiring portion

4a, 5,6a, 7.In the position that overlaps with inductor element 1 and wiring portion 3c, provide wiring portion 4b, and wiring portion 4b is coupled to

wiring portion

4a, 4c by contact hole.In the position that overlaps with inductor element 2 and wiring portion 3d, provide wiring portion 6b, and wiring portion 6b is coupled to end 3n and the wiring portion 6a of wiring portion 3d by contact hole.

As shown in figure 29, at transistor Q1p, Q1n, Q2p, Q2n is arranged in the situation in the zone of wiring of the wiring that wherein do not have described transformer and grounding pattern, and the wiring that is used for transistorized electrode can be formed at the identical wiring layer that wherein forms described transformer and described grounding pattern.Yet in this case, the earth shield of the patterning described in the 3rd execution mode can not be used as grounding pattern.

In in order to the accompanying drawing that first to fourth execution mode is described, shown transformer comprises primary inductor and secondary inductor, and described primary inductor integral body forms single turn, and described secondary inductor also is a single turn.Spendable transformer is not limited to shown transformer in first to fourth execution mode.Also promptly, secondary inductor or primary inductor and secondary inductor both can be multiturns.

It is illustrative, and not restrictive that execution mode disclosed herein all should be considered in every respect.Scope of the present invention shows by appended claim, but not shown by the description of front, and therefore is intended to contain the meaning of the equivalent that falls into claim and the institute in the scope changes.

Claims

1. A power amplifier device is formed on a substrate, the power amplifier device comprising:

a primary inductor comprising a plurality of inductor elements arranged in a generally annular geometry when viewed from a direction perpendicular to the substrate;

a ground pattern provided to extend from a ring-shaped portion of a region inside the primary inductor to a region outside the primary inductor when viewed from a direction perpendicular to the substrate, and in the primary inductor ground at multiple points in the area outside the inductor; and

a plurality of transistor pairs, each transistor pair being arranged in connection with each of the plurality of inductor elements,

wherein first main electrodes of a first transistor and a second transistor forming a transistor pair connected to said inductor element are respectively coupled to two ends of each of said plurality of inductor elements,

wherein the second main electrodes of the first transistor and the second transistor are coupled to the ground pattern in a region inside the primary inductor and are in electrical conduction with the corresponding plurality of points,

wherein pairs of a first signal and a second signal are provided as differential input signals to control electrodes of said first transistor and said second transistor respectively, and

Wherein the power amplifier device further includes a secondary inductor, the secondary inductor includes one-turn winding or multi-turn winding and is annularly arranged to surround the primary inductor, and the secondary inductor also passes the magnetic coupled to the primary inductor to synthesize and output a composite signal of the first signal and the second signal synthesized in each inductor element.

2. A power amplifier device is formed on a substrate, the power amplifier device comprising:

a primary inductor comprising a one-turn winding or multiple-turn windings arranged in a ring geometry when viewed from a direction perpendicular to said substrate;

a ground pattern provided to extend from a ring-shaped portion of an area inside the primary inductor to an area outside the primary inductor when viewed from a direction perpendicular to the substrate, and on the primary inductor ground at multiple points in the area outside the inductor; and

pair of transistors, which are disposed on the substrate,

wherein the first main electrodes of the first transistor and the second transistor forming the pair of transistors are respectively coupled to two ends of the primary inductor,

Wherein the power amplifier device further includes a secondary inductor, the secondary inductor includes one-turn winding or multi-turn winding and is annularly arranged to surround the primary inductor, and the secondary inductor is magnetically coupled to the primary inductor to output a composite signal of the first signal and the second signal synthesized in the primary inductor.

3. The power amplifier device of claim 1,

wherein the primary inductor is annularly formed about a central axis perpendicular to the substrate and has mirror symmetry about each of one or more planes of symmetry, each plane of symmetry including the central axis, and

Wherein, the ground pattern includes:

a plurality of first wiring portions each extending from the vicinity of an intersection point into an area outside the primary inductor and grounded in an area outside the primary inductor at which the center an axis intersects the surface of the substrate along any of the one or more planes of symmetry; and

A joining portion is provided near the intersection point and joins the plurality of first wiring portions.

4. The power amplifier device according to claim 3, wherein said ground pattern further comprises a plurality of second wiring portions each coupled to any one of said plurality of first wiring portions and said bonding portion and extend to an area outside the primary inductor in a direction intersecting the primary inductor.

5. The power amplifier device according to claim 4, wherein at least one of said plurality of second wiring portions is grounded in a region outside said primary inductor.

6. The power amplifier device of claim 1,

wherein the primary inductor is annularly formed about a central axis perpendicular to the substrate and has mirror symmetry about each of one or more planes of symmetry, each plane of symmetry including the central axis,

Wherein, the ground pattern has a geometric figure in which a plurality of slit openings are made in a single planar pattern which, when viewed from a direction perpendicular to the substrate, is separated from the an area inside the primary inductor extends into an area outside the primary inductor, and the slit opening is made in a direction intersecting the primary inductor so that no closed circle is formed around the central axis shaped pathways, and

Wherein, the second main electrodes of the transistors forming the one or more transistor pairs are coupled together.

7. The power amplifier device of claim 1,

wherein the first main electrode and the second main electrode are formed using a first metal layer formed over the substrate,

wherein the ground pattern is formed using a second metal layer formed farther from the substrate than the first metal layer, and

Wherein, the primary inductor and the secondary inductor are formed using a third metal layer formed farther from the substrate than the second metal layer.

8. The power amplifier device according to claim 1 , wherein when viewed from a direction perpendicular to the substrate, except for portions overlapping each other, the primary inductor, the secondary inductor, and the ground The patterns are formed using the same metal layer formed over the substrate.

9. The power amplifier device of claim 2,

Wherein, the ground pattern includes:

10. The power amplifier device according to claim 9 , wherein said ground pattern further comprises a plurality of second wiring portions each coupled to any one of said plurality of first wiring portions and said bonding portion and extend to a region outside the primary inductor in a direction intersecting the primary inductor.

11. The power amplifier device according to claim 10, wherein at least one of said plurality of second wiring portions is grounded in a region outside said primary inductor.

12. The power amplifier device of claim 2,

13. The power amplifier device of claim 2,

14. The power amplifier device according to claim 2, wherein when viewed from a direction perpendicular to the substrate, except for portions overlapping each other, the primary inductor, the secondary inductor, and the ground The patterns are formed using the same metal layer formed over the substrate.