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CN102214631A - 用于半导体装置的引线框 - Google Patents

用于半导体装置的引线框 Download PDF

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Publication number
CN102214631A
CN102214631A CN2010101475137A CN201010147513A CN102214631A CN 102214631 A CN102214631 A CN 102214631A CN 2010101475137 A CN2010101475137 A CN 2010101475137A CN 201010147513 A CN201010147513 A CN 201010147513A CN 102214631 A CN102214631 A CN 102214631A
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China
Prior art keywords
lead
wire
tube core
lead frame
semiconductor
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CN2010101475137A
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陆永胜
田斌
许南
姚晋钟
赵树峰
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NXP USA Inc
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Freescale Semiconductor Inc
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Priority to CN2010101475137A priority Critical patent/CN102214631A/zh
Priority to US13/021,716 priority patent/US8115288B2/en
Publication of CN102214631A publication Critical patent/CN102214631A/zh
Pending legal-status Critical Current

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Abstract

一种用于减小毛边形成的不利影响的引线框，包括：引线框，其具有引线，其中从第一引线将顶部表面的一部分去除，并从与第一引线相邻的第二引线将底部表面的一部分去除，以减少引线之间的间隔，同时减小在利用所述引线框制造的半导体器件的单颗化期间导致的毛边形成的不利影响，诸如短路等等。

Description

用于半导体装置的引线框
技术领域
本发明总的涉及半导体封装，并且更具体的，涉及用于封装半导体装置的引线框，其减少了在单颗化(singulation)工艺期间毛边形成(burr formation)的不利影响。
背景技术
典型地，利用矩阵阵列封装(MAP)来组装常规的半导体封装装置10，诸如，如图1A-1B中所示的单排引线框设计四方扁平无引线(quad flat no-lead，QFN)封装。MAP型的半导体封装装置可以被处理并制造为单个基板条单元(single substrate bar unit)上的多个半导体封装装置。在组装期间，通过单颗化工艺将所述单个基板条单元划分成单独且分立的半导体封装装置。
每个半导体封装装置10典型地包括具有引线12以及管芯接合区域(die bond area)14的引线框。利用粘结剂(诸如环氧材料)，将半导体集成电路(IC)管芯(die)(在图1A-1B中未示出)固定或接合到引线框的管芯接合区域14。引线框是该半导体封装装置的中央支撑结构。在IC管芯已经被附着到管芯接合区域14之后，通过导线接合(wire bonding)工艺利用导线将IC管芯电连接到引线12，以使得能够实现在IC管芯和下面的基板(诸如印刷电路板(PCB))之间的电互连。然后，陶瓷或塑料材料的模塑化合物(mold compound)16包封或部分包封管芯、导线以及部分的引线框，以保护它们免受环境影响。然后，对被包封的MAP的组件进行单颗化，以分离并完成制造分立的半导体封装装置10的工艺。
传统上，存在两种单颗化工艺：锯切单颗化和冲压单颗化。在MAP装置的单颗化工艺期间，半导体封装装置可能变得受损，如图1B中用装置20所示的。例如，在锯切单颗化中，由在锯切路径方向26上涂污(smear)引线12的锯子24所导致的毛边22的形成能够使一个引线延伸到相邻的引线。由于被涂污的材料可能导致相邻引线之间的短路，毛边22可能引起装置故障。随着输入/输出(I/O)的数量或密度正在增加以及相邻引线之间的节距或距离28正在变得更小，毛边形成在业内正在变为更重要的考量。也即，存在不断增加毛边形成和短路的风险。
因此，需要解决或者至少减轻与传统的半导体封装装置相关联的上述问题，以减小单颗化期间毛边形成的不利影响。
发明内容
本发明的一个方面是在半导体封装装置内支撑半导体管芯的引线框，该引线框包括：用于容纳半导体管芯的管芯接合区；以及布置在管芯接合区周围并与管芯接合区间隔开的多个引线，其用于与半导体管芯电互连，并用于提供用于半导体封装装置的电互连，所述引线具有顶部表面和底部表面，其中所述多个引线中的第一引线具有从所述顶部表面凹陷的部分，并且与第一引线相邻的第二引线具有从所述底部表面凹陷的部分，以用于减小毛边形成的影响。
在一个实施例中，所述多个引线以单排的形式布置在管芯接合区的周界周围。所述多个引线可以包括具有从所述顶部表面凹陷的部分的多个第一引线，其形成第一排；以及具有从所述底部表面凹陷的部分的多个第二引线，其形成第二排。第一引线和第二引线相邻但以第一距离分开，并且第一引线和与第二引线相邻的第三引线以第二距离分开，其中所述第二距离从第一引线延伸超出潜在的毛边形成区。所述第一距离可以被减小。
在一个实施例中，第一引线和第二引线的凹陷部分的深度可以不同或相同。第一引线的凹陷部分的深度可以是引线框的厚度的一半或更多。
本发明的一个方面是半导体封装装置，其包括半导体管芯、用于支撑半导体管芯的引线框、以及至少部分包封半导体管芯的半导体封装体，所述引线框包括：
用于容纳半导体管芯的管芯接合区；以及布置在管芯接合区周围并与管芯接合区间隔开的多个引线，其用于与半导体管芯电互连，并用于提供用于半导体封装装置的电互连，所述引线具有顶部表面和底部表面，其中所述多个引线中的第一引线具有从所述顶部表面凹陷的部分，并且与第一引线邻近的第二引线具有从所述底部表面凹陷的部分以用于减少毛边形成的影响，其中所述第一和第二引线的凹陷部分的表面被暴露在所述半导体封装体的表面上；并且
所述半导体管芯具有第一表面和第二表面，该第一表面附着在所述引线框的管芯接合区上，并且该第二表面与所述多个引线中的至少一个引线电互连。
在一个实施例中，所述引线框的所述多个引线以单排的形式布置在管芯接合区的周界周围。所述引线框的所述多个引线可以包括具有从所述顶部表面凹陷的部分的多个第一引线，其形成暴露在所述半导体封装体的表面上的第一排；以及具有从所述底部表面凹陷的部分的多个第二引线，其形成暴露在所述半导体封装体的表面上的第二排。所述引线框的第一引线和相邻引线可以以第一距离分开，并且第一引线和与第二引线相邻的第三引线以第二距离分开，其中所述第二距离从第一引线延伸超出潜在的毛边形成区。
本发明的一个方面是形成用于半导体封装的引线框的方法，该方法包括提供引线框，该引线框具有用于容纳半导体管芯的管芯接合区以及布置在管芯接合区周围并与管芯接合区间隔开的多个引线，所述引线用于与半导体管芯电互连，并用于提供用于半导体封装装置的电互连，所述引线具有顶部表面和底部表面；在所述多个引线中，从所述顶部表面移除一部分以形成第一引线的凹陷部分；以及从所述底部表面移除一部分以形成与第一引线邻近的第二引线的凹陷部分，以减少毛边形成的影响。
附图说明
为了可以通过非限制性的示例的方式来全面并且更清晰地理解本发明的各实施例，结合附图给出了下面的描述，在附图中相同的附图标记指示相似或相应的元件、区域或部分，并且在附图中：
图1A-B示出了传统的单排引线框四方扁平无引线(QFN)半导体封装装置在锯切单颗化期间的底部透视图(图1A)和截面侧视图(图1B)；
图2A-B示出了根据本发明实施例的单排引线框四方扁平无引线(QFN)半导体封装装置在锯切单颗化期间的底部透视图(图2A)和截面侧视图(图2B)；
图3A-C示出了根据本发明实施例的在刻蚀引线框的选定部分之后该引线框的底部平面图(图3A)、顶部平面图(图3B)、以及底部透视图(图3C)；
图4A-H示出了根据本发明实施例的在组装期间引线框和半导体封装装置的截面图；以及
图5是根据本发明实施例的组装半导体装置的方法的流程图。
具体实施方式
图2A示出了根据本发明实施例的半导体封装装置50的底部透视图。所示的半导体封装装置是具有矩阵阵列封装(MAP)的单排引线框四方扁平无引线(QFN)设计。将理解，本发明的实施例可以应用于具有MAP的任何基于引线框的半导体封装装置。装置50包括引线框，该引线框具有被模塑材料56包封或部分包封的引线52和54以及管芯接合区58。装置50包括集成电路(IC)管芯，其被附着于引线框的管芯接合区的顶部表面。该IC管芯与电互连器(interconnector)(诸如导线等)导线接合。模塑材料56还包封该IC管芯和互连器(在图2A中未示出)。模塑材料56形成半导体封装装置的主体。在描述制造封装装置的工艺时，在图4A-H和图5中示出了IC管芯和互连器。
图2B示出了在MAP装置的单颗化工艺期间装置50的截面侧视图70。该单颗化工艺是将包封的管芯组件从分享公共引线框架的物理上相连的包封的管芯组件的阵列分离的工艺。图2B示出了在锯切单颗化期间生成的毛边形成72。该毛边形成是由锯子24和引线材料之间的摩擦引起的。毛边形成72在锯子从引线表面52进入包封模制材料56中的路径的方向26上延伸。毛边形成区仅在锯子的该路径的方向上延伸。典型地，锯子是圆锯并且锯子旋转。毛边形成区主要沿着锯子的平移路径方向延伸。可以在锯子的圆周或旋转方向上稍微拉该材料。因此，在常规设计中，在毛边形成区内的相邻的暴露的引线表面处于风险中。然而，在本发明的实施例中，相邻的暴露的引线表面被布置使得该相邻的暴露的引线表面在毛边形成区外部。
引线框和引线的材料可以是涂敷、合金或预镀有诸如金(Au)、镍(Ni)、钯(Pd)、或锡(Sn)等的铜(Cu)的基础材料层。在蚀刻或处理了引线框的基板之后，接着使蚀刻后的基板镀覆或涂敷有涂层。如果金属的延展性是大的，那么这些金属层常常可能对涂污或毛边形成起贡献。例如，在与纯粹地基于Cu的引线框相比较时，在预镀有Sn的基于Cu的引线框中毛边形成是较大的，这是因为Sn的延展性大于Cu。用于QFN、功率QFN等等中的引线框具有这样的镀层或涂层。在毛边形成中，毛边主要是该镀覆材料。
引线的节距78是相邻引线之间的距离。所暴露的引线表面52、54由单排引线框组成。这些引线被部分包封使得通过增加引线之间的距离使相邻的引线每一个都具有减少毛边形成的不利影响的暴露表面。因此，在本发明的实施例中，当在单颗化期间形成毛边形成时，相邻的引线的相邻的暴露表面之间的距离大于毛边形成从暴露的引线延伸的距离，从而降低了毛边形成的不利影响。
在图2B中，在一个实施例中的暴露的引线表面52、54的图案被示出为每一相邻的引线表面相对于相邻的引线表面交错。在该实施例中，封装体的表面上的该交错的暴露的引线表面52、54形成两排。将理解，暴露的引线表面52、54可以形成不同的配置和图案。例如，可以在顶部和底部表面上将特别选择的引线部分地蚀刻到相同或不同的深度。这将允许所得到的引线的暴露的表面形成不同的排数、配置等等，只要沿半导体封装装置的表面侧的引线的暴露的表面在毛边形成区的外部即可。在图2B所示的实施例中，在相同排中的封装体的表面上的引线的暴露部分或表面具有大于毛边形成区的节距78。在比较图1B中所示的传统装置中相邻引线的节距28与图2B中所示的本发明的实施例中的在相同暴露排中的相邻引线的节距78时，图2B中所示的实施例中的节距78是较大的。例如，相同的暴露排中引线的暴露表面之间的节距78可以是1.8mm。布置并处理引线框的引线以减小暴露的引线表面52、54，其作用来减小毛边形成的不利影响。由于交错的暴露的排中的相邻引线不是在毛边形成区内，因此可以减小不同的暴露的排中的相邻引线之间的间隔或节距79。例如，传统装置的节距28可以是0.9mm，不同排中的暴露的引线之间的节距79可以小于0.9mm。封装体的表面上暴露的相邻引线之间的节距79是引线框的实际单排引线之间的间隔。在比较图1B中所示的传统装置中的相邻引线的节距28与图2B中所示的本发明实施例中的不同排中相邻引线的节距79时，图2B中所示的实施例中的节距79是较小的。布置并处理引线框的引线以减少或减小不同排中相邻引线的节距79，以允许高度地封装的或更密集地封装的引线表面配置。因而，可以减小布置在管芯衬垫(die pad)区域周围的单排引线中的每一引线之间的间隔或节距79。通过该配置，单排引线被密集地封装，并且减小了毛边形成的不利影响，这是因为相邻引线具有凹陷部分，该凹陷部分被布置为使得在包封时半导体封装体的表面上的引线的凹陷部分的暴露的表面在毛边形成区之外。由于可以减小引线之间间隔或节距79，因此可以增加引线数目。可能存在这样的具有MAP配置的包封的管芯组件的阵列，其经受单颗化工艺以分离并完成制造半导体封装装置10的工艺。
图3A示出了在将未被蚀刻的所选定的引线102的选定的底部表面和引线104的底部表面部分蚀刻之后引线框的底部平面图100。引线102、104是单排引线中的相邻引线，每一个都分别有一部分被从顶部和/或底部表面去除以形成引线的凹陷部分并且形成两排或更多排等，或者是在包封和单颗化时沿半导体封装装置的表面暴露的引线。示出了管芯接合区域58的底部表面108。图3B示出了在部分蚀刻选定的引线104的选定的顶部表面之后引线框的顶部平面图120。示出了管芯接合区域58的顶部表面118。选定的引线102的底部表面被部分地蚀刻到预定深度。引线102的底部表面具有蚀刻的底部部分表面122。选定的引线104的顶部表面被部分地蚀刻到预定深度。引线104的顶部表面具有蚀刻的顶部部分表面124。
选定的引线102、104被蚀刻的深度可以是减小毛边形成的不利影响并且继续用作封装装置上的引线的任何深度。在去除该材料之后，使布置在管芯接合区域周围的单排引线中的每一引线的部分凹陷，形成凹陷部分。在对半导体封装体的表面单颗化之后，每一引线的凹陷部分的表面被暴露。在凹陷部分的形成中，引线未被完整地或者完全地蚀刻穿过。引线仅被部分地蚀刻或者半蚀刻。引线102上从底部表面蚀刻的深度可以与引线104上从顶部表面蚀刻的深度不同或者相同。在图3C所示的实施例中，引线102、104被半蚀刻。在两组引线102、104被半蚀刻的该实施例中，蚀刻可以同时处理，然而部分蚀刻可以在不同处理时间完成，如图5所示。对深度进行选择以防止或者减小毛边形成对封装体上相邻的暴露引线的不利影响。所述深度可以是任何深度，只要在封装组装期间维持引线框稳定性即可。
在图3C中，在引线框的底部透视图150中，示出了部分蚀刻之后所得到的引线。示出了底部表面上部分蚀刻的引线102的蚀刻后的侧表面部分152和未蚀刻的或未受干扰的部分侧表面部分52，以及顶部表面上部分蚀刻的引线104的蚀刻后的侧表面部分154和未蚀刻的或未受干扰的侧表面部分54。将理解，在实施例中，选定的引线可以使其部分的顶部和底部表面被去除或被部分蚀刻，以形成引线的顶部表面上的凹陷部分以及引线的底部表面上的凹陷部分。
图4A-H示出根据本发明实施例的处理引线框以及半导体封装装置的截面图。图4A示出了具有底部表面162以及顶部表面164的引线框基板160。引线框基板160经受蚀刻以形成图4B中所示的引线166以及管芯接合区域58。管芯接合区域具有管芯接合区域底部表面108以及管芯接合区域顶部表面128。可以通过不同技术(诸如蚀刻等等)处理引线框基板，以形成所述引线166。例如，可以将掩模(未示出)应用于引线框基板160的底部表面162以及顶部表面164，描绘引线框布局的轮廓，以蚀刻未覆盖区域。
图4C-D更加详细地示出了上述讨论的并在图3A-C中示出的引线配置。图4C示出了从底部表面部分蚀刻的引线102，而图4D示出了从顶部表面部分蚀刻的引线104。图4C是图3A的部分蚀刻的引线框沿线A-A截取的截面图。图4D是图3B的部分蚀刻的引线框沿线B-B截取的截面图。
在图4C中，被部分去除或蚀刻掉的切除(cut-out)部分或凹陷部分是通过底部表面被部分蚀刻的引线102的底部蚀刻的部分表面122和侧面蚀刻的部分表面152定义的。示出了底部表面被部分蚀刻的引线102的底部表面的未受干扰的顶部表面172。
在图4D中，被部分去除或蚀刻掉的切除部分或凹陷部分是通过顶部表面被部分蚀刻的引线104的顶部蚀刻的部分表面124和侧面蚀刻的部分表面154定义的。示出了顶部表面被部分蚀刻的引线104的底部表面的未受干扰的顶部部分表面174。图4C还示出了底部表面被部分蚀刻的引线102的未受干扰的底部部分表面162。图4D还示出了顶部表面被部分蚀刻的引线104的底部表面的未受干扰的底部表面184。
将理解，可以使用不同技术来去除引线框的材料以形成期望的引线配置。例如，可以使用基于光刻的蚀刻工艺或者用于蚀刻、研磨或者以其它方式形成切除的引线配置的其他技术、化学物质和/或工艺，并且可以根据本发明实施例广泛地改变。将理解，可以同时地或者以逐步的方式进行刻蚀工艺。
图4E示出了附着于管芯衬垫区域58的顶部表面118的IC管芯186。可以利用粘合材料(诸如，环氧材料、焊料材料、或者非焊料材料等)来使管芯附着。附着于引线框的管芯接合区域的半导体管芯可以是任何适当的半导体装置，诸如水平的半导体装置、或垂直的半导体装置等。管芯可以使管芯的全部或部分的底部表面附着于管芯接合区域。将半导体管芯附着于引线框的工艺可以根据本发明的实施例而广泛地变化。在将管芯186附着到凹陷的管芯接合区域之后，将引线框管芯组件与互连188导线接合，如图4F所示。互连188可以是导线，诸如金线等等。导线接合的工艺可以根据本发明的实施例而广泛地变化。
如图4G-H所示，利用包封材料56(诸如环氧的或其他的塑料材料、陶瓷材料等)包封引线框管芯组件。通过底部表面被蚀刻的引线102的底部蚀刻的部分表面122和侧面蚀刻的部分表面152定义的切除区域或凹陷部分填充有模塑化合物196。具有部分蚀刻的底部表面的引线102的底部表面的未受干扰的或未蚀刻的部分182被暴露并且未被模塑材料56包封，如图4G如所示。此外，引线102的侧表面52也被暴露，并且未被模塑材料56包封。类似地，具有部分蚀刻的顶部表面的引线104的未受干扰的或未蚀刻的底部表面184暴露并且未被模塑材料56包封，如图4H所示。引线104的暴露的侧表面54和底部表面184形成引线材料的连续表面，其被暴露并且形成半导体封装装置的角。
在根据本发明的实施例的图5的流程图200中示出了如上所详细描述的工艺或方法。在步骤202，引线框基板设置有引线和所定义的管芯接合区域。在步骤204，在顶部表面上部分蚀刻选定的引线以形成凹陷部分，并且在步骤206，在底部表面上部分蚀刻选定的引线以形成凹陷部分。将理解，引线的蚀刻可以在单个蚀刻处理步骤中同时地或者在分开的蚀刻处理步骤中进行。在部分蚀刻了引线之后，在步骤208，如图4E中所示将管芯180附着到管芯接合区域58的顶部表面128。然后，在步骤210，将管芯与互连(导线)185导线接合，并且在在步骤212利用模塑化合物材料56将管芯包封。在步骤214，通过锯切或冲压单颗化来将包封的装置单颗化。
本发明的实施例减少了在单颗化时发生毛边形成的不利影响。引线框被设计有这样的引线，所述引线被处理和布置为使受毛边形成影响的暴露在封装体上的引线的一些部分或区段被布置在潜在的毛边形成区的外部。由于通过蚀刻选定引线的选定部分或区段增加了相邻引线之间的距离，因而减少了毛边形成的短路风险及其他不利影响。另外，在实施例中，可以减小顶部表面被蚀刻的引线和底部表面被蚀刻的引线之间的实际间隔或节距，从而减少了引线所需的总的空间并允许引线被更紧密地封装。本发明的实施例可以应用于各种类型的基于引线框的半导体封装装置，诸如MAP类型装置、高输入/输出(IO)(x)QFN装置、功率QFN装置等等。
尽管已经描述并示出了本发明的实施例，但是相关技术领域的技术人员将理解，可以进行设计或架构的细节上的许多变化或修改而不偏离本发明的范围。

Claims (10)

1.一种在半导体封装装置内支撑半导体管芯的引线框，所述引线框包括：
管芯接合区域，用于容纳半导体管芯；以及
多个引线，其布置在管芯接合区域周围并与管芯接合区域间隔开，用于与半导体管芯电互连，并用于提供用于半导体封装装置的电互连，所述引线具有顶部表面和底部表面，其中所述多个引线中第一引线具有从顶部表面凹陷的部分，并且与第一引线相邻的第二引线具有从底部表面凹陷的部分，用于减小毛边形成影响。
2.如权利要求1所述的引线框，其中所述多个引线以单排布置在所述管芯接合区域的周界周围。
3.如权利要求1所述的引线框，其中所述多个引线包括：多个具有从顶部表面凹陷的部分的第一引线，其形成第一排；以及多个具有从底部表面凹陷的部分的第二引线，其形状第二排。
4.如权利要求1所述的引线框，其中第一引线以及第二引线是相邻的并以第一距离分开，并且第一引线和与第二引线相邻的第三引线以第二距离分开，其中第二距离从第一引线延伸超出潜在的毛边形成区。
5.一种半导体封装装置，包括：
半导体管芯；
引线框，用于支撑所述半导体管芯；以及
半导体封装体，其至少部分包封所述半导体管芯；
所述引线框包括：
管芯接合区域，用于容纳所述半导体管芯；
多个引线，其布置在管芯接合区域周围并与管芯接合区域间隔开，用于与半导体管芯电互连，并用于提供用于半导体封装装置的电互连，所述引线具有顶部表面和底部表面，其中所述多个引线中的第一引线具有从顶部表面凹陷的部分，并且与第一引线邻近的第二引线具有从底部表面凹陷的部分，用于减小毛边形成影响，其中所述第一和第二引线的凹陷的部分的表面被暴露在所述半导体封装体的表面上；以及
其中所述半导体管芯具有第一和第二表面，第一表面附着在所述引线框的管芯接合区域上，而第二表面与所述多个引线中的至少一个引线电互连。
6.如权利要求5所述的半导体封装装置，其中所述引线框的所述多个引线以单排布置在所述管芯接合区域的周界周围。
7.如权利要求5所述的半导体封装装置，其中所述引线框的所述多个引线包括：具有从顶部表面凹陷的部分的多个第一引线，其形成暴露在所述半导体封装体的表面上的第一排；以及具有从底部表面凹陷的部分的多个第二引线，其形成暴露在所述半导体封装体的表面上的第二排。
8.如权利要求5所述的半导体封装装置，其中所述引线框的第一引线和相邻的引线以第一距离分开，并且第一引线和与第二引线相邻的第三引线以第二距离分开，其中第二距离从第一引线延伸超出潜在的毛边形成区。
9.一种形成用于半导体封装装置的引线框的方法，包括：
提供引线框，该引线框具有：管芯接合区域，用于容纳半导体管芯；以及多个引线，其被布置在所述管芯接合区域周围并与所述管芯接合区域间隔开，用于与所述半导体管芯电互连以及用于提供用于所述半导体封装装置的电互连，所述引线具有顶部表面和底部表面；
从所述多个引线中的第一引线的顶部表面去除一部分，以形成凹陷的部分；以及
从与第一引线相邻的第二引线的底部表面去除一部分，以形成凹陷部分，用于减少毛边形成影响。
10.如权利要求9的方法，进一步包括：
将半导体管芯附着于所述引线框的所述管芯接合区域；以及
将所述半导体管芯与所述引线框的引线电连接，以及包封所述管芯和所述引线框，从而形成半导体封装装置。
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