CN102226943B - System and method for realizing screen splicing - Google Patents
System and method for realizing screen splicing Download PDFInfo
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Abstract
The invention provides a system and a method for realizing screen splicing. A splicing control unit receives a splicing instruction, port configuration information and sub-screen splicing mode from a client and output the port configuration information and the sub-screen mode to an exchanger through a parallel transmission bus. A multicast group address and a multicast group mapping relation are generated based on the display address of a processor and are output to an exchanger through the parallel transmission bus. The main processor interacts with a video source and an image after coding is obtained. The main processor decodes the encoded image and outputs the decoded image to a plurality of sub-processors through the exchange. The sub-processors intercept the decoded image stored in the display address based on the received sub-screen splicing mode and outputs the intercepted image to sub-screens connected to the sub-processors. According to the system and method provided in the invention, a complex time synchronization control algorithm is unnecessary, the consumption of the system resource is reduced, and the synchronization precision of each part of the image to be spliced is improved.
Description
Technical field
The present invention relates to video display technology, particularly a kind of system and method for realizing screen splicing.
Background technology
In the video display system, in order to show better the details effect of video image, play after usually video image being amplified.Because size and the resolution of separate unit display are limited, can not satisfy actual demand, and the screen splicing technology can be spliced into the polylith display one monoblock giant-screen, the size of the screen that is spliced and resolution have had and have increased exponentially.
Application number is that 201010128568.3 patent of invention discloses a kind of large screen splicing method and system, and Fig. 1 is the structural representation of large screen splicing system in this patent of invention.Now in conjunction with Fig. 1, the structure of existing large screen splicing system is described, specific as follows:
Existing large screen splicing system comprises: video source, network-bus, multiple pc terminal and NTP (Network Time Protocol) server.Wherein, video source connects multiple pc and ntp server by network-bus, utilizes the mode such as UDP multicast transmission to guarantee the data synchronized transmission; It is synchronous that ntp server is used for that the multiple pc that is connected to network-bus is carried out system time, so that the time synchronized between each PC terminal and the video source; Each PC terminal is connected with the son screen that forms large-size screen monitors respectively, and the clock synchronization module that comprises in each station terminal is used for the clock synchronous of each PC terminal, guarantees continuity and the synchronism of the large screen image that each son screen is spliced into.Since video source in the process of carrying out Video coding, video source send image to the process of each PC terminal, and each PC terminal in the process of decoding, all can produce time delay, and the time delay that produces of each two field picture coding, send time delay that image produces, and the time delay that produces of each PC decoding terminals all incomplete same.In order to solve the synchronous problem of video image after each son screen is spliced into large-size screen monitors, the maximal value of the time delay that each two field picture of needs acquisition consumes from the process that is encoded to decoding, this just need to arrange complicated time synchronized control algolithm in video source and multiple pc terminal.
According to foregoing as can be known, adopt shown in Figure 1 existing large screen splicing system, because the image after video source will be encoded sends to each PC terminal by network-bus, and each PC terminal is carried out the decoding of image independently, and it is asynchronous to cause easily the son that is connected with each PC terminal to shield the large screen image that is spliced into.In order to solve the problem of large screen splicing rear video image synchronization, need to arrange complicated time synchronized control algolithm on each PC terminal and the video source; And complicated time synchronized control algolithm has consumed higher system resource, and the precision of the each several part image synchronization of splicing is still waiting further raising.
Summary of the invention
In view of this, the object of the present invention is to provide a kind of system that realizes screen splicing, this system need not complicated time synchronized control algolithm, has reduced the consumption to system resource, has improved the precision of the each several part image synchronization of splicing.
The object of the present invention is to provide a kind of method that realizes screen splicing, the method need not complicated time synchronized control algolithm, has reduced the consumption to system resource, has improved the precision of the each several part image synchronization of splicing.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
A kind of system that realizes screen splicing receives the data from video source, and this system comprises:
The splicing control module receives splicing instruction, port configuration information and son screen Splicing model from client by network, and by parallel transmission output end of main mouth configuration information and son screen Splicing model to interchanger; According to coming since the demonstration address of processor, generate multicast group address and multicast group mapping relations, and export interchanger to by the parallel transmission bus; Described son screen Splicing model comprises information, and each height screen and from the corresponding relation of processor of a plurality of son screens that splice; Described port configuration information comprises port information, and the port information of a plurality of interchangers that connect from processor of the interchanger that primary processor connects; Described multicast group mapping relations are the multicast group address and the corresponding relation of the port information of a plurality of interchangers that are connected from processor;
Interchanger, according to port configuration information, output screen Splicing model is to a plurality of from processor; According to port configuration information, output multicast group address is to primary processor; According to port configuration information, multicast group address and multicast group mapping relations, the decoded image that will read from the multicast group address exports to a plurality of from processor;
Primary processor, according to network output get the stream instruction, undertaken alternately by network and video source, also decode by the image behind the Network Capture coding, upload decoded image to the multicast group address of interchanger;
A plurality of from processor, wherein arbitrary son that receives from the processor basis shields Splicing model, by the interchanger that is connected with the parallel transmission bus, upload it and show that the address is to splicing control module, the decoded image of interchanger output is stored in the demonstration address, and according to son screen Splicing model, intercept showing the decoded image in the address, the image after the output intercepting is to connected son screen.
In the said system, described interchanger comprises:
First order crosspoint will export a plurality of second level crosspoint to from son screen Splicing model, port configuration information, multicast group address and the multicast group mapping relations that the parallel transmission bus is obtained, and the demonstration address with obtaining exports the parallel transmission bus to; The decoded image that obtains is write in the multicast group address, and the decoded image that will read from the multicast group address exports a plurality of second level crosspoint to;
A plurality of second level crosspoint, the arbitrary second level crosspoint that comprises connect respectively first order crosspoint and at least one processor; Be connected with the second level crosspoint of described primary processor according to port configuration information, output multicast group address is to primary processor, and decoded image and multicast group address that primary processor is sent export first order crosspoint to; Be connected with second level crosspoint from processor according to port configuration information, output screen Splicing model will export first order crosspoint to from the demonstration address of processor to from processor; According to multicast group address, multicast group mapping relations and port configuration information, export decoded image extremely from processor.
In the said system, described first order crosspoint is the outside interconnected PCIe interchanger of high speed; Described second level crosspoint is the PCIe interchanger.
A kind of method that realizes screen splicing, the method comprises:
A, splicing control module are exported son screen Splicing model to a plurality of from processor according to splicing instruction, son screen Splicing model and port configuration information from Network Capture by the interchanger that is connected with the parallel transmission bus;
B, a plurality of son screen Splicing model that receives from the processor basis by the interchanger that is connected with the parallel transmission bus, are uploaded it and are shown that address is to splicing control module;
C, splicing control module generate multicast group address and multicast group mapping relations according to coming since the demonstration address of processor, by parallel transmission bus output multicast group address and multicast group mapping relations to interchanger;
D, primary processor according to from Network Capture get the stream instruction, obtain image and decoding behind the coding by network from video source, by the interchanger that is connected with the parallel transmission bus, it is extremely a plurality of from processor to export decoded image;
E, a plurality of decoded image being stored in from processor show in the address, according to son screen Splicing model decoded image is intercepted, and image to the sub-screen display after the output intercepting are shown;
Described son screen Splicing model comprises information, and each height screen and from the corresponding relation of processor of a plurality of son screens that splice; Described port configuration information comprises port information, and the port information of a plurality of interchangers that connect from processor of the interchanger that primary processor connects.
In the said method, steps A is described to be comprised from processor to a plurality of by the interchanger output screen Splicing model that is connected with the parallel transmission bus:
A1, described splicing control module be by the parallel transmission bus, son shielded Splicing model and port configuration information exports interchanger to;
A2, described interchanger obtain connected a plurality of port information from processor according to port configuration information, and by the corresponding port, output screen Splicing model is to a plurality of from processor.
In the said method, the described interchanger by being connected with the parallel transmission bus of step D, export decoded image and comprise from processor to a plurality of:
D1, described primary processor are exported decoded image to the multicast group address of interchanger;
D2, described interchanger are according to port configuration information, multicast group address and multicast group mapping relations, and the decoded image that will read from the multicast group address exports to a plurality of from processor.
As seen from the above technical solutions, the invention provides a kind of system and method for realizing screen splicing, the splicing control module reaches the interchanger that is connected with the parallel transmission bus by the parallel transmission bus, sends the multicast group address to primary processor, and it is extremely a plurality of from processor to send son screen Splicing model; The image of primary processor after to the coding that obtains from video source by network decoded, and sends decoded image to a plurality of from processor by the interchanger that is connected with the parallel transmission bus; According to the son screen Splicing model that receives, the decoded image that interchanger is sent intercepts a plurality of each from processor from processor, and the image after the output intercepting is to connected son screen.Adopt system and method for the present invention, the decoding of the image after being encoded by a primary processor, the time-delay of having avoided a plurality of distinct devices to decode respectively causing is inconsistent, carry out the transmission of data and information by parallel transmission bus and network-bus, avoided the time-delay in the transmission course inconsistent, omit complicated time synchronized control algolithm, reduced the consumption to system resource, improved the precision of the each several part image synchronization of splicing.
Description of drawings
Fig. 1 is the structural representation of existing large screen splicing system.
Fig. 2 (a) realizes the structural representation of the system of screen splicing for the present invention.
Fig. 2 (b) realizes the structural representation of embodiment one of the system of screen splicing for the present invention.
Fig. 3 is the method flow diagram that the present invention realizes screen splicing.
Embodiment
For make purpose of the present invention, technical scheme, and advantage clearer, referring to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.
In the system and method for realization screen splicing provided by the invention, from a plurality of processors, select a processor as primary processor, this primary processor is to decoding by the image behind the coding of Network Capture, inconsistent problem time delay of having avoided different decoding devices to decode respectively and produce in the decode procedure that causes has improved synchronism; Primary processor is by the parallel transmission bus, with interconnected (the PCI Express of high speed external unit, PCIe) mode of multicast sends decoded image to a plurality of from processor, and the method for this parallel transmission data has been avoided the delay that produces in the transmission course, has further improved synchronism.
Splicing control module of the present invention is specially the splicing control module and obtains external information by network-bus by the Network Capture external information; Primary processor of the present invention is undertaken alternately by network and video source, is specially primary processor and is undertaken alternately by network-bus and video source; Among the following embodiment, only as an example of network-bus example explanation splicing control module and network be connected and the network connection of primary processor and video source concerns.
Fig. 2 (a) realizes the structural representation of the system of screen splicing for the present invention.Now in conjunction with Fig. 2 (a), the present invention is realized the structure of the system of screen splicing describes, specific as follows:
System shown in Fig. 2 (a) connects n son screen, is used for realizing the screen splicing of n son screen; Wherein, n is the integer more than or equal to 1.
The present invention realizes that the system of screen splicing comprises: video source 20, splicing control module 21, network-bus 22, parallel transmission bus 23, interchanger 24, primary processor 25 and n are individual from processor.
The structure of video source 20 comprises a video camera 202 that be used for to gather image and one and is used for video encoder 201 that the image of video camera 202 outputs is encoded; Wherein, video encoder 201 can adopt digital video code (Digital Video Server, DVS) etc. to have the equipment of encoding function.Video source 20 is used for gathering image and coding, and the primary processor that is connected to network-bus 22 is carried out legitimate verification, and the image behind the coding is sent to primary processor by legitimate verification by network-bus 22.
Wherein, son screen Splicing model comprises the information of a plurality of son screens that splice, and each height screen and from the corresponding relation of processor, such as, connect upper from hardware, totally 4 sub screens are spliced a screen by 1*4, but when concrete the application, only utilize 3 adjacent in this screen screens to show, namely the son screen 1, son screen 2 and son screen 3, and the processor that 3 the son screens adjacent with this are connected is set to from processor, namely from processor A 1, from processor A 2 with from processor A 3, then son screen Splicing model comprises: the information that above-mentioned 3 adjacent sons shield and and above-mentioned 3 adjacent information from processor that the son screen is connected.
Port configuration information comprises: the port information of the interchanger 24 that primary processor connects, and the port information of a plurality of interchangers 24 that connect from processor, such as, primary processor 25 shown in Figure 2, from processor A 1 to from processor A n, port configuration information comprises port numbers, and the port numbers from processor A 1 to the interchanger 24 that connects from processor A n of the interchanger 24 that primary processor connects.
Interchanger 24 is according to the port configuration information that receives, and by the corresponding port, output screen Splicing model is extremely from processor; To from the demonstration address that processor is uploaded, export splicing control module 21 to by parallel transmission bus 23; According to port configuration information, output multicast group address is to primary processor 25; Read decoded image from the multicast group address, obtain the multicast group mapping relations corresponding with it according to the multicast group address, according to multicast group mapping relations and port configuration information, export decoded image to a plurality of from processor.Interchanger 24 is according to primary processor 25 and multicast group address, the decoded image that primary processor 25 is uploaded is temporary in the multicast group address, from the multicast group address, read again decoded image, through after copying, export decoded image to a plurality of from processor.
Only comprise an interchanger 24 that is used for carrying out decoded image transmitting in the system shown in Figure 2, in actual applications, can reach according to concrete needs the number of the processor that is connected with interchanger 24 in the number of parallel transmission bus 23 increase interchangers 24, so that this system is expanded, and then realize more splicing and the demonstration of multi-screen.
A plurality of arbitrary from processor receive son screen Splicing models from processor by interchanger 24, according to son screen Splicing model, it are shown address by interchanger 24 and parallel transmission bus 23, are uploaded to splicing control module 21; Decoded image is temporary in it to be shown in the address; According to son screen Splicing model, it is shown that the decoded image of preserving in the address intercepts, and the image after will intercepting exports connected son screen to.Particularly, a plurality of can be by the display channel that is connected with son screen from processor, the image after the output intercepting to connected son shields; Carry out the required parameter of parameter initialization from the display channel of processor antithetical phrase screen, but pre-save can be contained in also in the son screen Splicing model in from processor.
Shown in Figure 2 uploads its inner demonstration address for storing decoded image from processor, and, the a plurality of demonstration addresses from processor that belong to same multicast group are identical, such as, belong to same multicast group from processor A 1, from processor A 2, can adopt identical demonstration address from processor A 3, store decoded image.
Fig. 2 (b) realizes the structural representation of embodiment one of the system of screen splicing for the present invention.Now in conjunction with Fig. 2 (b), the structure of system embodiment one of the present invention is described, specific as follows:
The system architecture difference of the structure of system embodiment one of the present invention and Fig. 2 (a) is that the concrete structure of interchanger 24 reaches the number from processor, and the structure of other ingredients is identical, does not repeat them here.In the present embodiment, be M*n from the number of processor, M is the integer more than or equal to 1, and n is the integer more than or equal to 1; From processor A 1 to connecting same crosspoint from processor A n, from processor B 1 to connecting same crosspoint from processor B n, the like.
Interchanger 24 comprises first order crosspoint 241 and a plurality of second level crosspoint 242; First order crosspoint 241 and second level crosspoint 242 can adopt existing PCIe interchanger.
First order crosspoint 241 connects respectively parallel transmission bus 23 and a plurality of second level crosspoint 242, son is shielded Splicing model, port configuration information, multicast group address and multicast group mapping relations export a plurality of second level crosspoint 242 to; With being connected with the demonstration address that sends from the second level crosspoint 242 of processor, export splicing control module 21 to; The decoded image that the second level crosspoint 242 that is connected with primary processor 25 is sent is temporary in the multicast group address, will export from the decoded image that the multicast group address reads a plurality of second level crosspoint 242 to.
Arbitrary second level crosspoint 242 connects respectively first order crosspoint 241 and at least one processor; Be connected with the second level crosspoint 242 of primary processor 25 according to the port configuration information that receives, output multicast group address exports the decoded image of primary processor 25 transmissions to the multicast group address of first order crosspoint 241 to primary processor 25; Be connected with second level crosspoint 242 from processor according to the port configuration information that receives, son shielded Splicing model export to connectedly from processor, will export first order crosspoint 241 to from the demonstration address of processor; According to multicast group mapping relations and port configuration information, the decoded image that first order crosspoint 241 is exported exports to connected from processor.
Each second level crosspoint 242 in a plurality of second level of the present invention crosspoint 242 can learn that according to port configuration information connected processor is to belong to primary processor 25, still belongs to from processor; Second level crosspoint 242 is exported corresponding information to primary processor 25 or from processor according to port configuration information.
In the system embodiment of the present invention, parallel transmission bus 23 can adopt PCIe bus etc. in order to carry out the bus of parallel data transmission; Primary processor 25 and n all can be adopted codec type digital signal processor (Digital Signal Processor, DSP) from processor, no longer its structure be given unnecessary details at this.
Fig. 3 is the method flow diagram that the present invention realizes screen splicing.Now in conjunction with Fig. 3, the present invention is realized the method for screen splicing describes, specific as follows:
Step 300: the splicing control module shields Splicing model to interchanger according to the splicing instruction of obtaining from network-bus by parallel transmission output end of main mouth configuration information and son;
Wherein, son screen Splicing model comprises information, and the corresponding relation of each height screen and processor of a plurality of son screens that splice, and the processor here refers to is primary processor 25 or from processor.Port configuration information comprises port information, and the port information of a plurality of interchangers 24 that connect from processor of the interchanger 24 that primary processor 25 connects.
Step 301: according to the son screen Splicing model that obtains from interchanger, by the interchanger that is connected with the parallel transmission bus, upload it and show that the address is to the parallel transmission bus from processor;
This step comprises: step 3011,, determine in order to store the demonstration address of decoded image according to the son screen Splicing model that obtains from interchanger 24 from processor; Step 3012 will show that from processor the address is uploaded to interchanger 24; Step 3013, interchanger 24 will show that the address is uploaded to the parallel transmission bus.
Step 302: the splicing control module generates multicast group address and multicast group mapping relations according to from the demonstration address from processor that the parallel transmission bus is obtained, and sends multicast group address and multicast group mapping relations to the parallel transmission bus;
This step comprises: step 3021, and splicing control module 21 generates a multicast group address according to from the demonstration address from processor that parallel transmission bus 23 is obtained; Step 3022, splicing control module 21 generate multicast group mapping relations according to port configuration information and the multicast group address obtained from network-bus 22; Step 3023, splicing control module 21 exports multicast group address and multicast group mapping relations to parallel transmission bus 22.
Step 303: interchanger sends the multicast group address to primary processor;
Step 304: primary processor is got the stream instruction according to what obtain from network-bus, obtain the image behind the coding and decode from video source by network-bus, with decoded image uploading to the multicast group address;
This step comprises: step 3041, primary processor 25 are got the stream instruction according to what obtain from network-bus 22, send identification information to video source 20 by network-bus 22; Step 3042, primary processor 25 are obtained the image behind the coding of video source 20 outputs from network-bus 22 after receiving the response that the legitimate verification of video source 20 by network-bus 22 feedback pass through; Step 3043, the image behind 25 pairs of codings of primary processor is decoded, and obtains decoded image; Step 3044, primary processor 25 with decoded image uploading to the multicast group address of interchanger 24.
Wherein, 20 of primary processor 25 and video source is mutual in step 3041 and the step 3042, has realized the legitimate verification of 20 pairs of primary processors 25 of video source, so that primary processor 25 obtains the image behind the coding corresponding with its authority; Identification information can be the information that username and password etc. is used for carrying out legitimate verification.
Step 305: the decoded image that interchanger will read from the multicast group address exports to a plurality of from processor;
This step comprises: step 3051, interchanger 24 read the decoded image that primary processor 25 is uploaded from the multicast group address; Step 3052, interchanger 24 obtains multicast group mapping relations according to the multicast group address; Step 3053, interchanger 24 are exported a plurality of from processor that decoded image to this multicast group comprises according to port configuration information and multicast group mapping relations.
Step 306: the decoded image that will receive from processor is stored in the demonstration address, and according to the son screen Splicing model that receives, to from showing that the decoded image that read the address intercepts, exports the extremely connected son screen of image after intercepting;
This step comprises: step 3061, a plurality of from processor arbitrary decoded image being temporary in from processor show in the address; Step 3062, a plurality of from processor arbitrary from processor according to the son that receives screen Splicing model, the display channel of connexon screen is carried out parameter initialization; Step 3063, a plurality of arbitrary from processor, intercept being stored in the decoded image that shows in the address according to son screen Splicing model when the initialization success of confirming display channel from processor; Step 3064, a plurality of arbitrary from the display channel of processor by the initialization success from processor, image to the sub-screen display after the output intercepting is shown.
Wherein, but when processor carries out initialization to display channel required parameter pre-save in this from processor, also portability is in the information of son screen Splicing model.
Step 307: finish.
In the above-mentioned preferred embodiment of the present invention, splicing control module 21 is by interchanger 24, obtain the demonstration address of uploading from processor, but splicing control module 21 obtains from the method for the demonstration address of processor, is not limited to this a kind of method in the present embodiment, such as, splicing control module 21 also can pass through network-bus 22, obtain the demonstration address from processor, this demonstration address is that the outside sets in advance, and is not to upload in real time from processor.
In the above-mentioned preferred embodiment of the present invention, network-bus be used for video source with for communicating by letter between the primary processor that carries out image decoding, parallel transmission bus and interchanger are used for the decoded image of parallel transmission to a plurality of from processor, have reduced the time-delay that produces in the transmission course; Realized the decoding of image behind the coding by equipment of primary processor, a plurality of only is intercepting and the output display of carrying out decoded image from processor, reduced the inconsistent problem of time-delay that each equipment is decoded respectively and produced, not only saved complicated time synchronized control algolithm, reduce the consumption to system resource, and improved the precision of the each several part image synchronization of splicing.
The above only is preferred embodiment of the present invention, and is in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, is equal to replacement, improvement etc., all should be included within the scope of protection of the invention.
Claims (5)
1. a system that realizes screen splicing receives the data from video source, it is characterized in that this system comprises:
The splicing control module receives splicing instruction, port configuration information and son screen Splicing model from client by network, and by parallel transmission output end of main mouth configuration information and son screen Splicing model to interchanger; According to coming since the demonstration address of processor, generate multicast group address and multicast group mapping relations, and export interchanger to by the parallel transmission bus; Described son screen Splicing model comprises information, and each height screen and from the corresponding relation of processor of a plurality of son screens that splice; Described port configuration information comprises port information, and the port information of a plurality of interchangers that connect from processor of the interchanger that primary processor connects; Described multicast group mapping relations are the multicast group address and the corresponding relation of the port information of a plurality of interchangers that are connected from processor;
Interchanger, according to port configuration information, output screen Splicing model is to a plurality of from processor; According to port configuration information, output multicast group address is to primary processor; According to port configuration information, multicast group address and multicast group mapping relations, the decoded image that will read from the multicast group address exports to a plurality of from processor;
Primary processor, according to network output get the stream instruction, undertaken alternately by network and video source, also decode by the image behind the Network Capture coding, upload decoded image to the multicast group address of interchanger; Describedly get the image behind the coding is obtained in the stream instruction from video source for the indication primary processor instruction;
A plurality of from processor, wherein arbitrary son that receives from the processor basis shields Splicing model, by the interchanger that is connected with the parallel transmission bus, upload it and show that the address is to splicing control module, the decoded image of interchanger output is stored in the demonstration address, and according to son screen Splicing model, intercept showing the decoded image in the address, the image after the output intercepting is to connected son screen.
2. system according to claim 1 is characterized in that, described interchanger comprises:
First order crosspoint will export a plurality of second level crosspoint to from son screen Splicing model, port configuration information, multicast group address and the multicast group mapping relations that the parallel transmission bus is obtained, and the demonstration address with obtaining exports the parallel transmission bus to; The decoded image that obtains is write in the multicast group address, and the decoded image that will read from the multicast group address exports a plurality of second level crosspoint to;
A plurality of second level crosspoint, the arbitrary second level crosspoint that comprises connect respectively first order crosspoint and at least one processor; Be connected with the second level crosspoint of described primary processor according to port configuration information, output multicast group address is to primary processor, and decoded image and multicast group address that primary processor is sent export first order crosspoint to; Be connected with second level crosspoint from processor according to port configuration information, output screen Splicing model will export first order crosspoint to from the demonstration address of processor to from processor; According to multicast group address, multicast group mapping relations and port configuration information, export decoded image extremely from processor.
3. system according to claim 2 is characterized in that, described first order crosspoint is the outside interconnected PCIe interchanger of high speed; Described second level crosspoint is the PCIe interchanger.
4. method that realizes screen splicing is characterized in that the method comprises:
A, splicing control module are exported son screen Splicing model to a plurality of from processor according to splicing instruction, son screen Splicing model and port configuration information from Network Capture by the interchanger that is connected with the parallel transmission bus;
Described interchanger output screen Splicing model by being connected with the parallel transmission bus comprises from processor to a plurality of: A1, described splicing control module be by the parallel transmission bus, son shielded Splicing model and port configuration information exports interchanger to; A2, described interchanger obtain connected a plurality of port information from processor according to port configuration information, and by the corresponding port, output screen Splicing model is to a plurality of from processor;
B, a plurality of son screen Splicing model that receives from the processor basis by the interchanger that is connected with the parallel transmission bus, are uploaded it and are shown that address is to splicing control module;
C, splicing control module generate multicast group address and multicast group mapping relations according to coming since the demonstration address of processor, by parallel transmission bus output multicast group address and multicast group mapping relations to interchanger;
D, primary processor according to from Network Capture get the stream instruction, obtain image and decoding behind the coding by network from video source, by the interchanger that is connected with the parallel transmission bus, it is extremely a plurality of from processor to export decoded image; Describedly get the image behind the coding is obtained in the stream instruction from video source for the indication primary processor instruction;
E, a plurality of decoded image being stored in from processor show in the address, according to son screen Splicing model decoded image is intercepted, and image to the sub-screen display after the output intercepting are shown;
Described son screen Splicing model comprises information, and each height screen and from the corresponding relation of processor of a plurality of son screens that splice; Described port configuration information comprises port information, and the port information of a plurality of interchangers that connect from processor of the interchanger that primary processor connects.
5. method according to claim 4 is characterized in that, the described interchanger by being connected with the parallel transmission bus of step D is exported decoded image and comprised from processor to a plurality of:
D1, described primary processor are exported decoded image to the multicast group address of interchanger;
D2, described interchanger are according to port configuration information, multicast group address and multicast group mapping relations, and the decoded image that will read from the multicast group address exports to a plurality of from processor.
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