CN102222669B - Silicon controlled rectifier used for ESD protection - Google Patents

Abstract

The invention discloses a silicon controlled rectifier for electrostatic protection, which comprises a pull-up silicon controlled rectifier, a pull-down silicon controlled rectifier, an isolation resistor, an NMOS transistor and a PMOS transistor, and the pull-up silicon controlled rectifier includes a first The first N well of the P+ implantation region and the first N+ implantation region and the first P well respectively having the second P+ implantation region and the second N+ implantation region, and the pull-down thyristor includes the third P+ implantation region and the third P+ implantation region respectively. The second N well with the third N+ injection region and the second P well with the fourth P+ injection region and the fourth N+ injection region respectively. The invention utilizes the parasitic PN diode structure and the parasitic well resistance structure in the silicon controlled rectifier to form a voltage clamping structure to realize the fast response of the ESD pulse and the pre-opening of the protection structure. It protects the fragile gate oxide layer from instantaneous and fast ESD electrostatic shock.

Description

A thyristor for electrostatic protection

technical field

The invention belongs to the field of integrated circuits, in particular to a thyristor for improving the reliability and static power consumption of an integrated circuit ESD protection device based on a thyristor.

Background technique

The phenomenon of electrostatic discharge (ESD) in nature poses a serious threat to the reliability of integrated circuits. In the industry, 30% of the failures of integrated circuit products are caused by electrostatic discharge, and the increasingly smaller process size and thinner gate oxide thickness greatly increase the probability of integrated circuit damage by electrostatic discharge. Therefore, improving the reliability of integrated circuit electrostatic discharge protection has a non-negligible effect on improving the yield of products.

The modes of electrostatic discharge phenomena are usually divided into four types: HBM (Human Body Model), MM (Machine Discharge Model), CDM (Component Charge Discharge Model) and Field Induction Model (FIM). The two most common electrostatic discharge modes that industrial products must pass are HBM and MM. When an electrostatic discharge occurs, the charge usually flows in from one pin of the chip and flows out from the other pin. At this time, the current generated by the electrostatic charge is usually as high as several amperes, and the voltage generated at the charge input pin is as high as several volts or even Dozens of volts. If a large ESD current flows into the internal chip, it will cause damage to the internal chip. At the same time, the high voltage generated at the input pin will also cause gate oxide breakdown of the internal device, resulting in circuit failure. Therefore, in order to prevent the internal chip from being damaged by ESD, each pin of the chip must be effectively protected against ESD to discharge the ESD current.

In the normal working state of the integrated circuit, the electrostatic discharge protection device is in a closed state and will not affect the potential on the input and output pins. When external static electricity is poured into the integrated circuit to generate an instantaneous high voltage, the device will turn on and discharge the static electricity quickly.

Because of the short time and high energy of ESD static electricity, it often has an instantaneous impact on the circuit and causes damage to the components in the circuit. This requires that the ESD protection structure not only has good current discharge capability, but also has a faster response speed to ESD static electricity.

In ESD protection, the gate protection of MOS transistors at the input and output terminals has always been a difficult problem, because the modern integrated circuit manufacturing process continues to improve, the device size continues to decrease, and the thickness of the gate oxide layer of the MOS transistors has also been reduced again and again. The rapid ESD impact is becoming more and more fragile, so it is very necessary to design a fast reaction structure to ensure that the gate oxide layer is not damaged before the ESD protection structure is opened.

As a commonly used ESD protection structure, thyristors are widely used in the protection of integrated circuit chip I/O ports and power domains. Thyristor has the advantages of uniform conduction and high ESD capability. However, the thyristor also has the disadvantages of slow turn-on speed and high turn-on voltage, which cannot effectively protect the gate oxide layer of the MOS transistor at the input and output ends of the integrated circuit.

Contents of the invention

The invention provides a silicon controlled rectifier for electrostatic protection, which can ensure that the gate of the MOS transistor at the input and output ends is not broken down in advance before the protection structure of the silicon controlled rectifier is turned on.

A thyristor with an electrostatic protection structure, including a pull-up thyristor, a pull-down thyristor, an isolation resistor, an NMOS transistor and a PMOS transistor,

The pull-up thyristor includes a first N well and a first P well, wherein the first N well has a first P+ implantation region and a first N+ implantation region respectively, and the first P well has a second P+ implantation region respectively. region and the second N+ implant region;

The pull-down thyristor includes a second N well and a second P well, wherein the second N well has a third P+ implantation region and a third N+ implantation region respectively, and the second P well has a fourth P+ implantation region respectively and a fourth N+ implantation region;

The first P+ injection region and the first N+ injection region in the first N well of the pull-up thyristor are connected to the power line, and the second P+ injection region in the first P well is connected to the second N well of the pull-down thyristor. The third N+ injection region and the isolation resistor, the second N+ injection region in the first P well of the pull-up thyristor and the third P+ injection region in the second N well of the pull-down thyristor are connected to the input and output terminals;

The third P+ implantation region in the second N well of the pull-down thyristor and the second N+ implantation region in the first P well of the pull-up thyristor are connected to the input and output terminals, and the third N+ implantation region in the second N well is The region is connected to the second P+ injection region and the isolation resistor in the first P well of the pull-up thyristor, and the fourth P+ injection region and the fourth N+ injection region grounding line in the second P well of the pull-down thyristor;

The anode of the isolation resistor is connected to the second P+ injection region in the first P well of the pull-up thyristor and the third N+ injection region in the second N well of the pull-down thyristor, and the cathode of the isolation resistor is connected to the gate of the PMOS transistor and the NMOS transistor. tube grid;

The source and the drain of the PMOS transistor are connected to the power line;

The drain and source of the NMOS transistor are grounded.

Based on the standard CMOS technology, the invention utilizes the characteristics of the forward conduction of the parasitic diode in the thyristor and the rapid opening of the diode in the case of ESD to realize the rapid response of the ESD pulse and the pre-opening of the protection structure.

When the ESD signal is generated at the input and output terminals, the ESD pulse from the input and output terminals to the ground will first pass through the parasitic diode of the pull-down thyristor, so that there will be a period of diode conduction time before the pull-down thyristor starts to work, preventing the gate The pole oxide layer is broken down by a rapid electrostatic charge. Similarly, when the power line generates ESD to the input and output terminals, the ESD pulse will first pass through the parasitic forward diode of the pull-up thyristor to conduct and discharge part of the current in advance.

The process of the entire thyristor fully turning on and discharging the ESD current is when the reverse PN junction in the thyristor reaches the breakdown voltage and the thyristor reaches the turn-on current, and the thyristor turns on, although the turning on of the thyristor requires a certain amount of time. Time and current value, but does not affect the turn-on of the parasitic diode. Before the thyristor is turned on, the parasitic diode will ensure that the gate oxide layer is not damaged.

The invention utilizes the parasitic PN diode structure and the parasitic well resistance structure in the thyristor to form a voltage clamping structure, and clamps the voltage acting between the gate and source of the PMOS transistor and the NMOS transistor at a relatively low voltage when the electrostatic energy arrives. The low voltage value and rapid response can ensure that the gate will not be broken down before the thyristor protection structure is turned on.

The invention adopts the parasitic diode structure and the parasitic well resistance in the thyristor to save area, has simple structure, uniform current, good device robustness, stability and reliability.

Description of drawings

Fig. 1 is a schematic diagram of a silicon controlled rectifier used for electrostatic protection according to the present invention.

FIG. 2 is a schematic diagram of the structure of the pull-up silicon controlled rectifier of the present invention.

Fig. 3 is a schematic diagram of the structure of the pull-down thyristor of the present invention.

Fig. 4 is a working schematic diagram of the present invention before the thyristor is turned on.

Detailed ways

The structure of P well, N well, N+, P+ injection region, PMOS, NMOS and isolation resistance in the present invention can all be realized by using the existing standard CMOS integrated circuit manufacturing process.

As shown in Figures 1-3, a thyristor with an electrostatic protection structure includes a pull-up thyristor 11, a pull-down thyristor 12, an isolation resistor 13, an NMOS transistor 14, and a PMOS transistor 15. The pull-up thyristor 11 includes a first N well 21 and a first P well 22, wherein the first N well 21 has a first P+ implantation region 23 and a first N+ implantation region 24 respectively, and the first P well 22 has a first P+ implantation region 24 respectively. The second P+ implantation region 25 and the second N+ implantation region 26;

The pull-down thyristor 12 includes a second N well 31 and a second P well 32, wherein the second N well 31 has a third P+ injection region 33 and a third N+ implant region 34 respectively, and the second P well 32 has There are respectively a fourth P+ implantation region 35 and a fourth N+ implantation region 36;

The first P+ injection region 23 and the first N+ injection region 24 in the first N well 21 of the pull-up thyristor 11 are connected to the power line, and the second P+ injection region 25 in the first P well 22 is connected to the pull-down controllable The third N+ implantation region 34 and the isolation resistor 13 in the second N well 31 of the silicon 12, the second N+ implantation region 26 in the first P well 22 of the pull-up thyristor 11 and the second N well 31 of the pull-down thyristor 12 The third P+ injection region 33 in the connection is connected to the input and output terminals;

The third P+ implantation region 33 in the second N well 31 of the pull-down thyristor 12 and the second N+ implantation region 26 in the first P well 22 of the pull-up thyristor 11 are connected to the input and output ends, and the second N well The third N+ injection region 34 in 31 is connected to the second P+ injection region 25 in the first P well 22 of the pull-up thyristor 11 and the isolation resistor 13, and the fourth P+ injection in the second P well 32 of the pull-down thyristor 12 Region 35 and the fourth N+ injection region 36 are grounded;

The anode of the isolation resistor 13 is connected to the second P+ injection region 25 in the first P well 22 of the pull-up thyristor 11 and the third N+ injection region 24 in the second N well 31 of the pull-down thyristor 12. 13 The cathode is connected to the gate of the PMOS transistor 14 and the gate of the NMOS transistor 15; the source and drain of the PMOS transistor 14 are connected to the power line; the drain and source of the NMOS transistor 15 are grounded.

As shown in Figure 4, after the ESD signal from the input and output terminals to the ground wire is generated, the ESD pulse will pass through the pull-down parasitic diode 17 in the pull-down thyristor 12 preferentially, so that the pull-down parasitic diode 17 will be closed before the pull-down thyristor 12 is turned on. Part of the current is released in advance to ensure that the grid of the NMOS transistor 15 is not damaged by the fast ESD pulse. When the ESD pulse reaches the breakdown voltage of the reverse PN junction of the pull-down thyristor 12, the pull-down thyristor 12 turns on to discharge the ESD current. Similarly, when the ESD signal on the input and output terminals of the power line is generated, the ESD pulse will first flow into the input and output terminals through the pull-up parasitic diode 16 in the pull-up thyristor 11 to discharge, thus ensuring that the PMOS tube 14 will not be quickly ESD Pulse damaged.

Claims (1)

1. a controllable silicon that is used for electrostatic defending comprises and draws controllable silicon (11), drop-down controllable silicon (12), isolation resistance (13), NMOS pipe (14) and PMOS pipe (15), it is characterized in that:

Draw controllable silicon (11) to comprise a N trap (21) and a P trap (22) on described; The one a P+ injection region (23) and a N+ injection region (24) are wherein arranged respectively on the N trap (21), the 2nd P+ injection region (25) and the 2nd N+ injection region (26) are arranged respectively on the P trap (22);

Described drop-down controllable silicon (12) comprises the 2nd N trap (31) and the 2nd P trap (32); The 3rd P+ injection region (33) and the 3rd N+ injection region (34) are wherein arranged respectively on the 2nd N trap (31), the 4th P+ injection region (35) and the 4th N+ injection region (36) are arranged respectively on the 2nd P trap (32);

Draw a P+ injection region (23) and a N+ injection region (24) in controllable silicon (11) the N trap (21) to connect power line on described; The 2nd P+ injection region (25) in the one P trap (22) connects the 3rd N+ injection region (34) and the isolation resistance (13) in drop-down controllable silicon (12) the 2nd N trap (31), on draw the 3rd P+ injection region (33) in the 2nd N+ injection region (26) and drop-down controllable silicon (12) the 2nd N trap (31) in controllable silicon (11) the P trap (22) to connect input/output terminal;

The 3rd P+ injection region (33) in described drop-down controllable silicon (12) the 2nd N trap (31) with on draw the 2nd N+ injection region (26) in controllable silicon (11) the P trap (22) to connect input/output terminal; The 3rd N+ injection region (34) in the 2nd N trap (31) connects the 2nd P+ injection region (25) and the isolation resistance (13) that draws in controllable silicon (11) the P trap (22), the 4th P+ injection region (35) in drop-down controllable silicon (12) the 2nd P trap (32) and the 4th N+ injection region (36) earth connection;

Said isolation resistance (13) anode connects the 3rd N+ injection region (34) in the 2nd N trap (31) of the 2nd P+ injection region (25) and drop-down controllable silicon (12) in the P trap (22) that draws controllable silicon (11), and isolation resistance (13) negative electrode connects PMOS pipe (14) grid and manages (15) grid with NMOS;

The source electrode and the drain electrode of said PMOS pipe (14) connect power line;

The drain electrode and the source ground line of said NMOS pipe (15).

Images