CN102244087A - Controllable power flip array light emitting diode (LED) chip and manufacturing method thereof - Google Patents

Abstract

The invention discloses a controllable power flip-chip array LED chip and a manufacturing method thereof. The controllable power flip-chip array LED chip is as follows: the array LED chip is composed of a plurality of array units, wherein all the array units are connected to the p-electrode layer (10) of each row, and the n-electrode layer (5) of each column is connected; The array unit is covered with n-type buffer layer (3), n-type semiconductor layer (6), active layer (7), p-type semiconductor layer (8), transparent electrode layer (9), p-electrode layer (10); all n-electrode layers (5) and p-electrode layers (10) are covered by an insulating layer (4); wherein the p-electrode layer (10) of each row passes above the window of the p-electrode layer (10) The p-electrode is connected to the metal layer (11); there is also a passivation layer (12) on the surface of the p-electrode connection metal layer (11).

Description

Controllable power flip-chip array LED chip and manufacturing method thereof

technical field

The invention relates to a flip-chip array LED chip and a manufacturing method thereof, in particular to a GaN-based controllable flip-chip array blue LED chip structure including multiple quantum well active regions and a manufacturing method thereof.

Background technique

White LED has the advantages of high brightness, energy saving and environmental protection, and has become one of the most potential lighting sources. The energy consumption of white light LED is only 1/8 of that of incandescent lamp and 1/2 of that of fluorescent lamp, and its life span can be as long as 100,000 hours. This can be described as "once and for all" for ordinary households. At the same time, it can also achieve mercury-free and easy recycling, which is of great significance to environmental protection and energy conservation.

The current method of preparing high-power white LEDs is mainly to coat yellow phosphor powder on blue or near-ultraviolet LED chips, and obtain white light through color mixing. This method of obtaining white light through blue LEDs has a simple structure, low cost, and high technical maturity, so it is widely used. Most high-power white LEDs above 5W are made of high-power blue LED chips. Therefore, manufacturing high-power blue LED chips is the basis for making high-power white LEDs.

At present, the LEDs that adjust the luminance are mainly in the following ways: first, a single LED chip mainly controls the current through the LED chip to adjust the luminance; second, the combination of multiple LED chips controls the current of multiple LED chips. Switch to adjust the brightness of the light. However, because each LED chip may not be produced in the same batch, the electrical and optical properties will be different. Through the above control method to connect the design and power drive, the coordination and consistency of the light emission of the combined chip is poor.

At present, monochrome display screens are used in outdoor advertisements and small mobile digital devices, so the development of LED monochrome display screens also has a broad application prospect.

Contents of the invention

The technical problem to be solved by the present invention is to provide a controllable power flip-chip array LED chip, which can effectively adjust the luminous brightness of the high-power blue LED flip-chip, and can also be used as a monochrome display screen. Scanning achieves the purpose of displaying characters; in addition, the present invention also provides a manufacturing method of the chip, so as to overcome the shortcomings of the prior art such as difficulty in adjusting the luminance of the LED chip.

The controllable power flip-chip array LED chip structure of the present invention is as follows: the array LED chip is composed of a plurality of array units, wherein the p-electrode layers of each row of all array units are connected together, and the n-electrode layers of each column are connected together. In this way, each array unit can be individually controlled to emit light; the array unit is sequentially covered with an n-type buffer layer, an n-type semiconductor layer, an active layer, a p-type semiconductor layer, a transparent electrode layer, and a p-electrode layer above the sapphire substrate; each column The n-electrode layers of the array unit are connected together; and all n-electrode layers and p-electrode layers are covered by an insulating layer; the p-electrode connection metal layer above the p-electrode layer window covered by the insulating layer makes the p-electrodes of each row connected to Together. The light-emitting surface of the sapphire substrate is a roughened surface to increase the light-emitting rate; there is also a passivation layer on the surface of the p-electrode connection metal layer. The p-electrode layer of the chip uses metals such as silver or aluminum with high light reflectivity to increase light reflection, and completely covers the transparent electrode layer of each array unit.

Among them, the light-emitting surface of the LED chip is a sapphire substrate, and sapphire (Al ₂ O ₃ ) is used; and the surface of the light-emitting surface is roughened to form a rough surface, so as to reduce the reflection of light on the light-emitting surface and improve the light-extracting rate. Improve the luminous efficiency of LED.

The n-type semiconductor layer and the p-type semiconductor layer are composed of GaN, or GaAs, or AlGaN semiconductor materials; wherein the impurities doped in the n-type semiconductor layer are materials such as Si, and the impurities doped in the p-type semiconductor layer are Mg, etc. Material; the active layer adopts multi-layer InGaN layer and GaN layer to form multiple quantum well layers.

The LED chip of the present invention is composed of mutually independent array units forming an array. However, the n-electrode layers of each row of array units are connected together; the material of the n-electrode layer includes Cu, Ti, Al, Ni or Au metal, and a single metal or a combination of metals is used; High metal Ag or Al, and completely cover the transparent electrode layer of each array unit;

The p-electrode connection metal layer above the p-electrode layer window covered by the insulating layer connects the p-electrodes of each row together; the material of the p-electrode connection metal layer includes Cu, Ti, Al, Ni or Au metal, and a single one of them is used metal or combination of metals.

The insulating layer and passivation layer are made of insulating materials such as SiO _x , SiN _x or SiO _x N _y ; the transparent electrode layer is made of metal thin film Ni/Au or indium tin oxide (ITO).

The manufacturing method of the controllable power flip-chip array LED chip of the present invention comprises the following manufacturing steps:

Step 1, growing a low-doped n-type buffer layer on the sapphire substrate, and then growing a highly-doped n-type semiconductor layer;

Step 2, growing the active layer as a single layer of InGaN, or alternately growing multiple periods of InGaN layers and GaN layers to form multiple quantum well layers;

Step 3, growing a p-type semiconductor layer on the basis of step 2;

Step 4, depositing a transparent electrode layer and a p-electrode layer;

Step 5, on the basis of step 4, perform photolithography and etching to expose the n-type buffer layer and the isolation groove of the chip, and prepare for the deposition of the n-electrode;

Step 6, depositing a metal layer, and performing photolithography and etching to form n-electrode layers that are connected together in each row;

Step 7, deposit an insulating layer, and perform photolithography and etching to expose the p-electrode layer window to prepare for the deposition of the p-electrode connection metal layer above the p-electrode layer window; at the same time, expose the n-electrode pad on the edge of the chip for external circuits connect;

Step 8, depositing Cu, Ti, Al, Ni or Au metal, adopting a single metal or a combination of metals, and performing photolithography and etching to form a p-electrode connection metal layer and n-electrode that are connected together in each row of array units External pad for external circuit connection;

Step 9, depositing a passivation layer, and performing photolithography and etching to expose the p-electrode pad and n-electrode pad for external circuit connection;

In step ten, the sapphire substrate is thinned, and the light-emitting surface of the sapphire is roughened in an organized manner to form a roughened surface.

Steps 1 to 3 are prepared by MOCVD (metal organic compound vapor deposition) process, or by MBE (molecular beam epitaxy) method.

Step five adopts a wet etching process, adopts an ICP (enhanced plasma etching) method, or a RIE (reactive ion etching) method, or adopts a combination of the two methods.

Step 4, Step 6 and Step 7 use magnetron sputtering or electron beam evaporation to grow the transparent electrode layer and p-electrode layer. Step 7 uses PECVD (Plasma Enhanced Chemical Vapor Deposition) process to grow the insulating layer and passivation layer; Step 10 The sapphire substrate is thinned using CMP (Chemical Mechanical Polishing) process equipment.

Step 1: Grow a low-doped Si n-type GaN buffer layer on the sapphire substrate by MOCVD method, and then grow a highly-doped Si n-type GaN contact layer; that is, use TMGa (trimethylgallium), NH ₃ ( Ammonia) and silicon source SiH ₄ (silane) at 570 ° C to grow a 2 μm thick low-doped Si n-GaN buffer layer; and then grow a 20 nm high-doped Si n-type GaN contact layer;

Step 2, growing the active layer by MOCVD method. Multiple periods of InGaN layers and GaN layers are alternately grown to form multiple quantum wells—MQW layers. The specific process is:

1. Introduce the indium source TMIn (trimethylindium) to grow 3nm thick InGaN;

2. Remove the indium source and feed silane (SiH ₄ ) to grow n-GaN with a thickness of 20nm;

3. Repeat process 1 and 2 multiple times to grow InGaN/GaN multiple quantum wells;

Step 3: On the top of the MQW active layer, grow a p-type semiconductor layer by MOCVD, that is, inject TMGa (trimethylgallium), NH ₃ (ammonia) and Cp ₂ Mg (dimagnesium), and grow a 100nm-thick p-type semiconductor layer. Type semiconductor layer;

Step 4, after cleaning, deposit a layer of ITO transparent conductive film on the p-type semiconductor layer by magnetron sputtering as a transparent electrode layer, and deposit Ag or Al metal on the transparent electrode layer to form a p-electrode layer; transparent electrode The thickness of the layer is 500nm, and the thickness of the p-electrode layer is 120nm;

Step 5. On the basis of step 4, apply photoresist, mask, photolithography, and etch to expose the n-type buffer layer and the isolation groove of the chip, and prepare for the deposition of the n-electrode;

Step 6. Deposit Cu/Au (copper/gold) by magnetron sputtering, and the thickness of the deposited metal is 120nm; form an n-electrode layer, and perform photolithography and etching to form n-electrodes that are connected together in each row;

Step 7, using PECVD (Plasma Enhanced Chemical Vapor Deposition) to grow the SiO ₂ insulating layer, and performing photolithography and etching to expose the p-electrode window and prepare for the further deposition of the p-electrode connection metal layer above the p-electrode layer window; at the same time The n-electrode pad is exposed on the edge of the chip for external circuit connection;

Step 8. Use magnetron sputtering to deposit Cu/Au (copper/gold) and other metals to connect the metal electrode layer of the p-electrode. The thickness of this layer is 90-150 μm, and perform photolithography and etching to form each row of array units. The p electrodes connected together are connected to the metal and the n electrodes are connected to an external pad; for external circuit connection;

Step 9, remove the photoresist, and grow SiOx or SiNx passivation layer by PECVD, that is, form an 80nm thick _SiO2 passivation layer; and perform photolithography and etching to expose the p-electrode pad and n-electrode pad for external circuits connect;

Step 10. Use chemical mechanical polishing (CMP) equipment to thin the sapphire, that is, thin the sapphire substrate from 350 μm to 450 μm to 90 μm to 150 μm, and use photolithography plus ion etching to roughen the light-emitting surface of the sapphire in an organized manner treated to form a roughened surface.

A controllable power flip-chip array LED chip can be obtained based on the manufacturing method of the above steps. Compared with the traditional LED chip, the chip can not only increase the light-emitting area, but also can control the power supply of the rows and columns of the chip array. Whether to control the light emission of the array unit, so that the power of the chip can be controlled to achieve the purpose of controlling the brightness of the chip; it can also be used to display characters by controlling whether the row and column of the chip are energized or not through the external driving scanning circuit.

Adjusting the structure of the active layer (such as quantum wells of multiple materials to form a composite quantum well) and material components (adjusting the doping concentration to change the emission wavelength) can emit light of various colors, and the present invention also covers this category of LED chips.

The above-mentioned content of the present invention has only provided a kind of implementation scheme that realizes the present invention, but the chip structure and process condition in this scheme and scheme can be changed, and this change does not depart from the idea and scope of the present invention, and is of great importance to those skilled in the art. All changes apparent to the person himself should be included within the scope of the claims.

Description of drawings

Fig. 1 is a process flow diagram of the present invention;

Figure 2 is a diagram of the cross-section after epitaxial growth of n-GaN layer, n ⁺ -GaN layer, active layer, p-GaN layer, transparent electrode and Ag/Al metal electrode on the sapphire Al ₂ O ₃ (0001) surface substrate ;

Figure 3 The plan view obtained after photolithography and etching of the n-region electrode;

Fig. 4 is the A-A sectional view of Fig. 3;

Fig. 5 is the plane view obtained after n-region electrode etching;

Fig. 6 is the A-A sectional view of Fig. 5

Fig. 7 is the plane figure after _SiOx or SiNx insulation layer etching;

Fig. 8 is the A-A sectional view of Fig. 7;

9 is a plan view of the p-electrode connection metal line after deposition, photolithography and etching above the p-electrode region;

Fig. 10 is the A-A sectional view of Fig. 8;

Figure 11 Plane pattern after etching of _SiOx or SiNx passivation layer

Fig. 12 is a cross-sectional figure obtained after organized roughening treatment on the light-emitting surface of sapphire;

Reference signs:

1—roughened surface of sapphire substrate;

2—Sapphire substrate;

3—n-type buffer layer, namely n-GaN buffer layer;

4—(SiO _x or SiNx) insulating layer;

5—n electrode layer;

6—n semiconductor layer, that is, n ⁺ -GaN layer;

7—active layer;

8—p semiconductor layer, that is, p-GaN layer;

9—transparent electrode layer;

10—p electrode layer;

11—the p electrode is connected to the metal layer;

12—( _SiOx or SiNx) passivation layer.

Detailed ways

Embodiments of the present invention: Here, the chip structure and its manufacturing method of the present invention will be described by taking the "GaN-based power-controllable blue flip-chip LED chip that emits light from the surface of sapphire" as an example.

The chip structure of the present invention is: an array LED chip is formed by a plurality of array units, in which the p-electrode layers 10 of each row of all array units are connected together, and the n-electrode layers 5 of each column are connected together, so that they can be individually controlled Each array unit emits light; the array unit is sequentially covered with an n-type buffer layer 3, an n-type semiconductor layer 6, an active layer 7, a p-type semiconductor layer 8, a transparent electrode layer 9, and a p-electrode layer 10 above the sapphire substrate 2. ; The n-electrode layer 5 of each column array unit is connected together; And all n-electrode layers 5 and p-electrode layers 10 are covered by insulating layer 4; Layer 11 connects the p-electrode layers 10 of each row together. The light-exiting surface of the sapphire substrate 2 is a roughened surface 1 to increase the light-extraction rate; there is a passivation layer 12 on the surface of the p-electrode connecting metal layer 11 . The p-electrode layer of the chip uses metals such as silver or aluminum with high light reflectivity to increase light reflection.

In the present invention, the gallium source is TMGa (trimethylgallium), the nitrogen source is NH ₃ (ammonia), the indium source is TMIn (trimethyl indium), the silicon source is SiH ₄ (silane), and the magnesium source is Cp ₂ Mg ( Dichloromagnesium).

The following is the detailed manufacturing method of the controllable power blue light flip-chip array LED chip structure of this embodiment, and its flow is shown in Figure 1, which includes the following steps:

Step 1: On the sapphire substrate 2, grow a low-doped Si n-type GaN buffer layer 3 by MOCVD method, and then grow a highly-doped Si n-type GaN semiconductor layer 6; that is, use TMGa (trimethylgallium), NH ₃ (ammonia) and silicon source SiH ₄ (silane) grow a 2 μm thick low-doped Si n-GaN buffer layer 3 at 570°C; then grow a 20nm highly doped Si n-type GaN semiconductor layer 6; as Figure 2 schematically.

Step 2, growing the active layer 7 by MOCVD method. Multiple periods of InGaN layers and GaN layers are alternately grown to form multiple quantum wells—MQW layers. The specific process is as follows: first, feed indium source TMIn (trimethyl indium) to grow 3nm thick InGaN; second, remove the indium source, feed silane (SiH ₄ ) to grow 20nm thick n-GaN; third, repeat In the first and second times of the process, InGaN/GaN multiple quantum wells are grown; as shown in Figure 2

Step 3: On the top of the MQW active layer 7, grow a p-type semiconductor layer 8 by MOCVD method, that is, inject TMGa (trimethylgallium), NH ₃ (ammonia) and Cp ₂ Mg (dimagnesium) to a thickness of 100nm The p-type semiconductor layer 8;

Step 4, after cleaning, deposit a layer of ITO transparent conductive film on the p-type semiconductor layer 8 by magnetron sputtering as the transparent electrode layer 9, and deposit Ag or Al metal on the transparent electrode layer to form the p-electrode layer 10 ; The thickness of the transparent electrode layer 9 is 500nm, and the thickness of the p-electrode layer 10 is 120nm;

Step 5, on the basis of step 4, apply photoresist, mask, photolithography, etch, expose the n-type buffer layer and the isolation groove of the chip, and prepare for the deposition of n electrode layer 5; as shown in Figure 3, Fig. 4 shown;

Step 6. Deposit Cu/Au (copper/gold) by magnetron sputtering, the thickness of the deposited metal is 120nm; form the n-electrode layer 5, and perform photolithography and etching to form n-electrode layers that are connected together in each row 5; as shown in Figure 5 and Figure 6.

Step 7. Use PECVD (Plasma Enhanced Chemical Vapor Deposition) to grow the SiO ₂ insulating layer 4, and perform photolithography and etching to expose the p-electrode layer 10 window, and to further deposit the p-electrode connection metal layer above the p-electrode layer 10 window Make preparations; at the same time, expose the n-electrode pad on the edge of the chip for external circuit connection; as shown in Figure 7 and Figure 8.

Step 8. On the p-electrode layer 10, use magnetron sputtering to deposit Cu/Au (copper/gold) and other metals to connect the metal electrode layer 11 of the p-electrode, the thickness of which is 90-150 μm, and perform photolithography and etching , to form the p-electrode connection metal and the n-electrode external pad that are connected together in each row of array units; for external circuit connection; as shown in Figure 9 and Figure 10

Step 9, remove the photoresist, grow SiOx or SiNx passivation layer by PECVD, namely form SiO ₂ passivation layer 12 with a thickness of 80nm; and perform photolithography and etching to expose the p electrode pad and n electrode pad for external circuit connection;

Step 10. Thinning the sapphire substrate 2 with chemical mechanical polishing (CMP) equipment, that is, thinning the sapphire substrate from 350 μm to 450 μm to 90 μm to 150 μm, and using photolithography plus ion etching to effectively polish the light emitting surface of the sapphire. Roughening of the tissue to form a roughened surface 1 .

The LED chips manufactured according to the above steps and process can obtain better quality flip-chip array LED chips.

Based on the above example structure and its manufacturing method, adjusting the active layer structure (such as quantum wells of multiple materials to form a composite quantum well) and material components (adjusting the doping concentration to change the emission wavelength) can emit multiple colors of light, and the present invention also Covers this category of LED chips.

The above content of the present invention has only provided a kind of implementation scheme that realizes the present invention, but the chip structure and process condition in this scheme and scheme can be changed, and this change does not depart from the idea and scope of the present invention, and is helpful to those skilled in the art. All changes that are self-evident should be included within the scope of the described claims.

Claims (14)

1. A controllable power flip-chip array LED chip, characterized in that: the array LED chip is composed of a plurality of array units to form an array, wherein the p-electrode layer (10) of each row of all array units is connected, and the n-electrode layer of each column (5) Connection; the structure of each array unit is that the sapphire substrate (2) is sequentially covered with an n-type buffer layer (3), an n-type semiconductor layer (6), an active layer (7), and a p-type semiconductor layer (8), transparent electrode layer (9), p-electrode layer (10); all n-electrode layers (5) and p-electrode layers (10) are covered by an insulating layer (4); wherein each row of p-electrode layers ( 10) Connecting through the p-electrode connection metal layer (11) above the window of the p-electrode layer (10); there is also a passivation layer (12) on the surface of the p-electrode connection metal layer (11). 2. The controllable power flip-chip array LED chip according to claim 1, characterized in that the roughened surface (1) is the light-emitting surface of the LED chip formed by roughening the sapphire substrate (2). 3. The controllable power flip chip array LED chip according to claim 1, characterized in that: n-type buffer layer (3), n-type semiconductor layer (6) and p-type semiconductor layer (8) are made of GaN, GaAs or It is composed of AlGaN semiconductor material; the impurity doped in the n-type layer is Si material, and the impurity doped in the p-type layer is Mg material. 4. The controllable power flip-chip array LED chip according to claim 1, characterized in that: the active layer (7) is a single layer of InGaN, or a multi-layer InGaN layer and GaN layer, forming multiple quantum wells layer. 5. The controllable power flip-chip array LED chip according to claim 1, 2 or 3, characterized in that: the LED chip is composed of mutually independent array units to form an array, and the n electrode layer (5) of each array unit is connected to ; The material of the n-electrode layer (5) includes Cu, Ti, Al, Ni or Au metal, and a single metal or a combination of metals is used. 6. The controllable power flip-chip array LED chip according to claim 1, 2 or 3, characterized in that: the p-electrode layer (10) is made of Ag or Al, and completely covers the transparent electrode layer (9) of each array unit ). 7. The controllable power flip-chip array LED chip according to claim 1, 2 or 3, characterized in that: the material of the p-electrode connection metal layer (11) includes Cu, Ti, Al, Ni or Au metal, among which a single metal or a combination of metals. 8. The controllable power flip chip _array LED chip according to claim 1, characterized in that the insulating layer (4) and the passivation layer (9) are made of _SiOx , _SiNx or _SiOxNy insulating material. 9. The controllable power flip chip array LED chip according to claim 1, characterized in that: the transparent electrode layer (9) is made of metal film Ni/Au or indium tin oxide. 10. A method for manufacturing controllable power flip-chip array LED chips, characterized in that it comprises the following manufacturing steps: Step 1, growing a low-doped n-type buffer layer (3) on a sapphire substrate, and then growing a highly-doped n-type semiconductor layer (6); Step 2, growing the active layer (7), growing into a single layer of InGaN, or alternately growing into multiple periods of InGaN layers and GaN layers to form multiple quantum well layers; Step three, growing a p-type semiconductor layer (8) on the basis of step two; Step 4, depositing a transparent electrode layer (9) and a p-electrode layer (10); Step 5, performing photolithography and etching on the basis of step 4, exposing the n-type buffer layer (3) and the isolation groove of the chip, and preparing for the deposition of the n-electrode; Step 6, depositing a metal layer, and performing photolithography and etching to form an n-electrode layer (5) where each row is connected together; Step 7, depositing an insulating layer (4), performing photolithography and etching, exposing the window of the p-electrode layer (10), and preparing for depositing the p-electrode connection metal layer (11) above the window of the p-electrode layer (10); at the same time The n-electrode pad is exposed on the edge of the chip; Step 8, depositing metals including Cu, Ti, Al, Ni or Au metals, using a single metal or a combination of metals, and performing photolithography and etching to form a p-electrode connection metal layer ( 11) and n electrode external pad; Step 9, depositing a passivation layer (12), and performing photolithography and etching to expose the p-electrode pad and n-electrode pad; Step ten, thinning the sapphire substrate (2), and performing organized roughening treatment on the light-emitting surface of the sapphire to form a roughened surface (1). 11. The method for manufacturing controllable power flip-chip array LED chips according to claim 10, characterized in that: in the above-mentioned manufacturing steps, the deposition sequence can be exchanged from step 1 to step 3, that is, the p-type semiconductor is first grown on the substrate layer (8) and active layer (7), and finally an n-type semiconductor layer (6) is grown on top of the active layer. 12. The method for manufacturing controllable power flip-chip array LED chips according to claim 10 or 11, characterized in that: Steps 1 to 3 are prepared by "MOCVD" metal organic compound vapor phase deposition process, or "MBE" prepared by molecular beam epitaxy. 13. The method for manufacturing controllable power flip-chip array LED chips according to claim 9, characterized in that: Step 5 adopts wet etching process, adopts "ICP" enhanced plasma etching method or "RIE" reactive ion etching method , or a combination of the two methods. 14. The method for manufacturing controllable power flip-chip array LED chips according to claim 9, characterized in that: step 4, step 6 and step 7 use magnetron sputtering or electron beam evaporation to grow the transparent electrode layer (9 ), p-electrode layer (10), n-electrode (5) and p-electrode connection metal layer (11); Step 7 adopts "PECVD" plasma enhanced chemical vapor deposition to grow insulating layer (4) and passivation layer (12); In step ten, the sapphire substrate (2) is thinned by chemical mechanical polishing "CMP" equipment.

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