CN102255975A - Dual-port-random access memory (RAM)-based embedded common Ethernet/Internet protocol (IP) communication interface device - Google Patents

Abstract

An embedded general-purpose Ethernet/IP communication interface device based on dual-port RAM, including: a core board unit, used to receive, send, analyze and process data information of Ethernet/IP industrial Ethernet and external equipment, and is an indicator circuit in the bottom board unit Provide indication logic signals, solidify system information, and provide software support for the entire device; the bottom board unit is connected to the core board unit through the core board interface circuit to form a whole, and is used to communicate with the Ethernet/IP network to exchange Ethernet/IP data, and external The equipment communicates and exchanges external data, provides standard circuit interfaces for external equipment, and is used for interconnection between communication interface devices and external equipment, indicating the current working status of communication interface devices, and providing power and reset functions for communication interface devices. The invention has wide versatility, and when the external equipment meets the specification of the interface circuit in the communication interface device, the communication interface device can interconnect and exchange Ethernet/IP data information with any external equipment.

Description

Embedded Universal Ethernet/IP Communication Interface Device Based on Dual-port RAM

technical field

The invention relates to the technical field of industrial network communication, in particular to an embedded universal Ethernet/IP communication interface device with wide versatility.

Background technique

In recent years, the industrial automation control system has been developing in the direction of intelligence, informationization and networking. At present, in all network technologies, Ethernet technology based on TCP/IP protocol has become a de facto standard network, extending standard TCP/IP Ethernet to the field of industrial real-time control, and is comparable to the common industrial protocol CIP (Common Industrial Protocol1). Combined, industrial Ethernet Ethernet/IP is formed.

Since the development of Ethernet/IP is not long, and it has just started in my country, the promotion of Ethernet/IP in my country is facing various problems, such as high development costs and a serious shortage of professional technicians, etc., which restrict the development of Ethernet/IP.

The integration of traditional non-industrial Ethernet devices into industrial Ethernet not only requires embedding a huge industrial Ethernet communication protocol code into the software control system of the device, but also requires a large number of changes in the design structure of the device. The transformation technology is complex and costly, which is not conducive to Integration of industrial equipment with Industrial Ethernet.

At present, there is no embedded universal Ethernet/IP communication interface device based on dual-port RAM, so that it can be interconnected with any external device that meets the interface circuit 1027 specification.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned deficiency that prior art exists, provide a kind of embedded universal Ethernet/IP communication interface device based on dual-port RAM, make it have wide versatility, can be connected with any external equipment with standard interface circuit It is interconnected and reflects the current working condition of the communication interface device through the indicating circuit, which is convenient for the staff to monitor and troubleshoot the device.

The embedded universal Ethernet/IP communication interface device based on dual-port RAM provided by the present invention includes two parts, a core board unit and a bottom board unit, wherein,

Core board unit:

It is composed of a microprocessor, SDRAM circuit and FLASH circuit respectively bidirectionally connected with the microprocessor; the core board unit is used to receive, send, analyze and process the data information of Ethernet/IP industrial Ethernet and external equipment, and is a bottom board unit The indication circuit in the system provides indication logic signals, solidifies system information, and provides software support for the entire device;

Base unit, consisting of:

Core board interface circuit: the base board unit is connected to the core board unit through the core board interface circuit, so that the core board unit and the base board unit form a whole;

Ethernet circuit: two-way connection with the Ethernet/IP network, and two-way connection with the core board unit through the core board interface circuit, and through the Ethernet circuit, it is used for information exchange between the core board unit and the Ethernet/IP network, and exchange of Ethernet/IP network data ;

External data exchange circuit: two-way connection with the core board unit through the core board interface circuit, and two-way connection with the external device through the interface circuit, and the core board unit communicates with the external device through the external data exchange circuit to exchange external data;

Indicating circuit: connected to the core board unit through the core board interface circuit, the core board unit provides the indicating logic signal, and indicates the working status of the current communication interface device through the indicating circuit. After the display returns to normal;

Power supply circuit: connect to the core board unit through the core board interface circuit, and connect to the external equipment through the interface circuit, and provide stable power supply for the communication interface device through the power supply circuit;

Reset circuit: connect to the core board unit through the core board interface circuit, and connect external devices through the interface circuit at the same time, provide reset function for the communication interface device through the reset circuit, and reset the circuit to the reset logic of the core board unit according to the reset command signal sent by the external device signal, after the reset signal is triggered, the communication interface device will restart;

Interface circuit: Provide a standard circuit interface for external equipment through the interface circuit, so that the communication interface device can be interconnected with any external equipment that meets the interface circuit specification, plug and play, easy to install and debug.

Advantages and beneficial effects of the present invention:

It can be seen from the technical solution provided by the present invention above that, compared with the prior art, the present invention provides a dual-port RAM-based embedded Ethernet/IP general communication interface device, which can meet any interface circuit 1027 specification, that is, has 2.00mm standard spacing of 15X2 pin interface slots for external devices to interconnect and exchange Ethernet/IP network data, has a wide range of versatility, is convenient for installation and debugging, and provides working status prompts, which is convenient for maintenance personnel to monitor and troubleshoot device faults. After troubleshooting, the device automatically resumes normal operation, which is of great practical significance.

Description of drawings

Fig. 1 is the general structural diagram of a kind of embedded Ethernet/IP universal communication interface device based on dual-port RAM provided by the present invention;

Fig. 2 is the circuit diagram of the microprocessor 1011S3C2440 in the core board unit 101 of Fig. 1;

Fig. 3 is the circuit diagram of the FLASH1013 circuit in the core board unit 101 of Fig. 1;

Fig. 4 is the circuit diagram of SDRAM1012 circuit in Fig. 1 core board unit 101;

FIG. 5 is a core board interface circuit 1021 in the bottom board unit 102 of FIG. 1;

FIG. 6 is a circuit diagram of the Ethernet circuit 1022 in the backplane unit 102 of FIG. 1;

FIG. 7 is a circuit diagram of the external data exchange circuit 1023 in the bottom plate unit 102 of FIG. 1;

FIG. 8 is a circuit diagram of the indicating circuit 1024 in the base unit 102 of FIG. 1;

FIG. 9 is a circuit diagram of the power supply circuit 1025 in the base unit 102 of FIG. 1;

FIG. 10 is a circuit diagram of the reset circuit 1026 in the bottom plate unit 102 of FIG. 1;

FIG. 11 is a circuit diagram of the interface circuit 1027 in the backplane unit 102 of FIG. 1 .

In order to enable those skilled in the art to better understand the solution of the present invention, the present invention will be described below in conjunction with the accompanying drawings and embodiments.

Detailed ways

FIG. 1 is an overall structural diagram of an embedded universal Ethernet/IP communication interface device based on dual-port RAM provided by the present invention.

Referring to Fig. 1, the embedded universal Ethernet/IP communication interface device based on dual-port RAM provided by the present invention includes two parts, a core board unit 101 and a bottom board unit 102, wherein,

Core board unit 101:

Consists of a microprocessor 1011, and SDRAM circuit 1012 and FLASH circuit 1013 bidirectionally connected to the microprocessor 1011 respectively; the core board unit is used to receive, send, analyze and process data information of Ethernet/IP industrial Ethernet and external devices , to provide indication logic signals for the indication circuit in the base unit, as well as solidify system information, and provide software support for the entire device;

Base unit 102, comprising:

Core board interface circuit 1021: the bottom board unit is bidirectionally connected with the microprocessor 1011 in the core board unit 101 through the core board interface circuit, so that the core board unit 101 and the bottom board unit 102 are connected to form a whole;

Ethernet circuit 1022: two-way connection with the Ethernet/IP network, and two-way connection with the core board unit 101 through the core board interface circuit 1021. Ethernet/IP network data;

External data exchange circuit 1023: two-way connection with the core board unit through the core board interface circuit 1021, and two-way connection with the external device through the interface circuit 1027, and the core board unit 101 communicates with the external device through the external data exchange circuit 1023 to exchange external data ;

Indicating circuit 1024: connected to the core board unit through the core board interface circuit 1021, the core board unit 101 provides an indicating logic signal, and indicates the working status of the current communication interface device through the indicating circuit 1024, and when the communication module is working abnormally, the indicating circuit sends out an abnormality Display, the display returns to normal after the abnormality is restored;

Power supply circuit 1025: connect to the core board unit through the core board interface circuit 1021, and connect to external equipment through the interface circuit 1027, and provide a stable power supply for the communication interface device through the power supply circuit 1025;

Reset circuit 1026: connect to the core board unit through the core board interface circuit 1021, and connect external devices through the interface circuit 1027 at the same time, provide a reset function for the communication interface device through the reset circuit 1026, and reset the circuit 1026 according to the reset command signal sent by the external device. The microprocessor 1011 in the core board unit 101 resets the logic signal. After the reset signal is triggered, the communication interface device will restart.

Interface circuit 1027: Through the interface circuit 1027, a standard circuit interface is provided for external equipment, so that the communication interface device can be interconnected with any external equipment that meets the specifications of the interface circuit 1027, plug and play, easy to install and debug.

The specific structure of each unit circuit involved in the device of the present invention is as follows:

Core board unit 101

Microprocessor 1011, referring to Fig. 2, adopts 16/32-bit RISC embedded microprocessor S3C2440A based on ARM920T core, is used for collecting and delivering Ethernet/IP data and external device data to base unit 102, and receiving data from base unit 102 The reset signal of the reset circuit 1026 provides a logical indication signal to the indication circuit 1024 of the backplane unit 102 to reflect the working state of the current communication interface device, and initializes the software protocol stack to complete all software processing tasks of the communication interface device;

In specific implementation, the microprocessor 1011 collects the Ethernet/IP network data in the Ethernet circuit 1022 in the backplane unit 102 and the external device data in the data exchange circuit, and sends the Ethernet/IP network data to the Ethernet circuit 1022 and the data exchange circuit. data and external data; collect the reset signal from the reset circuit 1026 in the base unit 102, and the microprocessor 1011 automatically restarts after receiving the reset signal; in addition, the microprocessor 1011 constantly scans the working conditions of the communication interface device, and sends an indication logic signal to The indicator circuit 1024 of the base unit 102 reflects the working status of the current communication interface device;

It should be noted that, after the microprocessor 1011 is initially powered on, the states of all parameters need an initial value, so that the microprocessor 1011 can enter a normal working state in an initial state. When the microprocessor 1011 starts to execute, relevant parameters such as IP address of the communication interface device, I/O exchange byte size and other parameters need to be written into the microcontroller, so that the communication interface device can work normally. Therefore, all initialization parameters need to be written into the microprocessor 1011 by the external device through the external data exchange circuit of the bottom board unit 102, so as to complete the initialization.

FLASH circuit 1013, see Figure 3, bidirectionally connected to the microprocessor through the data bus and control bus, Samsung K9F2G08U0B-PCB0 is a NAND-type FLASH chip with a data storage capacity of 256M, and 2M NOR-type FLASH, which constitutes a dual FLASH startup. The microprocessor 1011 reads and writes the program information and configuration information of the communication interface device through the NAND type FLASH chip, and the stored program information will not be lost after the communication interface device is powered off;

SDRAM circuit 1012, referring to Figure 4, has a synchronous dynamic random access memory SDRAM1012 chip with a 64MB capacity of model MT48LC16M16A2P, which is bidirectionally connected to the processor through the address bus, data bus and control bus, and provides high-speed memory for the processor through the large-capacity SDRAM1012 chip. The data processing capability is used to make the running space, data and stack area of the program in the system;

base unit 102

The core board interface circuit 1021, referring to Fig. 5, includes two sets of 36X2 and two sets of 16X2 standard plug-in devices with a spacing of 2.0 mm, so that the core board unit 101 and the base board unit 102 are bidirectionally connected, and form a whole in terms of electrical and physical characteristics;

Ethernet circuit 1022, referring to the interface circuit diagram of Fig. 6 Ethernet circuit 1022, comprises: Ethernet controller DM9000 and microprocessor 1011 are bidirectionally connected by data bus LDATA0-LDATA15 and control bus, for the data from Ethernet/IP network The message is sent to the microprocessor 10111011, and the microprocessor 1011 judges and filters (i.e. parses) the message from the Ethernet/IP industrial Ethernet according to the Ethernet/IP specification, and receives the Ethernet/IP message sent by the microprocessor 1011. The IP data message is sent to the Ethernet/IP network, that is, the message conforming to the Ethernet/IP protocol is sent to the Ethernet/IP industrial Ethernet, thereby improving the communication efficiency of the communication interface device of the present invention; the TXO+ and TXO- of the Ethernet controller , RXI+, RXI- four pins and network filter H1102NL TDP, TDN, RDP, RDN four pins two-way connection exchange data, Ethernet interface circuit device RJ45 TX+, TX-, RX+, RX- four pins The four pins of TXP, TXN, RXP and RXN of the network filter H1102NL are bidirectionally connected to exchange data, providing Ethernet physical interface, 3.3V power supply and ground signal provide analog power supply and analog ground for Ethernet circuit through capacitor and inductor circuit Signal.

The external data exchange circuit 1023, referring to Fig. 7, is bidirectionally connected with the microprocessor 1011, and is used to receive the data sent by the microprocessor 1011 to the external device, and send the data from the external device to the microprocessor 1011;

引脚和双口RAM的引脚相连，只有当片选线为低电平选中它们的时候才允许元件工作。微处理器1011的8位数据线DATA[0:7]通过电平转换芯片SN74LVC4245与双口RAM的数据线I/O[0:7]L相连，微处理器1011的LnWE引脚作为写信号控制线与双口RAM的R/WL引脚和电平转换芯片的DIR引脚相连。微处理器1011的LnOE引脚作为读控制线与双口RAM的

引脚相连。微处理器1011的LADDR[0:10]与双口RAM的10位地址总线A[0:10]L相连。双口RAM的中断

L引脚和

引脚与微处理器1011的nWAIT和EINT9引脚相连。The external data exchange circuit 1023 shown in Figure 7 adopts a dual-port RAM with 8 data bits and a 5V power supply voltage to provide a data sharing space between the communication interface device and the application equipment, and the nGCS5 pin of the microprocessor 1011 is used as a shared chip selection line with level shifter chip SN74LVC4245

pins and dual-port RAM’s The pins are connected to allow the components to operate only when the chip select line is low to select them. The 8-bit data line DATA[0:7] of the microprocessor 1011 is connected to the data line I/O[0:7]L of the dual-port RAM through the level conversion chip SN74LVC4245, and the LnWE pin of the microprocessor 1011 is used as a write signal The control line is connected with the R/WL pin of the dual-port RAM and the DIR pin of the level conversion chip. The LnOE pin of the microprocessor 1011 is used as the read control line and the dual-port RAM

pins are connected. The LADDR[0:10] of the microprocessor 1011 is connected with the 10-bit address bus A[0:10]L of the dual-port RAM. Dual-port RAM interrupt

L pin and

The pin is connected with the nWAIT and EINT9 pins of the microprocessor 1011.

置低电平，当右端口读取0x7FF单元内数据的时候双口RAM自动将

电平拉高，反之亦然，利用中断机制可以方便的实现两个CPU之间的数据高速交换。双口RAM与微处理器1011的硬件接口电路如图7所示。It should be noted that the model of the dual-port RAM is IDT7132, and the chip hardware has excellent performance, which makes the design of the peripheral interface circuit 1027 very simple. In order to prevent two ports from using the same data unit at the same time, the dual-port RAM hardware provides three different address contention mechanisms, namely hardware busy mechanism, interrupt mechanism and token mechanism. The communication interface device of the present invention uses a hardware busy mechanism and an interrupt mechanism to arbitrate address competition. Hardware busy mechanism, the two ports of dual-port RAM each have a BUSY pin, when one port tries to access an address unit being accessed by the other port, the corresponding BUSY pin will be set low. The interrupt mechanism uses the address 0x7FE and 0x7FF, that is, the highest two address units of the dual-port RAM as interrupt registers. For example, when the left port writes data to the 0x7FF unit, the dual-port RAM will interrupt the right pin

Set low level, when the right port reads the data in the 0x7FF unit, the dual-port RAM will automatically

The level is pulled high, and vice versa, the high-speed data exchange between the two CPUs can be easily realized by using the interrupt mechanism. The hardware interface circuit of the dual-port RAM and the microprocessor 1011 is shown in FIG. 7 .

引脚为微处理器1011提供外部中断源，引脚为微处理器1011提供插入等待信号。The interrupt INT pin and the busy BUSY pin of the dual-port RAM are open-drain outputs, so they should be externally connected with pull-up resistors in practical applications.

pin provides an external interrupt source for the microprocessor 1011, pin provides an insertion wait signal to the microprocessor 1011.

The microprocessor 1011 has a power supply voltage of 3.3V, and there is a level mismatch when it is directly connected to the 5V level. It is necessary to use a level conversion chip to solve the problem of level mismatch between the two parties. The level conversion chip is SN74LVC4245, which has two independent power supplies of 3.3V and 5V, and a pair of symmetrical 8-bit data ports on both sides, which can realize the mutual conversion of 3.3V signals and 5V signals. The DIR pin of SN74LVC4245 controls the transmission direction of the data signal. When the DIR pin is at a high level, the signal is allowed to be transmitted from 5V to 3.3V. When the DIR pin is at a low level, the signal is allowed to be transmitted from 3.3V to 5V. When the microprocessor 1011 reads data from the data bus, the LnWE pin is automatically high, and the signal direction of the DIR pin is from the dual-port RAM to the microprocessor 1011. When the microprocessor 10111011 writes data, the LnWE is automatically low. Ping, DIR pin signal direction from the microprocessor 10111011 to the dual-port RAM, which can control the transmission of both data signals.

Referring to FIG. 8 , the indicating circuit 1024 is unidirectionally connected to the microprocessor 1011 for indicating the working state of the current communication module, and the microprocessor 1011 sends an indicating logic signal to the indicating circuit 1024 according to the working state of the current communication module.

As shown in Figure 8, the anodes of the four LEDs are connected to the power supply voltage 3.3V, and the cathodes of the four LEDs are connected to the GPG7, GPG10, GPF6, and GPF5 pins of the microprocessor 1011 through four 1K current-limiting resistors. When the pin outputs a low level, the corresponding LED is lit, and the microprocessor 1011 reflects the initialization status, device and network connection status, etc. to the indicating circuit 1024 according to the current working status of the communication interface device.

The power supply circuit 1025, as shown in Figure 9, adopts 5V power supply, including a power switch and an indicator light, and is regulated by a low-dropout linear voltage regulator AS1117AR-3.3 chip capable of carrying 1.5A. The 5V power supply voltage passes through a 2.6A fuse. Connect to the Vin input terminal of AS1117AR-3.3 after being filtered by a capacitor, the GND terminal of AS1117AR-3.3 is directly grounded, output a 3.3V stable voltage through two connected Vout pins, and the 3.3V voltage output by AS1117AR-3.3 is filtered by a capacitor Provide the 3.3V stable power required by the device and connect it to the anode of the power indicator POWERRED. The cathode of the power indicator POWERRED is grounded through a 1K resistor to provide power indication for the communication interface device.

The reset circuit 1026, referring to Fig. 10, is unidirectionally connected with the microprocessor 1011, and is used to reset the communication interface device. When the reset circuit 1026 receives a reset signal from an external device, the reset circuit 1026 sends the reset signal to the microprocessor 1011 , the microprocessor 1011 restarts after receiving the reset signal.

As shown in the reset circuit 1026 in FIG. 10 , MAX811 is a relatively simple reset chip. Pin 3 is connected to pin 27 of the interface circuit 1027 , and pin 2 is connected to the reset pin nRESET of the microprocessor 1011 . When pin 3 receives a low-level signal from an external device, pin 3 of MAX811 sends a low-level signal to the microprocessor 1011, and the reset pin of the microprocessor 1011 receives a low-level signal Then trigger the reset function.

引脚，通过控制引脚外部设备与双口RAM相互提供控制逻辑，接插器件8到18引脚为地址信号线，与双口RAM右端地址线A[0:10]R相连，由外部设备提供地址选通信号为双口RAM提供地址信号逻辑，接插器件19到26引脚为数据信号线，与双口RAM右端的数据线I/O[0:7]R相连，与外部设备交换数据信息，接插器件27引脚为复位引脚，与复位电路1026MAX811芯片的3号引脚相连，由外部设备提供复位逻辑信号驱动通信接口装置的复位电路1026，接插器件28引脚NC为空引脚，接插器件29引脚与30引脚为串行口数据引脚，与微处理器1011的TXD0与RXD0引脚相连，用以通信接口装置与PC机进行串行通信交换数据进行固件升级。The interface circuit 1027, referring to FIG. 11, is bidirectionally connected with external equipment, and is used for interconnecting the communication interface device with external equipment. As shown in Figure 11, the interface circuit 1027 adopts a standard 2.0mm pitch 15X2 pin device for data exchange between external equipment and communication interface devices. The communication interface device provides power, and the pins 3 to 7 of the plug-in device are connected to the right end of the dual-port RAM.

Pins, external devices and dual-port RAM provide mutual control logic through control pins, pins 8 to 18 of the plug-in device are address signal lines, connected to the address line A[0:10]R at the right end of the dual-port RAM, and controlled by external devices Provide address strobe signal to provide address signal logic for dual-port RAM. Pins 19 to 26 of the plug-in device are data signal lines, connected to the data line I/O[0:7]R on the right end of dual-port RAM, and exchanged with external devices Data information, the 27 pins of the plug-in device are reset pins, which are connected to the No. 3 pin of the reset circuit 1026MAX811 chip, and the reset logic signal is provided by the external device to drive the reset circuit 1026 of the communication interface device, and the 28-pin NC of the plug-in device is Empty pins, the 29 pins and 30 pins of the plug-in device are serial port data pins, which are connected with the TXD0 and RXD0 pins of the microprocessor 1011, and are used for serial communication and data exchange between the communication interface device and the PC. Firmware upgrade.

Specifically, the embedded Ethernet/IP universal communication interface device based on dual-port RAM provided by the present invention firstly initializes the software and hardware functions of the microprocessor 1011 after power-on, enters the operating system through the boot code, and starts the Ethernet/IP The protocol stack bootstrap program displays the startup status of the current communication interface device through the indicator circuit 1024 .

Then the microprocessor 1011 reads the initialization information into the Ethernet/IP protocol stack bootloader by collecting the external device initialization information of the data exchange circuit 1022, in order to configure parameters such as IP address, input and output I/O data byte size, and complete the initialization Function, through the indicator circuit 1024 to display the current initialization status. When the initialization is finished, the Ethernet/IP protocol stack boot program will start the main program of the Ethernet/IP protocol stack to start processing Ethernet/IP packets, analyze and process data information from the Ethernet/IP network and external devices, according to the Ethernet/IP protocol specification, Automatically unpack the data message from the Ethernet/IP network, and automatically package the data message to be sent to the Ethernet/IP network, and display the communication status of the current communication interface device, external equipment and the Ethernet/IP network through the indicating circuit 1024.

In the above process of the present invention, the microprocessor 1011 first initializes its own software and hardware, utilizes the startup code to guide the operation of the operating system, and initializes the Ethernet/IP object model, communication parameters, setting scan cycle and peripheral Ethernet circuit 1022, data according to the initialization information. Exchange circuits, etc., thereby completing the initialization process of the communication interface device. Then carry out Ethernet/IP configuration and configuration. After configuring and configuring through the Ethernet/IP network, the communication interface device is connected to the Ethernet/IP network, and then the communication interface device enters an infinite data cycle exchange state.

For the above-mentioned device provided by the present invention, when the communication interface device is working abnormally, the abnormal state will be displayed immediately through the indicating circuit 1024, so that the user can judge the cause of the failure in time and effectively troubleshoot the problems in the communication process. Combined with the circuit shown in Figure 10, an abnormal prompt can be issued when a fault occurs, prompting the user to eliminate the fault as soon as possible. In addition, when the fault is eliminated, the communication interface device automatically returns to the normal working state immediately. The indicating circuit 1024 of the present invention has fast response speed, simple circuit, low cost and high working efficiency.

For the device provided by the present invention, in the design of communication with external equipment, dual-port RAM is adopted as the shared memory of external equipment and communication interface device microprocessor 1011, the design is simple, the real-time performance of data exchange is high, and standard plug-in devices are used As the interface circuit 1027, it has wide versatility. The communication module can be interconnected with any external device that conforms to the specification of the communication module interface circuit 1027, which greatly enhances the practicability of the communication module. It is plug and play, and the device utilization rate is high. Fast access of external devices to Ethernet/IP network. In the data exchange circuit design, a level conversion chip is used as an isolation element between the dual-port RAM and the microprocessor 1011 to solve the problem of level mismatch, so that the microprocessor 1011 will not cause hardware damage due to level mismatch. , the method is simple and efficient, and has a good level conversion effect.

In summary, compared with the prior art, the present invention provides a dual-port RAM-based embedded universal Ethernet/IP communication interface device, which has wide versatility and can be used with any interface circuit that meets the 1027 specification, namely The 15X2 pin interface slots with a standard spacing of 2.00mm are interconnected with external devices, plug and play, easy to install and debug, and reflect the working status of the current communication interface device in a timely manner through the indicator circuit 1024, which is convenient for maintenance personnel to monitor and troubleshoot the device , when the fault is eliminated, the device automatically resumes normal operation, which has great practical significance.

The above is only a preferred embodiment of the present invention, it should be pointed out that, for those of ordinary skill in the art, without departing from the principle of the present invention, some improvements and modifications can also be made, and these improvements and modifications can also be made. It should be regarded as the protection scope of the present invention.

Claims (9)

1. a kind of embedded universal Ethernet/IP communication interface device based on dual-port RAM, it is characterized in that this device comprises two parts of core board unit and base board unit, wherein, Core board unit: It is composed of a microprocessor, SDRAM circuit and FLASH circuit respectively bidirectionally connected with the microprocessor; the core board unit is used to receive, send, analyze and process the data information of Ethernet/IP industrial Ethernet and external equipment, and is a bottom board unit The indication circuit in the system provides indication logic signals, solidifies system information, and provides software support for the entire device; Base unit, consisting of: Core board interface circuit: the base board unit is connected to the core board unit through the core board interface circuit, so that the core board unit and the base board unit form a whole; Ethernet circuit: two-way connection with the Ethernet/IP network, and two-way connection with the core board unit through the core board interface circuit, and through the Ethernet circuit, it is used for information exchange between the core board unit and the Ethernet/IP network, and exchange of Ethernet/IP network data ; External data exchange circuit: two-way connection with the core board unit through the core board interface circuit, and two-way connection with the external device through the interface circuit, and the core board unit communicates with the external device through the external data exchange circuit to exchange external data; Indicating circuit: connected to the core board unit through the core board interface circuit, the core board unit provides the indicating logic signal, and indicates the working status of the current communication interface device through the indicating circuit. After the display returns to normal; Power supply circuit: connect to the core board unit through the core board interface circuit, and connect to the external equipment through the interface circuit, and provide stable power supply for the communication interface device through the power supply circuit; Reset circuit: connect to the core board unit through the core board interface circuit, and connect external devices through the interface circuit at the same time, provide reset function for the communication interface device through the reset circuit, and reset the circuit to the reset logic of the core board unit according to the reset command signal sent by the external device signal, after the reset signal is triggered, the communication interface device will restart; Interface circuit: Provide a standard circuit interface for external equipment through the interface circuit, so that the communication interface device can be interconnected with any external equipment that meets the interface circuit specification, plug and play, easy to install and debug. 2. The apparatus of claim 1, wherein The microprocessor in the core board unit is used to collect Ethernet/IP input data from the Ethernet circuit and send output Ethernet/IP data, collect external device data from the external data exchange circuit and send output data, Receive the reset signal provided by the reset circuit to complete the reset function, provide a logic indicator signal to the indicator circuit to reflect the current working status of the communication interface device, initialize and execute the software protocol stack to complete all the software processing tasks of the communication interface device; Described FLASH circuit adopts FLASH chip to constitute, is the program memory of communication interface device, stores the system information during programming, guarantees that the program information is not lost after system adjustment, and microprocessor reads and writes the program information of communication interface device through FLASH chip and configuration information; The SDRAM circuit is composed of an SDRAM chip, which is a synchronous dynamic random access memory, which ensures that data is not lost by continuously refreshing the storage array, and provides program running space and high-speed data processing capability for the communication interface device; 3. The device according to claim 1 or 2, characterized in that the core board interface circuit includes two sets of 36X2 and two sets of 16X2 standard plug-in devices with a spacing of 2.0mm, so that the core board unit and the base board unit are bidirectionally connected , electrical characteristics and physical characteristics constitute a whole. 4. The device as claimed in claim 1 or 2, characterized in that said Ethernet circuit comprises: Ethernet network controller DM9000, through the data port LDATA0-LDATA15 of the microprocessor in the core board interface circuit and the core board unit Two-way connection, the TXO+, TXO-, RXI+, RXI- four pins of DM9000 are connected to the TDP, TDN, RDP, RDN pins of the network filter H1102NL in two directions, which is used as a bridge for the microprocessor to exchange data with the Ethernet network, The TX+, TX-, RX+, RX- four pins of the Ethernet interface device RJ45 are bidirectionally connected with the four pins TXP, TXN, RXP, RXN of the network filter, providing an interface circuit for the communication interface device to access the Ethernet, The 3.3V power supply and ground signal provide analog power supply and analog ground signal for the Ethernet circuit through the capacitor and inductance circuit. 5. The device as claimed in claim 1 or 2, characterized in that said external data exchange circuit comprises: a dual-port RAM chip and a slice level conversion chip SN74LVC4245, the dual-port RAM chip model is IDT7132, a dual-port RAM The chip is equipped with two sets of independent addresses, data and control lines, allowing two independent CPUs or controllers to simultaneously access the memory chip randomly, as a shared data memory between the microprocessor and external devices, to exchange microprocessors The data information between the device and the external device, and the address contention arbitration logic is provided by the dual-port RAM hardware, so as to avoid the data error problem caused by the reading and writing of the data of the same address unit of the dual-port RAM; the dual-port RAM chip The left address bus and the left control bus are unidirectionally connected to the microprocessor, and the microprocessor provides address and logic control signals. In order to avoid the situation of level mismatch, the left data bus of the dual-port RAM chip and the level conversion chip SN74LVC4245 The B-side data bus is bidirectionally connected, and the A-side data bus of the level conversion chip SN74LVC4245 is bidirectionally connected to the data bus of the microprocessor, which is used to exchange data between the dual-port RAM chip and the microprocessor. The nGCS5 of the microprocessor and the LnWE pin The pins are respectively connected with the chip select pins of the level conversion chip SN74LVC4245

It is connected to the direction pin DIR to control the working logic of the level conversion chip. The address bus, data bus and control bus at the right end of the dual-port RAM are connected to external devices through the interface circuit, and the external devices provide address, data and logic control signals . 6. The device as claimed in claim 1 or 2, characterized in that said indicating circuit comprises: 4 LED lamps connected in parallel, and each branch LED lamp communicates with the core board unit through a current-limiting resistor and a core board interface circuit. The microprocessor is one-way connected, and the microprocessor provides logic signals to reflect the current working conditions of the communication interface device. When the communication interface device is working abnormally, the LED light will display abnormally. After the fault is eliminated, the LED light will return to normal display. 7. The device according to claim 1 or 2, characterized in that the power supply circuit includes: using 5V power supply, the voltage is stabilized by a low-dropout linear voltage regulator AS1117AR-3.3 chip capable of carrying 1.5A, The 5V power supply voltage is connected to the Vin input terminal of AS1117AR-3.3 after passing through a 2.6A fuse and filtered by a capacitor. The GND terminal of AS1117AR-3.3 is directly grounded, and a 3.3V stable voltage is output through two connected Vout pins. AS1117AR-3.3 outputs After the 3.3V voltage is filtered by the capacitor, the 3.3V stable power supply required by the device is provided and connected to the anode of the power indicator POWERRED. The cathode of the power indicator POWERRED is grounded through a 1K resistor to provide power indication for the communication interface device. 8. The device as claimed in claim 1 or 2, wherein the reset circuit comprises: a reset chip MAX811, the input end of the reset chip MAX811 is connected to the interface circuit unit, and the reset logic signal is provided by an external device, and the reset chip MAX811 The output end is connected to the reset pin nRESET pin of the microprocessor in the core board unit through the core board interface circuit, and provides reset capability for the microprocessor when an external device triggers a reset logic signal. 9. The device according to claim 5, characterized in that the interface circuit comprises: a standard 2.0mm pitch 15X2-pin device for exchanging data between external equipment and the communication interface device, the 1 pin of the plug-in device and the 2 Pins are power supply pins, external equipment provides power for communication interface devices, pins 3 to 7 of the plug-in device are control pins, external devices provide control logic to each other through control pins and communication interface devices, and plug-in devices 8 to 18 The pins are address signal lines, and the external device provides the address signal of the address bus at the right end of the dual-port RAM. The pin is a reset pin, and the external device provides a reset logic signal to drive the reset circuit of the communication interface device. The 28 pins of the plug-in device are empty pins, and the 29 and 30 pins of the plug-in device are serial port data pins. The interface circuit of the core board is connected with the serial port pin of the microprocessor in the core board unit, and is used for the serial communication exchange data between the communication interface device and the PC for firmware upgrade.

Images