CN102280428A - Packaging piece and manufacture method thereof - Google Patents

Abstract

The invention provides a package and a manufacturing method thereof. The package includes: a substrate; a wiring pattern formed on the substrate; a plurality of semiconductor chips stacked on an upper surface of the substrate and electrically connected to the wiring pattern; an encapsulation material layer formed on the upper surface of the substrate to Encapsulating the plurality of semiconductor chips, wherein the substrate includes at least one body portion and at least one stepped portion, at least a portion of at least one semiconductor chip of the plurality of semiconductor chips is disposed on the at least one stepped portion and Electrically connected to at least a portion of the wiring pattern disposed on the at least one stepped portion. Because the semiconductor material is used to form a substrate for mounting chips to replace the printed circuit board in the prior art, the manufacturing process of the package is simplified, the manufacturing cost of the package is reduced, and the electrical performance of the package is improved. And it is possible to implement a stacked chip package at the wafer level.

Description

Package and manufacturing method thereof

technical field

The present invention relates to the field of semiconductor packaging, and more specifically, to a packaging component and a manufacturing method thereof.

Background technique

With the continuous development of semiconductor technology, the demand for multifunctional semiconductor chip packages is increasing. Considering the need for device miniaturization, it is necessary to arrange a plurality of semiconductor chips respectively performing different functions in a single package, so as to reduce the number and occupied space of required packages. Therefore, stacked chip packages have been developed. In a stacked chip package, for example, a plurality of semiconductor chips arranged on top of each other are mounted on a printed circuit board (PCB) as a substrate by processes such as wire bonding or flip chip, and are The connectors on the surface of the (PCB) opposite to the surface on which the semiconductor chip is mounted electrically connect the semiconductor chip to the outside.

As described above, in the related art, it is necessary to use a printed circuit board (PCB) having a predetermined pattern in the process of manufacturing the stacked die package. Therefore, the manufacturing process is relatively complicated, and it is difficult to reduce the manufacturing cost of the stacked chip package, and the metal connection leads in the manufactured stacked chip package are relatively long, and the signal integrity is poor. In addition, it is difficult to reduce the size and space occupied by the stacked die package due to the limited size of the printed circuit board (PCB). Therefore, the existing stacked chip package and its manufacturing method cannot meet the ever-increasing demand for product diversification and the development trend of high speed, low cost, small size, and excellent electrical performance.

Contents of the invention

It is an object of exemplary embodiments of the present invention to overcome the above and other disadvantages in the prior art. To this end, exemplary embodiments of the present invention provide a package and a manufacturing method thereof, in which a semiconductor material is used to form a substrate for mounting a chip instead of a printed circuit board (PCB) in the prior art, thereby The manufacturing process of the package is simplified, the manufacturing cost of the package is reduced, the electrical performance of the package is improved, and the stacked chip package can be realized at the wafer level.

Exemplary embodiments of the present invention also provide a package and a method of manufacturing the same, in which at least a part of a wiring pattern formed on a substrate is exposed to the outside of the package, and at least a part of the wiring pattern is exposed. The connector is provided, thereby simplifying the structure of the package, reducing the manufacturing cost of the package, and improving the electrical performance of the package.

Exemplary embodiments of the present invention also provide a package and a manufacturing method thereof, wherein another wiring pattern electrically connected to at least a portion of the wiring pattern exposed is provided on the encapsulation material layer, and The connecting parts are arranged on the pattern, so as to increase the installation space of the connecting parts (for example, solder balls), and simplify the manufacturing process (for example, reduce the difficulty of the ball planting process).

According to an exemplary embodiment of the present invention, a package includes: a substrate; a wiring pattern formed on the substrate; a plurality of semiconductor chips stacked on an upper surface of the substrate and electrically connected to the wiring pattern; an encapsulation material layer, formed on an upper surface of a substrate to encapsulate the plurality of semiconductor chips, wherein the substrate includes at least one body portion and at least one stepped portion, at least a portion of at least one of the plurality of semiconductor chips is disposed on The at least one stepped portion is on and electrically connected to at least a portion of the wiring pattern disposed on the at least one stepped portion.

The substrate is formed of semiconductor material.

The at least one body portion and the at least one stepped portion are integrally formed through an etching process.

A wiring pattern is formed on the substrate through a plating process.

The plurality of semiconductor chips are stack-mounted on the upper surface of the substrate in a flip-chip manner and are electrically connected to the wiring patterns.

The package also includes a via hole formed in the substrate and electrically connected to the wiring pattern.

The package further includes: a connector provided on the lower surface of the substrate, the connector being electrically connected to the wiring pattern by the via hole, thereby electrically connecting the plurality of semiconductor chips to the outside.

At least another part of the wiring pattern is exposed to the outside of the package.

The package further includes: a connection member disposed on the at least another exposed portion of the wiring pattern, the connection member being electrically connected to the at least another exposed portion of the wiring pattern to electrically connect the plurality of semiconductor chips to the outside.

At least another semiconductor chip of the plurality of semiconductor chips is disposed on the at least one main body portion and is electrically connected to at least a further part of the wiring pattern disposed on the at least one main body portion, including a portion disposed on the at least one main body portion. At least another part of at least a part of the at least one semiconductor chip on the stepped portion is stacked on the at least another semiconductor chip.

According to another exemplary embodiment of the present invention, a method of manufacturing a package includes the steps of: forming a substrate, wherein the substrate includes at least one body portion and at least one stepped portion; forming a wiring pattern on the substrate; semiconductor chips are stacked on the upper surface of the substrate and electrically connected to the wiring pattern, wherein at least a part of at least one semiconductor chip of the plurality of semiconductor chips is disposed on the at least one stepped portion and electrically connected to the wiring pattern at least a part of which is disposed on the at least one stepped portion; forming an encapsulation material layer on the upper surface of the substrate to encapsulate the plurality of semiconductor chips.

The substrate is formed of semiconductor material.

In the forming of the substrate, the at least one body portion and the at least one stepped portion are integrally formed through an etching process.

Wiring patterns are formed on the substrate through a plating process.

The plurality of semiconductor chips are flip-chip mounted on the upper surface of the substrate and electrically connected to the wiring patterns.

The method further includes forming a via hole electrically connected to the wiring pattern in the substrate.

The method further includes providing a connection on a lower surface of the substrate such that the connection is electrically connected to the wiring pattern by a via hole, thereby electrically connecting the plurality of semiconductor chips to the outside.

In the step of forming the encapsulation material layer, at least another part of the wiring pattern is exposed to the outside of the package.

The method further includes forming a connection on the at least another exposed portion of the wiring pattern such that the connection is electrically connected to the at least another exposed portion of the wiring pattern to electrically connect the plurality of semiconductor chips to external.

In the step of stacking the plurality of semiconductor chips, at least another semiconductor chip of the plurality of semiconductor chips is disposed on the at least one main body portion and is electrically connected to the wiring pattern disposed on the at least one main body portion. and stacking at least another portion of the at least one semiconductor chip including at least a portion disposed on the at least one stepped portion on the at least another semiconductor chip.

Description of drawings

1 is a cross-sectional view illustrating a package according to an exemplary embodiment of the present invention;

2 is a cross-sectional view illustrating a package according to another exemplary embodiment of the present invention;

3A to 3F are cross-sectional views illustrating a method of manufacturing a package according to an exemplary embodiment of the present invention;

4A to 4G are cross-sectional views illustrating a method of manufacturing a package according to an exemplary embodiment of the present invention.

Detailed ways

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art. The size and relative sizes of layers and regions may be exaggerated in the drawings for clarity. Also, in the drawings, the same or similar reference numerals may denote the same or similar elements.

FIG. 1 is a cross-sectional view illustrating a package 10 according to an exemplary embodiment of the present invention.

As shown in FIG. 1 , a package 10 according to an exemplary embodiment of the present invention may include a substrate 11 , a wiring pattern 12 , a semiconductor chip 13 and an encapsulation material layer 14 .

The substrate 11 may be formed of a semiconductor material, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the substrate 11 may be formed of other semiconductor materials, insulating materials and/or conductive materials as required. For example, if the substrate 11 is formed of a conductive material such as metal, a dielectric layer may be formed on the entire surface or a part of the surface of the substrate 11 formed of the metal as needed to provide good insulating properties.

The substrate 11 may include at least one body portion 11a and at least one stepped portion 11b, 11c. Although it is only shown in FIG. 1 that the substrate 11 includes one body portion 11a and two stepped portions 11b, 11c, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the substrate 11 including a plurality of main body parts and one or more than two stepped parts may be formed as required.

As shown in Fig. 1, at least one body portion 11a and at least one stepped portion 11b, 11c may have different heights. For example, the body portion 11a may have the smallest height, the stepped portion 11c may have the largest height, and the stepped portion 11b may have a height greater than that of the body portion 11a and smaller than that of the stepped portion 11c. In this way, step shapes having different heights can be formed on the upper surface of the substrate 11 . In at least one other exemplary embodiment of the present invention, a height difference between two adjacent parts of the at least one body part and the at least one stepped part is determined according to the thickness of the semiconductor chip to be mounted.

For example, when the substrate 11 is formed of a semiconductor material, at least one body portion 11a and at least one stepped portion 11b, 11c may be integrally formed through an etching process, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, at least one body portion 11a and at least one stepped portion 11b, 11c may be formed by other processes. For example, when the substrate 11 is formed of a conductive material such as metal, at least one body portion 11a and at least one stepped portion 11b, 11c may be formed by a process such as punching; when the substrate 11 is formed of an insulating material such as resin, it may be formed by A process such as injection molding is used to form the substrate 11 comprising at least one body portion 11a and at least one stepped portion 11b, 11c.

The wiring pattern 12 may be formed on the substrate 11 (eg, an upper surface and/or a lower surface of the substrate 11 ). For example, the wiring pattern 12 may be formed on at least one body portion 11 a and at least one stepped portion 11 b, 11 c of the substrate 11 . As shown in FIG. 1 , the wiring pattern 12 may include at least one portion 12a formed on at least one body portion 11a and at least one portion 12b, 12c formed on at least one stepped portion 11b, 11c. The wiring pattern 12 may be formed on the substrate 11 by various processes from a conductive material such as metal. For example, the wiring pattern 12 may be formed of a conductive material such as metal through a deposition process and/or a plating process, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, other conductive materials and/or other processes may be used to form the wiring pattern 12 as required. For example, when the substrate 11 is formed of a semiconductor material, the wiring pattern 12 may be formed such as by a doping process. In at least one other exemplary embodiment of the present invention, when the substrate 11 is formed of a conductive material such as metal, the wiring pattern 12 may be formed on a dielectric layer formed on the substrate 11 as described above.

A plurality of semiconductor chips 13 may be stacked and attached on the substrate 11 (eg, stacked and attached on the upper surface of the substrate 11 ), and electrically connected to the wiring patterns 12 , respectively. For example, a plurality of semiconductor chips 13 may be stacked on at least one body portion 11 a and at least one stepped portion 11 b of the substrate 11 . As shown in FIG. 1, the plurality of semiconductor patterns 13 may include: at least one semiconductor chip 13a disposed on at least one body portion 11a and electrically connected to at least a portion 12a of the wiring pattern 12 disposed on at least one body portion 11a; At least one semiconductor chip 13b, 13c, wherein at least a part of the semiconductor chip 13b may be disposed on the at least one stepped portion 11b and electrically connected to at least a portion 12b of the wiring pattern 12 disposed on the at least one stepped portion 11b, the semiconductor chip At least a portion of 13c may be disposed on at least one stepped portion 11c and electrically connected to at least a portion 12c of the wiring pattern 12 disposed on at least one stepped portion 11c. Furthermore, at least another part of the semiconductor chip 13b may be stacked on the semiconductor chip 13a, and at least another part of the semiconductor chip 13c may be stacked on the semiconductor chip 13b. Although only one semiconductor chip 13a disposed on at least one body portion 11a and two semiconductor chips 13b and 13c stacked on the semiconductor chip 13a are shown in FIG. 1 , exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the package 10 may include a plurality of semiconductor chips 13a disposed on at least one main body portion 11a and one or more than two semiconductor chips stacked in the plurality of semiconductor chips 13a. A semiconductor chip on at least one semiconductor chip 13a, wherein at least one of the one or more than two semiconductor chips stacked on the semiconductor chip 13a may include a semiconductor chip disposed on at least one stepped portion and electrically connected to At least a portion of at least a portion of the wiring pattern 12 disposed on at least one stepped portion.

As shown in FIG. 1 , a plurality of semiconductor chips 13 may be stack-mounted on the substrate 11 in a flip-chip manner and electrically connected to the wiring pattern 12 , however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, a plurality of semiconductor chips 13 may be stacked and mounted by various mounting methods such as wire bonding as required.

An encapsulation material layer 14 may be formed on the substrate 11 (eg, the upper surface of the substrate 11 ) to encapsulate the plurality of semiconductor chips 13 . The encapsulation material layer 14 may be formed from an encapsulation material such as epoxy resin through an injection molding process.

According to an exemplary embodiment of the present invention, the package 10 may further include a through hole 15 . Via holes 15 may be formed in the substrate 11 and electrically connected to the wiring pattern 12 . In such a case, the via 15 may be a conductive via. For example, vias may be formed in the substrate 11 such as by an etching process and plated or filled with a conductive material in the vias to form the conductive vias 15 .

As shown in FIG. 1 , package 10 may also include connectors 16 . The connector 16 may be disposed on the lower surface of the substrate 11 . For example, the connector 16 may be provided on the wiring pattern 12 formed on the lower surface of the substrate 11, and/or the connector 16 may be provided corresponding to (eg, on or around) the through hole 16 . The connector 16 may be electrically connected to the wiring pattern 12 by the via hole 15, thereby electrically connecting at least one semiconductor chip among the plurality of semiconductor chips 13 to the outside (eg, a printed circuit board (PCB)). The connectors 16 may be solder balls, as shown in FIG. 1 . In such a case, the package 10 may also include pads for disposing the solder balls 16 . Pads may be formed on or around the wiring patterns 12 and/or the via holes 16 on the lower surface of the substrate 11 , however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the connecting member 16 may be configured as a connecting bump, a pin, etc. as required.

In the package 10 according to the exemplary embodiment of the present invention described with reference to FIG. 1 , a semiconductor material may be used to form a substrate for mounting chips instead of a printed circuit board (PCB) in the related art. A process such as plating a conductive material or doping may be used to form a wiring pattern on a substrate formed of a semiconductor material, and a method such as etching may be used to form a through hole for electrical connection in the substrate. Therefore, the manufacturing process of the package is simplified, the manufacturing cost of the package is reduced, the electrical performance of the package is improved, and the stacked chip package can be realized at the wafer level.

2 is a cross-sectional view illustrating a package 20 according to an exemplary embodiment of the present invention, and for the sake of brevity, like reference numerals are used to designate elements identical or similar to those in FIG. 1 and their detailed descriptions will be omitted.

As shown in FIG. 2 , a package 20 according to an exemplary embodiment of the present invention may include a substrate 21 , a wiring pattern 22 , a semiconductor chip 23 and an encapsulation material layer 24 .

The substrate 21 may be formed of a semiconductor material, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the substrate 21 may be formed of other semiconductor materials, insulating materials and/or conductive materials as required. For example, if the substrate 21 is formed of a conductive material such as metal, a dielectric layer may be formed on the entire surface or a part of the surface of the substrate 21 formed of the metal as needed to provide good insulating properties.

The base plate 21 may include at least one body portion 21a and at least one stepped portion 21b, 21c. Although it is only shown in FIG. 2 that the substrate 21 includes one body portion 21a and two stepped portions 21b, 21c, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the substrate 21 including a plurality of main body parts and one or more than two stepped parts may be formed as required.

As shown in Fig. 2, at least one body portion 21a and at least one stepped portion 21b, 21c may have different heights. For example, the body portion 21a may have the smallest height, the stepped portion 11c may have the largest height, and the stepped portion 21b may have a height greater than that of the body portion 21a and smaller than that of the stepped portion 21c. In this manner, step shapes having different heights can be formed on the upper surface of the substrate 21 . In at least one other exemplary embodiment of the present invention, a height difference between two adjacent parts of the at least one body part and the at least one stepped part is determined according to the thickness of the semiconductor chip to be mounted.

For example, when the substrate 21 is formed of a semiconductor material, at least one body portion 21a and at least one stepped portion 21b, 21c may be integrally formed through an etching process, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, at least one body portion 21a and at least one stepped portion 21b, 21c may be formed by other processes. For example, when the substrate 21 is formed of a conductive material such as metal, at least one body portion 21a and at least one stepped portion 21b, 21c may be formed by a process such as punching; when the substrate 21 is formed of an insulating material such as resin, it may be formed by The base plate 21 comprising at least one body portion 21a and at least one stepped portion 21b, 21c is formed by a process such as injection molding.

The wiring pattern 22 may be formed on the substrate 21 (eg, an upper surface and/or a lower surface of the substrate 21 ). For example, the wiring pattern 22 may be formed on at least one body portion 21 a and at least one stepped portion 21 b, 21 c of the substrate 21 . As shown in FIG. 2 , the wiring pattern 22 may include at least one portion 22a formed on at least one body portion 21a and at least one portion 22b, 22c formed on at least one stepped portion 21b, 21c. The wiring pattern 22 may be formed on the substrate 21 by various processes from a conductive material such as metal. For example, the wiring pattern 22 may be formed of a conductive material such as metal through a deposition process and/or a plating process, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, other conductive materials and/or other processes may be used to form the wiring pattern 22 as required. For example, when the substrate 21 is formed of a semiconductor material, the wiring pattern 22 may be formed such as by a doping process. In at least one other exemplary embodiment of the present invention, when the substrate 21 is formed of a conductive material such as metal, the wiring pattern 22 may be formed on a dielectric layer formed on the substrate 21 as described above.

A plurality of semiconductor chips 23 may be stacked and attached on the substrate 21 (eg, stacked and attached on the upper surface of the substrate 21 ), and electrically connected to the wiring patterns 22 , respectively. For example, a plurality of semiconductor chips 23 may be stacked on at least one body portion 21 a and at least one stepped portion 21 b of the substrate 21 . As shown in FIG. 2, the plurality of semiconductor patterns 23 may include: at least one semiconductor chip 13a disposed on at least one body portion 21a and electrically connected to at least a portion 12a of the wiring pattern 22 disposed on at least one body portion 21a; At least one semiconductor chip 13b, at least a portion of which may be disposed on the at least one stepped portion 21b and electrically connected to at least a portion 22b of the wiring pattern 22 disposed on the at least one stepped portion 21b. Furthermore, at least another part of the at least one semiconductor chip 23b may be arranged stacked on the semiconductor chip 23a. Although only one semiconductor chip 23a disposed on at least one body portion 21a and one semiconductor chip 23b stacked on the semiconductor chip 23a are shown in FIG. 1, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the package 20 may include a plurality of semiconductor chips 23a disposed on at least one body portion 21a and a plurality of at least one semiconductor chip stacked in the plurality of semiconductor chips 23a. A semiconductor chip on the chip 23a, wherein at least one semiconductor chip among the plurality of semiconductor chips stacked on the semiconductor chip 23a may include at least one At least a portion of at least a portion 22b on the stepped portion 21b.

As shown in FIG. 2 , a plurality of semiconductor chips 23 may be stack-mounted on the substrate 21 in a flip-chip manner and electrically connected to the wiring pattern 22 , however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, a plurality of semiconductor chips 23 may be stacked and mounted by various mounting methods such as wire bonding as required.

An encapsulation material layer 24 may be formed on the substrate 21 (eg, the upper surface of the substrate 21 ) to encapsulate the plurality of semiconductor chips 23 . The encapsulation material layer 24 may be formed from an encapsulation material such as epoxy resin through an injection molding process.

According to an exemplary embodiment of the present invention, at least a portion 22c of the wiring pattern 22 may be exposed to the outside of the package 20 . 2 shows that at least a portion 22c of the wiring pattern 22 formed on the stepped portion 21c having the largest height of the substrate 21 is exposed to the outside of the package 20, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, at least a part of the wiring pattern 22 formed on other parts of the substrate 21 may be exposed as required, for example, at least one portion of the wiring pattern 22 formed on the substrate 21 may be exposed. At least a portion of the body portion 21a. In this case, the encapsulation material layer 24 may be selectively formed on the substrate 21 through injection molding or the like to encapsulate the plurality of semiconductor chips 23 and expose at least a portion of the wiring pattern 22 .

As shown in FIG. 2 , package 20 may also include connectors 26 . The connection member 26 may be provided on the exposed at least a portion 22c of the wiring pattern 22 and electrically connected to the exposed at least a portion 22c of the wiring pattern 22 to electrically connect at least one of the plurality of semiconductor chips 23 to the outside ( For example, a printed circuit board (PCB). Connectors 26 may be solder balls, as shown in FIG. 2 . In this case, the package 20 may further include a pad for disposing the solder ball 26 formed on the exposed at least a portion 22c of the wiring pattern 22, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the connecting member 26 can be configured as a connecting bump, a pin, etc. as required.

According to an exemplary embodiment of the present invention, the package 20 may further include another wiring pattern 27 formed on the upper surface of the encapsulation material layer 24 . Like the wiring pattern 22 , the wiring pattern 27 may be formed of a conductive material such as metal on the encapsulation material layer 24 through various processes. For example, the wiring pattern 22 may be formed of metal through a deposition and/or plating process, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, other conductive materials and/or other processes may be used to form the wiring pattern 27 as required. Although not shown in the drawing, the wiring pattern 27 may be electrically connected to at least one chip 23 of the plurality of chips 23 , such as by being electrically connected to the exposed at least a portion 22 c of the wiring pattern 22 .

In the case that the package 20 includes a wiring pattern 27 formed on the upper surface of the encapsulation material layer 24 (that is, the upper surface of the package 20), the connector 26 may also be provided on the wiring pattern 27 so that multiple At least one of the semiconductor chips 23 is electrically connected to the outside (for example, a printed circuit board (PCB)). As described above, when the connection member 26 is a solder ball, the package 20 may include a pad for disposing the solder ball 26 formed on the wiring pattern 27 .

Although not shown, according to an exemplary embodiment of the present invention, the package 20 may further include through holes (not shown) as in the exemplary implementation of the present invention shown above with reference to FIG. 1 . Like the via hole 15 described above, a via hole according to an exemplary embodiment of the present invention may be formed in the substrate 21 and electrically connected to the wiring pattern 22 . In such cases, the vias may be conductive vias. For example, vias may be formed in the substrate 21 such as by an etching process and plated or filled with a conductive material in the vias to form conductive vias.

In case the package 20 further includes a through hole formed in the substrate 21 , the package 20 may also include a connector (not shown) provided on the lower surface of the substrate 21 . For example, the connectors may be provided on the wiring pattern 22 formed on the lower surface of the substrate 21, and/or the connectors may be provided corresponding to (eg, on or around) the through holes. The connector 26 may be electrically connected to the wiring pattern 22 by a via hole, thereby electrically connecting at least one semiconductor chip among the plurality of semiconductor chips 23 to the outside (eg, a printed circuit board (PCB)). As mentioned above, when the connector 26 is a solder ball, the package 20 may also include a pad for setting the solder ball 26 on or around the wiring pattern 22 and/or the through hole formed on the lower surface of the substrate 21, However, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the connecting member can be configured as a connecting bump, a pin, etc. as required.

That is, according to exemplary embodiments of the present invention, a part of the wiring pattern may be exposed to the outside of the package and/or the through hole formed in the substrate as needed. In such cases, connectors 26 may be provided on the lower surface of the package (ie, the lower surface of the substrate) and/or the upper surface of the package (ie, the upper surface of the encapsulation material layer).

In the package 20 according to the exemplary embodiment of the present invention described with reference to FIG. 2 , a semiconductor material may be used to form a substrate for mounting chips instead of a printed circuit board (PCB) in the related art. A process such as plating a conductive material or doping may be used to form a wiring pattern on a substrate formed of a semiconductor material. Therefore, the manufacturing process of the package is simplified, the manufacturing cost of the package is reduced, the electrical performance of the package is improved, and the stacked chip package can be realized at the wafer level.

In the package 20 according to the exemplary embodiment of the present invention described with reference to FIG. Connectors are arranged on the package, thereby simplifying the structure of the package, reducing the manufacturing cost of the package, and improving the electrical performance of the package.

In the package 20 according to the exemplary embodiment of the present invention described with reference to FIG. 2 , another wiring pattern electrically connected to at least a part of the exposed wiring pattern may be provided on the encapsulation material layer, and the other wiring pattern The connecting parts are arranged on the pattern, so as to increase the installation space of the connecting parts (for example, solder balls), simplify the manufacturing process, for example, reduce the difficulty of the ball planting process.

In the package 20 according to the exemplary embodiment of the present invention described with reference to FIG. 2, through holes for electrical connection can also be formed in the substrate by means such as etching, therefore, it is different from the process of manufacturing a printed circuit board (PCB). Compared with the present invention, the manufacturing cost is further reduced, and the stacked chip package can be realized at the wafer level.

A method of manufacturing a package according to an exemplary embodiment of the present invention will be described in detail below with reference to FIGS. 3A to 3F . 3A to 3F are cross-sectional views illustrating a method of manufacturing the package 10 shown in FIG. 1 according to an exemplary embodiment of the present invention. For the sake of simplicity, the same reference numerals are used to indicate the same elements as those in FIG. 1 components, and their detailed descriptions will be omitted.

As shown in Fig. 3A, a quasi-substrate 11' may be prepared in advance. The quasi-substrate 11' may comprise a semiconductor material. Next, as shown in FIG. 3B , the substrate 11 including at least one body portion 11a and at least one stepped portion 11b, 11c may be integrally formed by etching the quasi-substrate 11'. Although it is only shown in FIG. 3B that the substrate 11 is formed to include one body portion 11a and two stepped portions 11b, 11c, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the substrate 11 including a plurality of main body parts and one or more than two stepped parts may be formed as required.

At least one body portion 11a and at least one stepped portion 11b, 11c may be formed to have different heights. For example, the body portion 11a may be formed to have the smallest height, the stepped portion 11c may be formed to have the largest height, and the stepped portion 11b may be formed to have a height greater than that of the body portion 11a and smaller than that of the stepped portion 11c. the height of. In this way, step shapes having different heights can be formed on the upper surface of the substrate 11 . In at least one other exemplary embodiment of the present invention, a height difference between two adjacent parts of the at least one body part and the at least one stepped part is determined according to the thickness of the semiconductor chip to be mounted.

In at least one other exemplary embodiment of the present invention, the substrate 11 may be formed of other semiconductor materials, insulating materials and/or conductive materials as required. For example, when the quasi-substrate 11' is formed of a conductive material such as metal, the substrate 11 including at least one body portion 11a and at least one stepped portion 11b, 11c may be formed by a process such as punching. When the substrate 11 is formed of a conductive material such as metal, a dielectric layer may be formed on the entire surface or a part of the surface of the substrate 11 formed of the metal as necessary to provide good insulating properties. In addition, the substrate 11 including at least one main body portion 11a and at least one stepped portion 11b, 11c may be formed from an insulating material such as resin through a process such as injection molding.

As shown in FIG. 3C , a wiring pattern 12 may be formed on a substrate 11 (eg, an upper surface and/or a lower surface of the substrate 11 ). For example, the wiring pattern 12 may be formed to include at least one portion 12a formed on at least one body portion 11a and at least one portion 12b, 12c formed on at least one stepped portion 11b, 11c. The wiring pattern 12 may be formed on the substrate 11 from a conductive material such as metal through various processes. For example, the wiring pattern 12 may be formed of metal through a deposition process and/or a plating process, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, other conductive materials and/or other processes may be used to form the wiring pattern 12 as required. For example, when the substrate 11 is formed of a semiconductor material, the wiring pattern 12 may be formed through a doping process. In at least one other exemplary embodiment of the present invention, when the substrate 11 is formed of a conductive material such as metal, the wiring pattern 12 may be formed on a dielectric layer formed on the substrate 11 as described above.

According to an exemplary embodiment of the present invention, a via hole 15 electrically connected to the wiring pattern 12 may be formed in the substrate 11, as shown in FIG. 3C. In such a case, the via 15 may be a conductive via. For example, vias may be formed in the substrate 11 such as by an etching process and plated or filled with a conductive material in the vias to form the conductive vias 15 .

At this time, pads for disposing solder balls may also be formed. For example, pads may be formed on or around the wiring pattern 12 and/or the through hole 15 formed on the upper surface and/or lower surface of the substrate 11 through a process such as plating. However, embodiments are not limited thereto. The pads may be formed on or around the lower surface of the substrate 11 and/or the through hole 15 after an encapsulation process of forming an encapsulation material layer which will be described in detail later.

Then, as shown in FIG. 3D , a plurality of semiconductor chips 13 may be stacked and attached on the substrate 11 (eg, on the upper surface of the substrate 11 ) and electrically connected to the wiring patterns 12 respectively. For example, the semiconductor chip 13 may be stacked on at least one body portion 11 a and at least one stepped portion 11 b of the substrate 11 . As shown in FIG. 3D, at least one semiconductor chip 13a may be disposed on at least one main body portion 11a and electrically connected to at least a portion 12a of wiring pattern 12 disposed on at least one main body portion 11a, and at least one semiconductor chip 13b may be disposed on at least one main body portion 11a. At least a part of the semiconductor chip 13b in 13c is disposed on at least one stepped portion 11b and is electrically connected to at least a portion 12b of the wiring pattern 12 disposed on the at least one stepped portion 11b, and at least one semiconductor chip 13b, At least a part of the semiconductor chip 13c in 13c is disposed on at least one stepped portion 11c and is electrically connected to at least a portion 12c of the wiring pattern 12 disposed on the at least one stepped portion 11c. Furthermore, at least another part of the semiconductor chip 13b may be stacked on the semiconductor chip 13a, and at least another part of the semiconductor chip 13c may be stacked on the semiconductor chip 13b. Although only one semiconductor chip 13a disposed on at least one body portion 11a and two semiconductor chips 13b and 13c stacked on the semiconductor chip 13a are shown in FIG. 3D , exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, a plurality of semiconductor chips 13a may be provided on at least one main body portion 11a as required, and one or more semiconductor chips may be stacked on at least one of the plurality of semiconductor chips 13a. Two or more semiconductor chips, wherein at least a part of at least one semiconductor chip of the one or more semiconductor chips stacked on the semiconductor chip 13a can be provided on at least one stepped portion and electrically connected to the wiring At least a part of the pattern 12 is disposed on the at least one stepped portion.

In the exemplary embodiment of the present invention shown in FIG. 3D, a plurality of semiconductor chips 13 may be stacked and mounted on the substrate 11 in a flip-chip manner and electrically connected to the wiring pattern 12, however, the exemplary embodiment of the present invention Exemplary embodiments are not limited thereto. In at least one other exemplary embodiment of the present invention, a plurality of semiconductor chips 13 may be stacked and mounted by various mounting methods such as wire bonding as required.

Afterwards, as shown in FIG. 3E , an encapsulation material layer 14 may be formed on the substrate 11 (eg, the upper surface of the substrate 11 ) to encapsulate the plurality of semiconductor chips 13 . The encapsulation material layer 14 may be formed from an encapsulation material such as epoxy resin through an injection molding process.

Next, as shown in FIG. 3F , connectors 16 may also be provided on the lower surface of the substrate 11 . For example, the connectors 16 may be provided on the wiring pattern 12 formed on the lower surface of the substrate 11 . In addition, the connecting piece 16 can also be arranged to correspond to the through hole 16 (for example, arranged on or around the through hole 16 ). The connector 16 may be electrically connected to the wiring pattern 12 by the via hole 15, thereby electrically connecting at least one semiconductor chip among the plurality of semiconductor chips 13 to the outside (eg, a printed circuit board (PCB)). Connectors 16 may be solder balls, as shown in FIG. 3F . In this case, pads may be formed on or around the wiring pattern 12 and/or the via hole 16 on the lower surface of the substrate 11 as described above, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, connection bumps (bumps), pins (pins) and the like can be used as the connection parts 16 as required.

In the method of manufacturing a package according to an exemplary embodiment of the present invention described with reference to FIGS. 3A-3F , a semiconductor material can be used to form a substrate for mounting a chip instead of a printed circuit board (PCB) in the prior art. ). A process such as plating a conductive material or doping may be used to form a wiring pattern on a substrate formed of a semiconductor material, and a method such as etching may be used to form a through hole for electrical connection in the substrate. Therefore, the manufacturing process of the package is simplified, the manufacturing cost of the package is reduced, the electrical performance of the package is improved, and the stacked chip package can be realized at the wafer level.

A method of manufacturing a package according to another exemplary embodiment of the present invention will be described in detail below with reference to FIGS. 4A to 4G . 4A to 4G are cross-sectional views showing a method of manufacturing the package 20 shown in FIG. 2 according to another exemplary embodiment of the present invention. elements are the same, and their detailed descriptions will be omitted.

As shown in Fig. 4A, a quasi-substrate 21' may be prepared in advance. The quasi-substrate 21' may comprise a semiconductor material. Next, as shown in FIG. 4B , the substrate 21 including at least one body portion 21a and at least one stepped portion 21b, 21c may be integrally formed by etching the quasi-substrate 21'. Although it is only shown in FIG. 4B that the substrate 21 is formed to include one body portion 21a and two stepped portions 21b, 21c, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the substrate 21 including a plurality of main body parts and one or more than two stepped parts may be formed as required.

At least one body portion 21a and at least one stepped portion 21b, 21c may be formed to have different heights. For example, the body portion 21a may be formed to have the smallest height, the stepped portion 21c may be formed to have the largest height, and the stepped portion 21b may be formed to have a height greater than that of the body portion 21a and smaller than that of the stepped portion 21c. the height of. In this manner, step shapes having different heights can be formed on the upper surface of the substrate 21 . In at least one other exemplary embodiment of the present invention, a height difference between two adjacent parts of the at least one body part and the at least one stepped part is determined according to the thickness of the semiconductor chip to be mounted.

In at least one other exemplary embodiment of the present invention, the substrate 21 may be formed of other semiconductor materials, insulating materials and/or conductive materials as required. For example, when the quasi-substrate 21' is formed of a conductive material such as metal, the substrate 21 including at least one body portion 21a and at least one stepped portion 21b, 21c may be formed by a process such as punching. When the substrate 21 is formed of a conductive material such as metal, a dielectric layer may be formed on the entire surface or a part of the surface of the substrate 21 formed of the metal as needed to provide good insulating properties. In addition, the substrate 21 including at least one main body portion 21a and at least one stepped portion 21b, 21c may be formed from an insulating material such as resin through a process such as injection molding.

As shown in FIG. 4C , a wiring pattern 22 may be formed on a substrate 21 (eg, an upper surface and/or a lower surface of the substrate 21 ). For example, the wiring pattern 22 may be formed to include at least one portion 22a formed on at least one body portion 21a and at least one portion 22b, 22c formed on at least one stepped portion 21b, 21c. The wiring pattern 22 may be formed on the substrate 21 from a conductive material such as metal through various processes. For example, the wiring pattern 22 may be formed of metal through a deposition process and/or a plating process, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, other conductive materials and/or other processes may be used to form the wiring pattern 22 as required. For example, when the substrate 21 is formed of a semiconductor material, the wiring pattern 22 may be formed through a doping process. In at least one other exemplary embodiment of the present invention, when the substrate 21 is formed of a conductive material such as metal, the wiring pattern 22 may be formed on a dielectric layer formed on the substrate 21 as described above.

Although not shown, according to an exemplary embodiment of the present invention, like the exemplary embodiment of the present invention shown in FIG. 3C , a via hole electrically connected to the wiring pattern 22 may be formed in the substrate 21 . In such cases, the vias may be conductive vias. For example, vias may be formed in the substrate 21 such as by an etching process and plated or filled with a conductive material in the vias to form conductive vias.

At this time, pads for disposing solder balls may also be formed. For example, pads may be formed on or around the wiring patterns 22 and/or through holes formed on the upper and/or lower surfaces of the substrate 21 through a process such as plating. However, embodiments are not limited thereto. The pads may be formed on or around the wiring pattern 22 and/or the via hole 25 formed on the lower surface of the substrate 21 after an encapsulation process which will be described in detail later and before the connection member 26 as a solder ball is provided.

Then, as shown in FIG. 4D, a plurality of semiconductor chips 23 may be stacked and attached on the substrate 21 (for example, on the upper surface of the substrate 21), and at least one semiconductor chip among the stacked plurality of semiconductor chips 23 may be electrically connected to each other. Connected to the wiring pattern 22 . For example, the semiconductor chip 23 may be stacked on at least one body portion 21 a and at least one stepped portion 21 b of the substrate 21 . As shown in FIG. 4D, at least one semiconductor chip 23a may be disposed on at least one main body portion 21a and electrically connected to at least a portion 22a of wiring pattern 22 disposed on at least one main body portion 21a, and at least one semiconductor chip may be disposed on at least one main body portion 21a. At least a part of 23b is disposed on at least one stepped portion 21b and is electrically connected to at least a portion 22b of the wiring pattern 22 disposed on at least one stepped portion 21b. Furthermore, at least another part of the semiconductor chip 23b may be stacked on the semiconductor chip 23a. Although only one semiconductor chip 23a disposed on at least one body portion 21a and one semiconductor chip 23b stacked on the semiconductor chip 23a are shown in FIG. 4D, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, a plurality of semiconductor chips 23a may be provided on at least one main body portion 21a as required, and multiple semiconductor chips 23a may be stacked on at least one semiconductor chip 23a among the plurality of semiconductor chips 23a. semiconductor chips, wherein at least a part of at least one semiconductor chip among the plurality of semiconductor chips stacked on the semiconductor chips 13a can be disposed on at least one stepped portion 11b and electrically connected to the wiring pattern 12 disposed at least At least a portion 12b of a stepped portion 11b.

In the exemplary embodiment of the present invention shown in FIG. 4D, a plurality of semiconductor chips 23 may be stacked and mounted on the substrate 21 in a flip-chip manner and electrically connected to the wiring pattern 22, however, the exemplary embodiment of the present invention Exemplary embodiments are not limited thereto. In at least one other exemplary embodiment of the present invention, a plurality of semiconductor chips 23 may be stacked and mounted by various mounting methods such as wire bonding as required.

Afterwards, as shown in FIG. 4E , an encapsulation material layer 24 may be formed on the substrate 21 (eg, the upper surface of the substrate 21 ) to encapsulate the plurality of semiconductor chips 23 . The encapsulation material layer 24 may be formed from an encapsulation material such as epoxy resin through an injection molding process.

According to an exemplary embodiment of the present invention, at least a portion 22c of the wiring pattern 22 may be exposed to the outside of the package 20 in the step of forming the encapsulation material layer 24 . 4E shows that at least a portion 22c of the wiring pattern 22 formed on the stepped portion 21c having the largest height of the substrate 21 may be exposed to the outside of the package 20, however, exemplary embodiments of the present invention are not limited to this. In at least one other exemplary embodiment of the present invention, at least a portion of the wiring pattern 22 formed on other portions of the substrate 21 may be exposed as needed. For example, at least a portion of the wiring pattern 22 formed on at least one body portion 21 a of the substrate 21 may be exposed. In this case, the encapsulation material layer 24 may be selectively formed on the substrate 21 through injection molding or the like to encapsulate the plurality of semiconductor chips 23 and expose at least a portion of the wiring pattern 22 .

According to an exemplary embodiment of the present invention, another wiring pattern 27 may also be formed on the upper surface of the encapsulation material layer 24, as shown in FIG. 4F. Like the wiring pattern 22 , the wiring pattern 27 may be formed on the encapsulation material layer 24 by various processes from a conductive material such as metal. For example, the wiring pattern 27 may be formed of metal through a deposition and/or plating process, however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, other conductive materials and/or other processes may be used to form the wiring pattern 27 as required. Although not shown in the drawing, the wiring pattern 27 may be electrically connected to the plurality of chips 23 such as by being electrically connected to at least a portion 22 c of the wiring pattern 22 exposed to the outside of the package 20 .

Next, as shown in FIG. 4G , connectors 26 may also be provided on the upper surface of the encapsulation material layer 24 . The connector 26 may be provided on at least a portion 22c of the wiring pattern 22 exposed to the outside of the package 20 and electrically connected to at least a portion 22c of the wiring pattern 22 exposed to the outside of the package 20, so as to connect multiple At least one semiconductor chip 23 among the semiconductor chips 23 is electrically connected to the outside (for example, a printed circuit board (PCB)). Connectors 26 may be solder balls, as shown in FIG. 4G. In this case, pads for disposing solder balls 26 may also be formed on at least a portion 22 c of the wiring pattern 22 exposed to the outside of the package 20 , however, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the connecting member 26 can be configured as a connecting bump, a pin, etc. as required.

In the case where the wiring pattern 27 is formed on the upper surface of the encapsulation material layer 24 (that is, the upper surface of the package 20) as shown in FIG. At least one of the plurality of semiconductor chips 23 is electrically connected to the outside (for example, a printed circuit board (PCB)). As described above, when the connection member 26 is a solder ball, a pad for disposing the solder ball 26 may also be formed on the wiring pattern 27 .

Although not shown, according to one other exemplary embodiment of the present invention, in the case of forming the through hole in the substrate 21 as described above, a connecting member (not shown) may be provided on the lower surface of the substrate 21. . For example, the connectors may be provided on the wiring pattern 22 formed on the lower surface of the substrate 21, and/or the connectors may be provided corresponding to (eg, on or around) the through holes. The connector 26 may be electrically connected to the wiring pattern 22 by a via hole, thereby electrically connecting at least one semiconductor chip among the plurality of semiconductor chips 23 to the outside (eg, a printed circuit board (PCB)). As mentioned above, when the connector 26 is a solder ball, the package 20 may also include a pad for setting the solder ball 26 on or around the wiring pattern 22 and/or the through hole formed on the lower surface of the substrate 21, However, exemplary embodiments of the present invention are not limited thereto. In at least one other exemplary embodiment of the present invention, the connecting member can be configured as a connecting bump, a pin, etc. as required.

That is, according to an exemplary embodiment of the present invention, a via hole formed in a substrate and/or exposing a part of a wiring pattern to the outside of the package may be provided in the package as needed. In such cases, connectors 26 may be provided on the lower surface of the package (ie, the lower surface of the substrate) and/or the upper surface of the package (ie, the upper surface of the encapsulation material layer).

In the method of manufacturing a package according to an exemplary embodiment of the present invention described with reference to FIGS. 4A-4G , a semiconductor material can be used to form a substrate for mounting a chip instead of a printed circuit board (PCB) in the prior art. ). A process such as plating a conductive material or doping may be used to form a wiring pattern on a substrate formed of a semiconductor material. Therefore, the manufacturing process of the package is simplified, the manufacturing cost of the package is reduced, the electrical performance of the package is improved, and the stacked chip package can be realized at the wafer level.

In the method of manufacturing a package according to an exemplary embodiment of the present invention described with reference to FIGS. 4A-4G , at least a part of a wiring pattern formed on a substrate may be exposed to the outside of the package, and may be formed in the wiring pattern. A connector is provided on at least a part of the exposed part, thereby simplifying the structure of the package, reducing the manufacturing cost of the package, and improving the electrical performance of the package.

In the method of manufacturing a package according to an exemplary embodiment of the present invention described with reference to FIGS. The connection element is arranged on the other wiring pattern, thereby increasing the installation space of the connection element (for example, solder balls), and simplifying the manufacturing process, for example, reducing the difficulty of the ball planting process.

In the method of manufacturing a package according to an exemplary embodiment of the present invention described with reference to FIGS. Compared with the PCB (PCB) process, the manufacturing cost is further reduced, and the stacked chip package can be realized at the wafer level.

While examples of exemplary embodiments of the present invention have been shown and described, it should be understood by those skilled in the art that the exemplary embodiments of the present invention are not limited thereto without departing from the scope of the present invention as defined in the claims. Various modifications may be made to the exemplary embodiments of the invention within the spirit and scope of the invention.

Claims (20)

1. A package, characterized in that the package comprises: Substrate; a wiring pattern formed on the substrate; a plurality of semiconductor chips stacked on the upper surface of the substrate and electrically connected to the wiring pattern; an encapsulation material layer formed on the upper surface of the substrate to encapsulate the plurality of semiconductor chips, Wherein, the substrate includes at least one main body portion and at least one stepped portion, at least a part of at least one semiconductor chip among the plurality of semiconductor chips is disposed on the at least one stepped portion and is electrically connected to a wiring pattern disposed on the at least one stepped portion. at least a portion of the at least one stepped portion. 2. The package of claim 1, wherein the substrate is formed of a semiconductor material. 3. The package of claim 2, wherein the at least one body portion and the at least one stepped portion are integrally formed by an etching process. 4. The package of claim 1, wherein the wiring pattern is formed on the substrate through a plating process. 5. The package of claim 1, wherein the plurality of semiconductor chips are stack-mounted on the upper surface of the substrate in a flip-chip manner and are electrically connected to the wiring pattern. 6. The package of claim 1, wherein the package further comprises: Via holes are formed in the substrate and are electrically connected to the wiring patterns. 7. The package of claim 6, wherein the package further comprises: Connectors are provided on the lower surface of the substrate, the connectors are electrically connected to the wiring patterns by the via holes, thereby electrically connecting the plurality of semiconductor chips to the outside. 8. The package of claim 1, wherein at least another portion of the wiring pattern is exposed to the outside of the package. 9. The package of claim 8, wherein the package further comprises: A connector disposed on the at least another exposed portion of the wiring pattern, the connector being electrically connected to the at least another exposed portion of the wiring pattern to electrically connect the plurality of semiconductor chips to the outside. 10. The package according to claim 1, wherein at least another semiconductor chip of the plurality of semiconductor chips is disposed on the at least one main body portion and is electrically connected to a wiring pattern disposed on the at least one body portion. At least a further part of the one body part, at least another part of the at least one semiconductor chip including at least a part provided on the at least one stepped part is stacked on the at least another semiconductor chip. 11. A method of manufacturing a package, characterized in that said method comprises the steps of: forming a substrate, wherein the substrate includes at least one body portion and at least one stepped portion; forming a wiring pattern on the substrate; A plurality of semiconductor chips are stacked on the upper surface of the substrate and electrically connected to the wiring pattern, wherein at least a part of at least one semiconductor chip of the plurality of semiconductor chips is disposed on the at least one stepped portion and electrically connected to at least a portion of the wiring pattern disposed on the at least one stepped portion; An encapsulation material layer is formed on the upper surface of the substrate to encapsulate the plurality of semiconductor chips. 12. The method of claim 11, wherein the substrate is formed of a semiconductor material. 13. The method of claim 12, wherein, in the step of forming the substrate, the at least one body portion and the at least one stepped portion are integrally formed through an etching process. 14. The method of claim 11, wherein the wiring pattern is formed on the substrate through a plating process. 15. The method of claim 11, wherein the plurality of semiconductor chips are flip-chip mounted on the upper surface of the substrate and electrically connected to the wiring patterns. 16. The method of claim 11, further comprising: Via holes electrically connected to the wiring patterns are formed in the substrate. 17. The method according to claim 16 or claim 17, wherein said method further comprises: Connectors are provided on the lower surface of the substrate such that the connectors are electrically connected to the wiring patterns by via holes, thereby electrically connecting the plurality of semiconductor chips to the outside. 18. The method of claim 11, wherein at least another part of the wiring pattern is exposed to the outside of the package in the step of forming the encapsulation material layer. 19. The method of claim 18, further comprising: A connector is formed on the exposed at least another portion of the wiring pattern such that the connector is electrically connected to the exposed at least another portion of the wiring pattern to electrically connect the plurality of semiconductor chips to the outside. 20. The package according to claim 11, wherein, in the step of stacking the plurality of semiconductor chips, at least another semiconductor chip of the plurality of semiconductor chips is disposed on the at least one main body portion and electrically connected to at least another part of the wiring pattern provided on the at least one body part, and at least another part of the at least one semiconductor chip including at least a part provided on the at least one stepped part is stacked. on said at least one other semiconductor chip.

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