CN102280477B

CN102280477B - Semiconductor device

Info

Publication number: CN102280477B
Application number: CN 201010202456
Authority: CN
Inventors: 黄学义; 李明东; 吴锡垣
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2010-06-09
Filing date: 2010-06-09
Publication date: 2013-09-11
Anticipated expiration: 2030-06-09
Also published as: CN102280477A

Abstract

The invention discloses a semiconductor device suitable for relatively high voltage application, comprising: a substrate; a first N-type well region in the substrate for serving as a high voltage N-well for the semiconductor device; a pair of second N-type well regions in the first N-type well region; a P-type region in the first N-type well region between the pair of second N-type well regions; a pair of conductive regions on the substrate between the pair of second N-type well regions; and a plurality of N-type regions serving as N-type buried layers (NBLs) for the semiconductor device, wherein the NBLs are disposed under the first N-type regions and dispersed in the substrate.

Description

A kind of semiconductor device

Technical field

The invention relates to a kind of semiconductor device, and particularly relevant for a kind of semiconductor device that is applicable to that quite high voltage applies.

Background technology

Power transistor, horizontal (two) diffuse metal oxide-semiconductor (lateral diffusedmetal-oxide-semiconductor for example, LDMOS) transistor AND gate drain electrode is extended MOS (DrainExtension MOS, DEMOS) transistor is used in during high voltage applies usually.A power transistor can be designed to have quite high puncture voltage and quite low conducting resistance ideally.Yet high-breakdown-voltage and low on-resistance may be the compromise proposals of power transistor.Fig. 1 is the layout of a kind of LDMOS device 100 in the prior art.Referring to Fig. 1, LDMOS device 100 can comprise a high voltage N-type well (high voltage n-type well, HVNW) zone 101, a pair of N-type well area 102 in HVNW zone 101 and a N-type embedding layer (n-type buried layer, NBL) 103 between N-type well area 102.For the voltage that applies of 40V, LDMOS 100 may be designed to have for example the puncture voltage of 60V (volt) (breakdownvoltage, BV).Unacceptablely be: in order to reduce the conducting resistance of LDMOS device 100, the concentration of attempting increasing HVNW zone 101 may cause the minimizing of puncture voltage.

Therefore need a kind of not must with the compromise situation of puncture voltage under can have quite low conducting resistance semiconductor device.

Summary of the invention

In view of this, main purpose of the present invention provides a kind of semiconductor device that is applicable to that quite high voltage applies, and it can reach quite low conducting resistance.

According to a first aspect of the invention, a kind of semiconductor device that is applicable to that quite high voltage applies is proposed.This semiconductor device can comprise: a substrate; One first N-type well area is arranged in substrate, in order to as a high voltage n trap of using for semiconductor device (high voltage n-well, HVNW); The a pair of second N-type well area is arranged in the first N-type well area; One p type island region territory, this to the first N-type well area between the second N-type well area in; The pair of conductive zone, this to the substrate between the second N-type well area on; And a plurality of N-types zone, in order to (n-type buried layer, NBL), wherein these a little NBL are arranged in the below in the first N-type zone and are dispersed in substrate as the N-type embedding layer of using for semiconductor device.

According to a second aspect of the invention, a kind of semiconductor device that is applicable to that quite high voltage applies is proposed.This semiconductor device can comprise: a substrate; One first N-type well area is arranged in substrate, in order to a high voltage n trap (HVNW) of using as the confession semiconductor device; The a pair of second N-type well area is arranged in the first N-type well area; One p type island region territory is between this is to the second N-type well area; The pair of conductive zone, this to the substrate between the second N-type well area on; And a plurality of N-types zone, be positioned at the below in the first N-type zone, with as the N-type embedding layer of using for semiconductor device (NBL), wherein these a little NBL comprise: a plurality of NBL, it is configured under the p type island region territory with one first density; And a plurality of the 2nd NBL, being disposed at other zone in the substrate with one second density, first density is greater than second density.

According to a third aspect of the invention we, a kind of semiconductor device that is applicable to that quite high voltage applies is proposed.This semiconductor device can comprise: a substrate; One first N-type well area is arranged in substrate, in order to a high voltage n trap (HVNW) of using as the confession semiconductor device; The a pair of second N-type well area is arranged in the first N-type well area; One p type island region territory is between this is to the second N-type well area; The pair of conductive zone, this to the substrate between the second N-type well area on; And a plurality of N-types zone, be positioned at the below in the first N-type zone, with as the N-type embedding layer of using for semiconductor device (NBL), wherein these a little NBL comprise: a plurality of NBL are configured under the p type island region territory; And a plurality of the 2nd NBL, be disposed at other zone in the substrate, and the concentration of each NBL is greater than the concentration of each the 2nd NBL.

Additional features of the present invention and advantage are suggested part in the following description, and part will be apparent from explanation, maybe may obtain by implementation of the present invention.Feature of the present invention and advantage will be utilized especially element pointed in the claim scope of enclosing and combination and be implemented and obtain.

It will be appreciated that above-mentioned general remark and following detailed description only for illustration and explanation, and unrestricted claim scope of the present invention also.

For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.

Description of drawings

Above-mentioned summary of the present invention and following detailed description will better be understood when reading being associated with annexed drawings.For the present invention is described, a plurality of examples are shown in the accompanying drawings.Yet we it should be noted that the present invention is not subject to accurate configuration and means shown in the example.

In the accompanying drawings:

Fig. 1 is the layout of a horizontal proliferation metal oxide-semiconductor (LDMOS) device of the prior art;

Fig. 2 A is the layout according to the semiconductor device of an example of the present invention;

Fig. 2 B is along the profile of line AA ' in the semiconductor device of Fig. 2 A;

Fig. 3 A system is according to the layout of the semiconductor device of another example of the present invention;

Fig. 3 B is along the profile of line BB ' in the semiconductor device in Fig. 3 A; And

4A to 4H figure is the profile that illustrates according to the manufacture method of the semiconductor device of an example of the present invention.

[main element symbol description]

20,40: substrate

41,41-1,41-2,41-3: be injected into the zone

42: the patterning photoresist layer

43: opening

44: epitaxial loayer

45: the first well areas

46: the second well area/the 2nd n traps

47:P type zone/P type base stage

48,49: patterned conductive layer

The 100:LDMOS device

101: the high voltage N-type well area

102:N type well area

103:N type embedding layer

200,300: semiconductor device

201: the n trap (HVNW) zones

202: the two n well areas

203:P type zone/P type base stage

204: conductive region

231,232,233,331,332,333:N type embedding layer (NBL)

Embodiment

Now detailed description is illustrated in the example of the present invention in the accompanying drawing.If if possible, the identical reference number of graphic middle use will represent same or similar part.

Fig. 2 A is the layout according to the semiconductor device 200 of an example of the present invention.Semiconductor device 200 can be used as the power transistor that applies usefulness for high voltage, horizontal (two) diffuse metal oxide-semiconductor (1ateral diffused metal-oxide-semiconductor for example, LDMOS) MOS (drain extension MOS, DEMOS) transistor are extended in transistor or drain electrode.See also Fig. 2 A, semiconductor device 200 can comprise: one the one n trap (n-well, HVNW) zone 201, for example the high voltage n trap in a substrate 20 (high voltage NW, HVNW); A pair of the 2nd n well area 202, the position is in a HVNW 201; One p type island region territory 203, this to the HVNW 201 between the 2nd n well area 202 in; Pair of conductive zone 204 is positioned on the substrate 20; And a plurality of N-type embedding layers (n-type buried layer, NBL) 231,232 and 233, be dispersed in a HVNW 201 belows.In specific words, these a little NBL 231 can be positioned under the p type island region territory 203 in fact, these a little NBL 232 can be in fact under the zone between p type island region territory 203 and each the 2nd n well area 202, and these a little the 3rd NBL 233 can be in fact under the periphery and the zone between each the 2nd n well area 202 of first HVNW 201.

What difference was illustrated in single NBL 103 among Fig. 1 is, the a plurality of NBL 231,232 and 233 that are dispersed in a HVNW 201 belows can help improve puncture voltage (the breakdown voltage of semiconductor device 200, BV), from for example about 60 volts (V) to about 65V.As discussed previously, the increase of the concentration of HVNW (HVNW 201 in this example) may cause the reduction of puncture voltage, and therefore it may be down to below the acceptable numerical value.Be increased to from 60V under the situation of 65V in puncture voltage, by increasing the concentration of a HVNW 201, the increment of 5V can promote the reduction of the conducting resistance of semiconductor device 200.In specific words, no matter therefore the increment of 5V may increase along with the concentration of a HVNW 201 and by payment (that is puncture voltage can roll back 60V, yet its voltage that applies for 40V is a kind of acceptable numerical value), conducting resistance still can reduce.

These a little NBL 231,232 and 233 can form by inject n type impurity from each mask opening.In an example, the gross area of the mask opening that a little NBL 231 to 233 are relevant can equal the area of the mask opening relevant with NBL shown in Figure 1 103 therewith.

In this example, these a little NBL 231,232 and 233 can be evenly distributed in HVNW201 below.Therefore, these a little NBL 231,232 with 233 density and synthetic concentration in fact can be identical.

Fig. 2 B is along the profile of line AA ' in the semiconductor device 200 of Fig. 2 A.See also Fig. 2 B, p type island region territory 203 (it can be used as the base stage for semiconductor device 200 usefulness) more can comprise a pair of a large amount of doped N-type (n+) zone (not having numbering) and the zone of a large amount of doping P types (p+) between the n+ zone (not having numbering).A large amount of doped N-types and p type island region territory in P type base stage 203 can be used as the one source pole zone.Moreover a plurality of contacts (do not have numbering) may be formed on the source region with as source terminal.

This more can comprise a large amount of doped N-types (n+) zone (not having numbering) to each of the 2nd n well area 202, and it is as the drain region for semiconductor device 200 usefulness.Moreover a plurality of contacts (do not have numbering) can be formed on these a little drain regions with as drain terminal.

This can be used as the gate terminal that supplies semiconductor device 200 usefulness to conductive region 204 (it can comprise polysilicon).One of them conductive region 204 can be in fact on the substrate 20 between source region and one of them drain region, and another conductive region 204 can be in fact on the substrate 20 between source region and another drain region.

In addition, insulating regions (being denoted as " OD " at Fig. 2 A) for example is that (field oxide FOX) can be positioned on the substrate 20 field oxide, in order to improve element safety operation scope (SOA, Safe operationarea).

Fig. 3 A is the layout according to the semiconductor device 300 of another example of the present invention.See also Fig. 3 A, except NBL 331 for example, 332 and 333 distribution, semiconductor device 300 may be similar to the illustrated semiconductor device 200 with demonstration of Fig. 2 A.In specific words, a plurality of NBL 331 that are positioned in fact under the p type island region territory 203 can one first density be configured.Moreover a plurality of the 2nd NBL 332 under the zone between p type island region territory 203 and each the 2nd n well area 202 can one second density be configured in fact.In addition, can be configured by a triple density at the periphery of first HVNW 201 and a plurality of the 3rd NBL 333 under the zone between each the 2nd n well area 202 in fact.In this example, first density can be greater than each of second density and triple density.In addition, second density can be greater than triple density.For example, when give 40V apply voltage the time, these a little NBL 331 may be separated from one another about 1 micron (μ m), these a little the 2nd NBL 332 may be separated from one another about 1 to 2 μ m, and these a little the 3rd NBL 333 may be separated from one another about 2 to 3 μ m.

The synthetic concentration of NBL 331 to 333 can be positively correlated with the density of distribution.That is it is more intensive that NBL disposes, and then synthetic concentration is bigger.In an example, give 10 ¹³Cm ^-2Identical implantation concentration, then the synthetic concentration of these a little NBL 331 can be approximately 10 ¹⁹To 10 ²⁰Cm ^-3, the synthetic concentration of these a little the 2nd NBL 332 can be approximately 10 ¹⁷To 10 ¹⁹Cm ^-3, and the synthetic concentration of these a little the 3rd NBL 333 can be approximately 10 ¹⁷Cm ^-3The distribution of this NBL can make the increase of puncture voltage, and it can make the minimizing of conducting resistance in regular turn.

Fig. 3 B is along the profile of line BB ' in the semiconductor device 300 among Fig. 3 A.See also Fig. 3 B, a little NBL of this under p type island region territory 203 331 comparable these a little second and the 3rd NBL332 and 333 are configured more thick and fast.

Fig. 4 A to Fig. 4 H is the profile that illustrates according to the manufacture method of the semiconductor device of an example of the present invention.See also Fig. 4 A, a substrate 40 of being made up of silicon is provided, it has been impregnated in one first type impurity.In an example, the first type impurity can comprise the P-type material of boron for example or indium.Moreover the scope of the resistivity of substrate 40 can be from about 8 to 12 ohm-centimeter (ohm-cm).Yet in another example, the first type impurity can comprise the n type material of phosphorus impurities for example or antimony.For simplify just, can suppose that the first type impurity is P-type material, and the second type impurity is n type material.

Then, form a patterning photoresist layer 42 on substrate 40, expose a plurality of parts of substrate 10 by a plurality of openings 43.Drive in the injection technology of (drive-in) technology being accompanied by one, this of substrate 40 exposes the zone can mix n type impurity through a little openings 43 thus, uses producing a plurality of zones 41 that are injected into.In a foundation example of the present invention, this concentration that is injected into zone 41 a bit can be approximately 10 ¹³To 10 ¹⁵Cm ^-2Moreover, be injected into the thickness that zone 41 can have about 2 μ m.Each is injected into zone 41 can be therefore as a N-type embedding layer (NBL).Then, peelable patterning photoresist layer 42.

In this example, as be illustrated among Fig. 4 A, this is injected into zone 41 and may be configured equably in fact.In other example, as be illustrated among Fig. 4 B, be injected into comparable being positioned at of regional 41-1 near a plurality of first of a central area of substrate surface and be injected into regional 41-2 away from a plurality of second of central area and be configured more thick and fast, itself thereby comparable being positioned at are injected into regional 41-3 further from a plurality of the 3rd of central area and are configured more thick and fast.

See also Fig. 4 C, an epitaxial loayer 44 of the first type impurity can be formed on the substrate 40 by a for example depositing operation.In an example, epitaxial loayer 44 can have the thickness of about 5 μ m, and it has the resistivity of about 45ohm-cm.

See also Fig. 4 D, one first well area 45 of the second type impurity (that is, n well area 45) can be by photoetching process (lithography process) for example, be accompanied by a N-type injection technology and a hot injection process and be formed in the epitaxial loayer 44 that is injected on regional 41.In an example, first well area 45 (it can be considered HVNW subsequently) can have the thickness of about 5 μ m.

See also Fig. 4 E, a pair of second well area 46 of the second impurity pattern (that is, n trap 46) can pass through photoetching process, is accompanied by a N-type injection technology and an injection process and is formed in the n trap 45.Moreover for example a plurality of insulating regions of FOX can be by a depositing operation for example, is accompanied by a thermal oxidation technology and is formed at desired locations on the substrate 40.

See also Fig. 4 F, a p type island region territory 47, it can pass through a photoetching process in order to as a base region between these a little the 2nd n traps 46, is accompanied by a P type injection technology and an injection process and is formed in the n trap 45.Then, a patterned conductive layer 48, it can pass through a depositing operation in order to as a plurality of gate terminals, is accompanied by an etch process and forms.

See also Fig. 4 G, an injection technology can be passed through in the N-type of a plurality of a large amount of doping (n+) zone, and is formed at these a little the 2nd n traps 46 therewith in the p type island region territory 47.N+ zone in the 2nd n trap 46 can be used as the drain region.Moreover a large amount of doped P-type (p+) zone can be formed in the P type base stage 47 between this a little n+ zone, uses to produce the one source pole zone.

See also Fig. 4 H, another patterned conductive layer 49 can be formed on these a little the 2nd n traps 46 and the p type island region territory 46, uses producing drain electrode and the source terminal of using for semiconductor device.

It will be appreciated by one of skill in the art that not deviating under its vast inventive concept, can make change at above-mentioned example.Therefore, be understood that the present invention is not subject to disclosed specific examples, but intention is encompassed in as by the modification within the defined spirit of the present invention of the claim scope of enclosing and the category.

Moreover in explanation representation example of the present invention, specification may provide method of the present invention and/or the technology step as particular order.Yet method or technology is not by in the step of the particular order that this proposed to a certain extent, and method or technology should not be subject to the step of illustrated particular order.One of them it will be appreciated by one of skill in the art that the step of other sequence also is possible.Therefore, the step of the particular order that proposes in the specification should not be interpreted into the restriction to the claim scope.In addition, should not be subject to their performance of step of being docile and obedient that order writes at the claim scope of method of the present invention and/or technology, and those skilled in the art can understand easily that sequence may change and still maintains within spirit of the present invention and the category.

In sum, though the present invention discloses as above with a preferred embodiment, so it is not in order to limit the present invention.Those skilled in the art without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is when looking being as the criterion that the claim scope of enclosing defines.

Claims

1. a semiconductor device that is applicable to that quite high voltage applies is characterized in that, comprising:

One substrate;

One first N-type well area is arranged in this substrate, in order to a high voltage n trap HVNW who uses as this semiconductor device of confession;

The a pair of second N-type well area is arranged in this first N-type well area;

One p type island region territory, this to this first N-type well area between the second N-type well area in;

The pair of conductive zone, this to this substrate between the second N-type well area on; And

A plurality of N-types zone, in order to a plurality of N-type embedding layer NBL that use as this semiconductor device of confession, wherein these a plurality of NBL are arranged in the below of this first N-type well area and are dispersed in this substrate;

Wherein, these a plurality of NBL comprise:

A plurality of NBL are positioned under this p type island region territory;

A plurality of the 2nd NBL are located at this p type island region territory and respectively under the zone between this second N-type well area; And

A plurality of the 3rd NBL are at this periphery of this first N-type well area and respectively under the zone between this second N-type well area.

2. semiconductor device according to claim 1 is characterized in that, these a plurality of NBL are configured in this substrate under this first N-type well area equably.

3. semiconductor device according to claim 1 is characterized in that, these a plurality of NBL are configured with one first density, and these a plurality of the 2nd NBL are configured with one second density, and this first density is greater than this second density.

4. semiconductor device according to claim 3 is characterized in that, these a plurality of the 3rd NBL are configured with a triple density, and this triple density is less than this first density.

5. semiconductor device according to claim 3 is characterized in that, these a plurality of the 3rd NBL are configured with a triple density, and this triple density is less than this second density.

6. semiconductor device according to claim 1 is characterized in that, respectively a NBL have one first concentration and respectively the 2nd NBL have one second concentration, this first concentration is greater than this second concentration.

7. semiconductor device according to claim 6 is characterized in that, respectively the 3rd NBL has one the 3rd concentration, and the 3rd concentration is less than this first concentration.

8. semiconductor device according to claim 6 is characterized in that, respectively the 3rd NBL has one the 3rd concentration, and the 3rd concentration is less than this second concentration.

9. semiconductor device according to claim 1 is characterized in that, as a plurality of drain regions, and this p type island region territory more comprises a pair of N-type zone and a p type island region territory to the second N-type well area for this, as the source region.