CN102298973B - Radiation-resistant fault-protected storage device and radiation-resistant fault-protected method thereof - Google Patents

Abstract

The invention discloses an anti-radiation fault-secure type memory device, and an anti-radiation fault-secure method thereof, and relates to an anti-radiation fault-secure type memory device, and a protection method thereof. In the prior art, multiple-bit upsets exist in the existing memory array; single event transient effects exist in an encoder, a decoder and other combinational circuits; EG-LDPC codes require a plurality of redundant bits to store encoded information so as to increase large area overhead and increase the chip cost. A purpose of the present invention is to solve the problems in the prior art. The anti-radiation fault-secure method comprises: 1, selecting the EG-LDPC codes and the Hamming codes; 2, dividing the EG-LDPC codes into M parts; 3, uniformly inserting the Hamming codes into the intervals of the M parts; 4, adopting a constraint algorithm to ensure the fault-secure characteristic of the mixed codes. The device has characteristics of low area and delay overhead, and can be applicable for synchronously inhibiting the multiple-bit upsets in the memory array and the single event transient effects in the encoder, the decoder and other combinational circuits.

Description

Radiation-resistant fault-protected storage device and radiation-resistant fault-protected method thereof

technical field

The invention relates to an anti-failure protection storage device and a protection method thereof.

Background technique

With the continuous reduction of the size of the integrated process, the integrated circuit is more and more sensitive to the space radiation environment and the ground noise environment, and the normal working state of the circuit is seriously affected. Error Correcting Code (ECC) is a common method for correcting faults in memory. However, as the distance between adjacent cells in the memory continues to shrink, the probability of multiple bit flips caused by a radiation event greatly increases; at the same time, since the ECC circuit needs to be composed of an encoder and a decoder, these combined circuits will be affected by radiation. The influence of single-event transient effects induced. Therefore, there is a need for a more effective memory fault protection (Fault-Secure) hardening technology, which can not only correct multi-bit errors in the storage array, but also correct errors in the ECC circuit.

Hamming codes are the most common error correction technology in ECC, which can correct one bit and detect two bit errors. Hamming code has the characteristics of simple coding structure and easy implementation, but it cannot correct errors of more than two digits. Euclidean Geometry Low-Density Single Parity-Check Code (EG-LDPC) is the only ECC code known to be fail-safe. EG-LDPC code is a kind of block cyclic code, it can correct multiple errors, and has the characteristics of high code gain and low bit error rate, and has been widely used in the field of communication. EG-LDPC code is also a kind of large number logic decodable, compared with other iterative decoding methods of block cyclic codes, it has the characteristics of fast decoding speed. The specific decoding method is as follows: First, by calculating the inner product of the received data vector and its own parity check matrix, α parity check sums are obtained; then α parity check sums are input into the large number logic gate for judgment; if If the output result of the large number gate is 1, the corresponding data bit needs to be flipped if an error occurs in the transmitted data; if the output result of the large number gate is 0, the transmitted data is correct and remains unchanged.

The fault protection capability of an ECC code is determined by the detector circuit composed of its syndrome (syndrome) S _i . The syndrome detection circuit can detect whether the information bits output by the encoder, decoder and its own circuit are correct. If the decoding is correct, the syndrome is 0, and if an error occurs in the decoding, the syndrome is not 0. For an EG-LDPC code with a word length of n, it will generate n syndromes, which are used to generate the detection signal and feed back to the memory. If an uncorrectable error occurs in the encoder, decoder or detector, it will be interrupted. And resend the wrong data, so that the memory has a fault protection capability, the correction scheme is shown in Figure 1.

However, not all ECC encodings are failsafe. Let J be the minimum distance of the ECC code, then the maximum error correction capability E of the ECC code is (J-1)/2, the maximum detection capability D is J-1, and the weight of the error pattern satisfies 0< e≤J-1. The errors occurring in the encoder, decoder and correction circuit are marked with E _e , E _d and E _s respectively, and the errors in the storage array are E _m . For ordinary ECC codes, E _m ≤ E and E _e = E _d = 0 must be satisfied, while for ECC codes with fault protection capabilities, E _e + E _m ≤ E and E _e + E _m + E _d + E _s must be satisfied ≤D. Assuming that the error pattern weight in the fail-safe ECC is E _e +E _m +E _d =e, the error weight of the syndrome circuit within the detectable range should satisfy E _s ≤ J-1-e. To ensure that each error in the syndrome circuit affects only one syndrome bit, and realize the detection of errors in the syndrome circuit itself, the weight of the syndrome needs to be at least Je. It has been proven that the syndrome weight of the EG-LDPC code can be greater than Je, so it has the ability of fault protection.

Since EG-LDPC codes require more redundant bits to store coding information, and the storage unit occupies most of the area of the entire memory, the fault protection scheme of EG-LDPC codes will bring huge area overhead and increase the chip cost. the cost of. In addition, the EG-LDPC of some code segments requires multi-step large number logic to realize decoding, which brings excessive delay overhead and is not suitable for some high-speed memory applications.

Contents of the invention

The present invention does not solve the multi-bit inversion that occurs in the existing storage array, but also can suppress the single-event transient effect that occurs in combination circuits such as encoders and decoders, and the existing EG-LDPC code requires more redundant bits. The storage of encoded information brings huge area overhead and increases the cost of the chip; and a radiation-resistant fault-protection type storage device and a radiation-resistant fault protection method thereof are proposed.

Anti-radiation fault protection type storage device, it comprises mixed code coding component and mixed code decoding component; Described mixed code coding component is made up of EG-LDPC code coding module and Hamming code coding module; Information coding of EG-LDPC code coding module The data input end and the information encoding data input end of the Hamming code encoding module are connected to the external information data output end at the same time; the EG-LDPC code encoding data output end of the EG-LDPC code encoding module is connected to the EG-LDPC code encoding data input of the storage array module The terminal is connected; the Hamming code encoding data output end of the Hamming code encoding module is connected with the Hamming code encoding data input end of the storage array module; the mixed code decoding assembly is composed of an EG-LDPC code decoding module and a Hamming code decoding module; The EG-LDPC code decoding data input terminal of the EG-LDPC code decoding module is connected to the EG-LDPC code decoding data output terminal of the storage array module; the Hamming code decoding data input terminal of the Hamming code decoding module is connected to the storage array module The Hamming code decoding data output end is connected; It also includes coding error code detection component and decoding error code detection component; Described coding error code detection component is detected by EG-LDPC code coding error code detection module and Hamming code coding error code detection Module composition;

The EG-LDPC code encoding error code detection data input end of the EG-LDPC code encoding error code detection module is connected with the EG-LDPC code encoding data output end of the EG-LDPC code encoding module; the Hamming code encoding error code detection module The Hamming code encoding error code detection data input end of the Hamming code encoding module is connected to the Hamming code encoding data output end;

Described decoding error code detection assembly is made up of EG-LDPC code decoding error code detection module and Hamming code decoding error code detection module;

The EG-LDPC code decoding error code detection data input end of the EG-LDPC code decoding error code detection module is connected with the EG-LDPC code decoding data output end of the EG-LDPC code decoding module; the Hamming code decoding The Hamming code decoding error code detection data input end of the code error code detection module is connected with the Hamming code decoding data output end of the Hamming code decoding module;

The EG-LDPC code decoding accompanying data input end of the EG-LDPC code decoding error code detection module is simultaneously with the EG-LDPC code decoding accompanying data output end of the EG-LDPC code decoding module, and the Hamming code decoding module The Hamming code decoding accompanying data output terminal is connected with the Hamming code decoding accompanying data input terminal of the Hamming code decoding error code detection module.

The anti-radiation fault protection method of the above-mentioned anti-radiation fault protection storage device is composed of the following steps:

Step 1: According to the data width N of the hardened memory, select the EG-LDPC code with the code word (n1, k1) and the Hamming code with the code word (n2, k2); where n1 and k1 are the EG-LDPC code Code length and data width, n2 and k2 are the code length and data width of Hamming code respectively;

Step 2: Divide the EG-LDPC code with code length n1 selected in step 1 into M parts, the value of M is equal to the code length n2 of the Hamming code, and the length of each part in the M parts is at least 2 bits ;

Step 3: Insert the Hamming code with a code length of n2 evenly into the interval of the M parts divided by the EG-LDPC code, so that each byte of the Hamming code is physically separated; if the Hamming code and EG -The code length and information bits of the LDPC code satisfy equations 1 and 2, that is, a mixed code with a data width of N and a code length of n1+n2 is formed;

$\frac{\mathrm{<figure-callout\; id="1"\; label="no"\; filenames="HDA0000065954010000012.png"\; state="\{\{state\}\}">no</figure-callout>}1}{\mathrm{<figure-callout\; id="2"\; label="no"\; filenames="HDA0000065954010000012.png"\; state="\{\{state\}\}">no</figure-callout>}2}\&Greater\; Equal;2$ Equation 1

k1+k2=N Equation 2

Step 4: Ensure the fail-safe characteristics of the hybrid code through the fail-safe constraint algorithm; let J be the minimum distance of the error-correcting code, e be the weight of the error pattern, and check matrix of the system form

${\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; systematic</span>}}<span\; class="notranslate">\; =</span>\left[\begin{array}{cccccccccccccccccccccc}\mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\end{array}\right]$

Carry out row elementary transformation to obtain the parity check matrix H _FS with fault protection capability;

${\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; FS</span>}}<span\; class="notranslate">\; =</span>\left[\begin{array}{cccccccccccccccccccccc}\mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\\ \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\\ \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\end{array}\right]$

The check matrix _HFS with fault protection capability satisfies the following conditions:

a. Each column contains at least J 1s;

b. The total number Z of 1s in the failsafe parity check matrix H _FS is kept between "(J+1)×number of matrix columns≥Z≥J×matrix column number';

c. The number of 1s in each row in the failsafe parity check matrix _HFS is equal;

Step 5: Use the EG-LDPC code check matrix and the Hamming code check matrix H _FS obtained in step 4 to obtain the parameters of the encoder and decoder of the mixed code by performing corresponding vector matrix multiplication with the received and sent data bits The parameters of the detector and the parameters of the detector; the encoder of the mixed code, the decoder and the detector are connected to form a radiation-resistant fault protection storage device.

The anti-radiation fault protection storage device of the invention has the characteristics of low area and delay overhead, and is suitable for simultaneously suppressing multi-bit inversion in a storage array and single event transient effects in combined circuits such as encoders and decoders.

Description of drawings

Fig. 1 is the fault protection device structural representation of ECC coding; Fig. 2 is the module structural representation of the present invention; Fig. 3 is the structure of mixed code word in the method described in specific embodiment two, wherein M represents Hamming code, and E represents EG-LDPC code, A represents the error interval, and B represents the length of each part.

Detailed ways

Specific Embodiment 1: This embodiment is described in conjunction with FIG. 2 . The anti-radiation fault protection storage device described in this embodiment includes a mixed code encoding component 2 and a mixed code decoding component 3; the mixed code encoding component 2 consists of The EG-LDPC code encoding module 2-1 and the Hamming code encoding module 2-2 are composed; the information encoding data input end of the EG-LDPC code encoding module 2-1 and the information encoding data input end of the Hamming code encoding module 2-2 are simultaneously connected with The external information data output end is connected; the EG-LDPC code encoding data output end of the EG-LDPC code encoding module 2-1 is connected with the EG-LDPC code encoding data input end of the storage array module 1; the Hanming code encoding module 2-2 The output end of the plain code coded data is connected to the input port of the Hamming code coded data of the storage array module 1; the mixed code decoding component 3 is composed of an EG-LDPC code decoding module 3-1 and a Hamming code decoding module 3-2; EG -The EG-LDPC code decoding data input end of the LDPC code decoding module 3-1 is connected with the EG-LDPC code decoding data output end of the storage array module 1; the Hamming code decoding data of the Hamming code decoding module 3-2 The input end is connected with the Hamming code decoded data output end of storage array module 1; It also comprises encoding error code detection component 4 and decoding error code detection component 5; Described encoding error code detection component 4 is coded by EG-LDPC code error Composed of code detection module 4-1 and Hamming code error code detection module 4-2;

The EG-LDPC code encoding error code detection data input end of the EG-LDPC code encoding error code detection module 4-1 is connected with the EG-LDPC code encoding data output end of the EG-LDPC code encoding module 2-1; The Hamming code coding error code detection data input end of the plain code coding error code detection module 4-2 is connected with the Hamming code coding data output end of the Hamming code coding module 2-2;

Described decoding error code detection assembly 5 is made up of EG-LDPC code decoding error code detection module 5-1 and Hamming code decoding error code detection module 5-2;

The EG-LDPC code decoding error code detection data input end of the EG-LDPC code decoding error code detection module 5-1 is connected with the EG-LDPC code decoding data output end of the EG-LDPC code decoding module 3-1 The Hamming code decoding error code detection data input end of the Hamming code decoding error code detection module 5-2 is connected to the Hamming code decoding data output end of the Hamming code decoding module 3-2;

The EG-LDPC code decoding accompanying data input terminal of the EG-LDPC code decoding error code detection module 5-1 is simultaneously connected with the EG-LDPC code decoding accompanying data output terminal of the EG-LDPC code decoding module 3-1, The Hamming code decoding accompanying data output terminal of the Hamming code decoding module 3-2 is connected with the Hamming code decoding accompanying data input terminal of the Hamming code decoding error code detection module 5-2. The EG-LDPC code is the Euclidean geometry low density single parity check code.

The working principle of the anti-radiation fault protection type storage device is as follows: data is stored in the storage array module 1 through the mixed code encoding component 2, if a radiation event affects multiple data bits in the storage array module 1, and the state of the data changes, then the data in During the process of reading out the memory array module 1 , these data can be corrected by the mixed code decoding component 3 . If error occurs in the mixed code encoding component 2, the mixed code decoding component 3, the encoding error code detection component 4 and the decoding error code detection component 5, then it can be detected by the encoding error code detection component 4 and the decoding error code detection component 5 Errors are detected and subsequently corrected. The anti-radiation fault protection storage device of the invention has the characteristics of low area and delay overhead, and is suitable for simultaneously suppressing multi-bit inversion in a storage array and single event transient effects in combined circuits such as encoders and decoders.

Embodiment 2: The radiation-resistant fault protection method of the radiation-resistant fault-protected storage device described in Embodiment 1 is adopted, which consists of the following steps:

Step 1: According to the data width N of the reinforced memory, select the EG-LDPC code with the code word (n1, k1) and the Hamming code with the code word (n2, k2); where n1 and k1 are the EG-LDPC code Code length and data width, n2 and k2 are the code length and data width of Hamming code respectively;

Step 2: Divide the EG-LDPC code with code length n1 selected in step 1 into M parts, the value of M is equal to the code length n2 of the Hamming code, and the length of each part in the M parts is at least 2 bits ;

Step 3: Insert the Hamming code with a code length of n2 evenly into the interval of the M parts divided by the EG-LDPC code, so that each byte of the Hamming code is physically separated; if the Hamming code and EG -The code length and information bits of the LDPC code satisfy equations 1 and 2, that is, a mixed code with a data width of N and a code length of n1+n2 is formed;

$\frac{\mathrm{no}1}{\mathrm{no}2}\&Greater\; Equal;2$ Inequality 1

k1+k2=N Equation 2

Step 4: Ensure the fail-safe characteristics of the hybrid code through the fail-safe constraint algorithm; let J be the minimum distance of the error-correcting code, e be the weight of the error pattern, and check matrix of the system form

${\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; systematic</span>}}<span\; class="notranslate">\; =</span>\left[\begin{array}{cccccccccccccccccccccc}\mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\end{array}\right]$

Carry out row elementary transformation to obtain the parity check matrix H _fs with fault protection capability;

${\mathrm{<span\; class="notranslate">\; h</span>}}_{\mathrm{<span\; class="notranslate">\; FS</span>}}<span\; class="notranslate">\; =</span>\left[\begin{array}{cccccccccccccccccccccc}\mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\\ \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\\ \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}\\ \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 0</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}& \mathrm{<span\; class="notranslate">\; 1</span>}\end{array}\right]$

The check matrix H _fs with fault protection capability satisfies the following conditions:

a. Each column contains at least J 1s;

b. The total number Z of 1s in the failsafe parity check matrix _Hfs is kept between "(J+1)×number of matrix columns≥Z≥J×matrix column number';

c. The number of 1s in each row in the failsafe check matrix H _fs is equal;

Step 6: Use the EG-LDPC code check matrix and the Hamming code check matrix H _fs obtained in step 5 to obtain the encoder, decoder and detector of the mixed code by performing corresponding vector matrix multiplication with the received and sent data bits device; the encoder, decoder and detector of the mixed code are connected to form a radiation-resistant fault protection type storage device.

Purpose: The mixed code encoder encodes the written data, and the encoded data is stored in the memory. The mixed code decoder decodes the data read out of the memory. If the radiation event affects multiple data bits in the memory and changes the state of the data, then these multi-bit inversions can be corrected by the mixed code decoder. Hybrid code detectors can detect and subsequently correct single-event upsets in encoders, decoders, and detectors.

The fault-protected memory system composed of the mixed code obtained by the above method has the characteristics of low area and delay overhead, and is suitable for simultaneously suppressing multi-bit flips in memory arrays and single event transients in combinational circuits such as encoders and decoders. state effect.

Embodiment 3: The difference between this embodiment and Embodiment 2 is that a codeword is defined as (n, k, t), where n is the code length, k is the information bit, and t represents the error correction capability. The EG-LDPC code can provide strong error correction capability for the data bits commonly used in the storage array module 1, but it needs to be realized through double redundancy and multi-step decoding, which will bring excessive power to the entire storage array module 1. area and latency overhead. Furthermore, excessive error correction capability (eg 15 bits) is not required for typical radiation environments. Reinforcement scheme for mixed codes

EG-LDPC code (127,64,7) (208,128,8) (511,256,15) (754,512,16) Combined EG-LDPC code (63,48,2) (127,99,3) (255,231,2) (511,448,4) Hamming code (21,16,1) (35,29,1) (30,25,1) (71,64,1) mixed code (84,64,2) (162,128,3) (285,256,2) (582,512,4) Redundancy reduction 68% 58% 89% 71% Decoding steps are reduced 2 steps 0 steps 3 steps 0 steps

The comparison between the reinforcement scheme of the hybrid code and the reinforcement scheme of the EG-LDPC code is shown in Table I. The first line in the table is the reinforcement scheme of the EG-LDPC code, the second and third lines are the selected EG-LDPC codes with low weight or fewer decoding stages and the corresponding Hamming codes respectively, and the third line is the mixed code reinforcement scheme. It can be seen from Table I that the redundant bits and decoding steps of the reinforcement scheme of the hybrid code are significantly reduced. Other compositions and connection methods are the same as those in the second embodiment.

The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in this technical field, without departing from the concept of the present invention, some simple deduction or replacement can also be made, which should be regarded as belonging to the scope of patent protection determined by the claims submitted by the present invention .

Claims (2)

1. Anti-radiation fault-secure type memory device, is characterized in that it comprises hybrid code encoding pack (2) and hybrid code translation subassembly (3); Described hybrid code encoding pack (2) is comprised of EG-LDPC code coding module (2-1) and Hamming code coding module (2-2); The information coding data input pin of the information coding data input pin of EG-LDPC code coding module (2-1) and Hamming code coding module (2-2) is connected with external information data output end simultaneously; The EG-LDPC code coded data output terminal of EG-LDPC code coding module (2-1) is connected with the EG-LDPC code coded data input end of storage array module (1); The Hamming code coded data output terminal of Hamming code coding module (2-2) is connected with the Hamming code coded data input end of storage array module (1); Described hybrid code translation subassembly (3) is comprised of EG-LDPC code decoding module (3-1) and Hamming code decoding module (3-2); The EG-LDPC code decoding data input end of EG-LDPC code decoding module (3-1) is connected with the EG-LDPC code decoding data output terminal of storage array module (1); The Hamming code decoding data input end of Hamming code decoding module (3-2) is connected with the Hamming code decoding data output terminal of storage array module (1); Described memory storage also comprises code error code probe assembly (4) and decoding error code probe assembly (5); Described code error code probe assembly (4) is comprised of EG-LDPC code code error code detecting module (4-1) and Hamming code code error code detecting module (4-2);

The EG-LDPC code code error code detection data input end of described EG-LDPC code code error code detecting module (4-1) is connected with the EG-LDPC code coded data output terminal of EG-LDPC code coding module (2-1); The Hamming code code error code detection data input end of described Hamming code code error code detecting module (4-2) is connected with the Hamming code coded data output terminal of Hamming code coding module (2-2);

Described decoding error code probe assembly (5) is comprised of EG-LDPC code decoding error code detecting module (5-1) and Hamming code decoding error code detecting module (5-2);

The EG-LDPC code decoding error code detection data input end of described EG-LDPC code decoding error code detecting module (5-1) is connected with the EG-LDPC code decoding data output terminal of EG-LDPC code decoding module (3-1); The Hamming code decoding error code detection data input end of described Hamming code decoding error code detecting module (5-2) is connected with the Hamming code decoding data output terminal of Hamming code decoding module (3-2);

The EG-LDPC code decoding companion data input end of described EG-LDPC code decoding error code detecting module (5-1) simultaneously with EG-LDPC code decoding companion data output terminal, the Hamming code decoding companion data output terminal of Hamming code decoding module (3-2) and the Hamming code decoding companion data input end of Hamming code decoding error code detecting module (5-2) of EG-LDPC code decoding module (3-1) be connected.

2. adopt the radioresistance fault protecting method of Anti-radiation fault-secure type memory device claimed in claim 1, it is characterized in that it is comprised of following step:

Step 1: reinforce as required the data width N of storer, the Hamming code that the EG-LDPC code that selection code word is (n1, k1) and code word are (n2, k2); Wherein n1 and k1 are respectively code length and the data width of EG-LDPC code, and n2 and k2 are respectively code length and the data width of Hamming code;

Step 2: the EG-LDPC code that the code length that step 1 is selected is n1 is divided into M part, and the value of M equates with the code length n2 of Hamming code, at least 2 of the length of the every part in a described M part;

Step 3: the Hamming code that is n2 code length is inserted in the interval of M the part that EG-LDPC code cuts apart equably, and each byte of Hamming code is separated in physical layout; If the code length of Hamming code and EG-LDPC code and information bit meet equation 1 and 2, forming a data width is N, the hybrid code that code length is n1+n2;

$\frac{n1}{n2}\&GreaterEqual;2$ Inequality 1

K1+k2=N equation 2

Step 4: the emergency protection characteristic of guaranteeing hybrid code by emergency protection bounding algorithm; If the minor increment that J is bug patch code, the weight that e is error pattern, the check matrix to system form

$H_{\mathrm{systematic}}=\left[\begin{array}{cccccccccccccccccccccc}1& 0& 0& 0& 0& 0& 1& 0& 0& 1& 1& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0& 0\\ 0& 1& 0& 0& 0& 0& 0& 0& 1& 1& 1& 1& 1& 0& 1& 0& 0& 0& 1& 0& 1& 0\\ 0& 0& 1& 0& 0& 0& 1& 1& 1& 0& 1& 1& 1& 0& 0& 1& 1& 0& 0& 0& 0& 0\\ 0& 0& 0& 1& 0& 0& 1& 1& 1& 0& 0& 0& 0& 1& 1& 1& 0& 1& 0& 0& 0& 1\\ 0& 0& 0& 0& 1& 0& 0& 0& 0& 1& 0& 0& 1& 1& 1& 1& 0& 0& 0& 1& 1& 1\\ 0& 0& 0& 0& 0& 1& 0& 1& 0& 0& 0& 1& 0& 0& 0& 0& 1& 1& 1& 1& 1& 1\end{array}\right]$

Carry out row elementary transformation, obtain having the check matrix H of emergency protection ability _fS;

$H_{\mathrm{FS}}=\left[\begin{array}{cccccccccccccccccccccc}0& 0& 0& 1& 0& 1& 1& 0& 1& 0& 0& 1& 0& 1& 1& 1& 1& 0& 1& 1& 1& 0\\ 0& 1& 1& 1& 1& 1& 0& 1& 1& 0& 0& 1& 1& 0& 1& 1& 0& 0& 0& 0& 1& 1\\ 1& 1& 0& 0& 1& 0& 1& 0& 1& 1& 0& 1& 0& 0& 0& 1& 1& 1& 0& 0& 0& 1\\ 1& 1& 1& 0& 1& 1& 0& 0& 0& 1& 1& 1& 1& 0& 0& 0& 1& 0& 1& 1& 1& 0\\ 1& 1& 1& 0& 0& 0& 0& 1& 0& 0& 1& 0& 0& 1& 1& 1& 0& 1& 0& 1& 1& 0\\ 0& 1& 0& 1& 0& 0& 1& 1& 0& 1& 1& 1& 1& 1& 0& 1& 0& 1& 1& 0& 1& 1\end{array}\right]$

The described check matrix H with emergency protection ability _fSmeet following condition:

In a, each row, at least comprise J individual 1;

B, emergency protection check matrix H _fSin total number Z of 1 remain between " (J+1) * matrix columns>=Z>=J * matrix columns ";

C, emergency protection check matrix H _fSin in every a line 1 number all equate;

Step 5: the Hamming check matrix H of utilizing EG-LDPC code check matrix and step 4 to obtain _fS, by carrying out with the data bit receiving and send scrambler, code translator and the detector that corresponding vector-matrix multiplication obtains hybrid code; The scrambler of described hybrid code, code translator and detector connect and compose Anti-radiation fault-secure type memory device.

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