CN102339646B - Discontinuous type layer identification number detector and method for three-dimensional chip - Google Patents

Abstract

The invention relates to a discontinuous layer identification number detector of a three-dimensional chip and a method thereof. The detector is a three-dimensional chip detector for each layer of an N-layer stack assembly, comprising: a divide-by-two circuit coupled to an (N-1) signal; a first comparator coupled to the first and second circuits, wherein an input A is coupled to an initial layer number signal, and an input B of the first comparator is coupled to an output of the first and second circuits; a second comparator coupled to the initial layer number by an input A of the second comparator, a num coupled to an input B of the second comparator; a first adder-subtractor circuit, coupled to num via an input A of the first adder-subtractor circuit, coupled to the first comparator via an input B of the first adder-subtractor circuit, and coupled to the second comparator via an input "+/-" signal of the first adder-subtractor circuit; and a second adder-subtractor, coupled to the first comparator via an input A of the second adder-subtractor, and coupled to num via an input B of the second adder-subtractor.

Description

Discontinuous type layer identification number detector and method for three-dimensional chip

technical field

The present invention relates to a three-dimensional stacked chip assembly, in particular to a discontinuous type layer identification number detector of a three-dimensional chip.

Background technique

Incoming portable electronic devices, such as mobile phones and non-volatile semiconductor memory media (such as integrated circuit memory cards), have been designed or manufactured in reduced size, and the increased demand is to reduce the number of parts used in devices and media and Reduce its size. Therefore, in the semiconductor industry, packaging technology for integrated circuits has evolved to meet the demands of miniaturization and subsequent reliability. For example, the demand for miniaturization has led to the accelerated development of packaging technology to have a similar size to a semiconductor chip. Furthermore, the importance of follow-up reliability in packaging technology is that it can improve the efficiency of the follow-up process and improve the mechanical and electrical reliability after the follow-up process is completed. Accordingly, considerable work has been devoted to developing efficient packaging of semiconductor chips. Packages that meet the above requirements include: Chip Scale Packages (CSPs) that have a package size approximately equal to a semiconductor chip, multiple chip packages that have multiple semiconductor chips incorporated into a single package, and multiple packages that are stacked and bonded in a single chip. Stack package.

With the development of technology, in response to the increase of memory and its associated required storage capacity, a stacked semiconductor module (multi-chip module) is proposed, which has semiconductor integrated circuit chips stacked together. In other words, it provides a stacked type semiconductor device formed by stacking at least two semiconductor integrated circuit devices, each of which has specifications and includes a semiconductor integrated circuit chip, wherein each semiconductor integrated circuit device includes a conductor passing therethrough, and the semiconductor The integrated circuit components are electrically connected by conductors, and the above specifications include the largest or smallest size of the uppermost or lowermost semiconductor integrated circuit components. Therefore, the stacked semiconductor device has a plurality of chips stacked in a vertical direction. In a stacked semiconductor device, chips are electrically connected together through, for example, plugs passing through the chips. Therefore, it is an important task to select an appropriate stack memory chip with the same structure. When a stacked type semiconductor device is manufactured, the chips can be individually operated and tested so that only normal chips can be picked out and stacked.

One technology that provides vertical connections is called through-silicon vias (TSVs), which has emerged as a promising solution for 3D stacked components. In the above technology, the vertical connection lines are formed through the wafer, so that the stacked chips can communicate with each other. A related paper can refer to the title "8 Gigabit 3D DDR3 Dynamic Random Access Memory Using Through-Silicon Hole Technology" (IEEE, JOURNAL OF SOLID-STATE CIRCUITS, VOL.45, NO.1, JANUARY2010). In this paper, a 3D DRAM with TSVs is proposed to overcome the limitations of the traditional modular approach. It also discloses how to design the structure and data paths. It also discloses a TSV connectivity inspection and repair method including a three-dimensional technology, and a power noise reduction method. TSVs can be formed after the factory in a simple way, so no special process integration is required during the normal process. Chip identification is usually assigned.

After the same or different chips are stacked to form a three-dimensional chip, in order to select a desired chip to operate among the multiple chips of the three-dimensional integrated circuit component, when the system is operating, each chip of the three-dimensional integrated circuit component must confirm its layer identification number Operate by selecting the specified chip. Many methods for confirming layer identification numbers have been proposed in the past, but they not only increase the cost, but also fail to overcome the problem of more electrodes in more stacked chips of three-dimensional integrated circuit components. For example, the US 20070126105 patent applied by Elpida Memory Corporation discloses a stacked semiconductor memory component and a chip selection circuit. It provides a stacked semiconductor memory component. When a desired semiconductor chip is selected among multiple stacked semiconductor chips, a plurality of chip identification numbers different from each other can be automatically generated by a plurality of operating circuits connected in series. , and a desired semiconductor chip can be surely selected by assigning a unique identification number to each semiconductor chip, which utilizes that the semiconductor chips have the same structure without utilizing complicated structures or special controls. In the conventional technology, the calculation output of one of the last incremental circuits among M serially connected incremental circuits can be used to determine the number M of semiconductor chips. According to this, when the number of stacked semiconductor components is unknown, the correct number of semiconductor chips can be surely confirmed. A further prior art is US Patent No. 7,494,846 disclosed by Taiwan Semiconductor Manufacturing Company and filed on March 9, 2007. Its disclosure includes a first semiconductor die and a second semiconductor die identical to the first semiconductor die. The first semiconductor die includes a first identification circuit and a first plurality of input/output pads formed on the surface of the first semiconductor die. The second semiconductor die includes a second identification circuit, wherein the programming of the first identification circuit and the second identification circuit are different from each other, and a second plurality of input/output pads are formed on the surface of the second semiconductor die. Each of the first plurality of I/O pads is vertically aligned and connected to the corresponding second plurality of I/O pads. The second semiconductor die is vertically aligned and soldered on the first semiconductor die.

The invention provides a novel method for identifying three-dimensional integrated circuits.

Contents of the invention

One aspect of the present invention is to provide a method and structure of a discontinuity type detector for a three-dimensional chip stack assembly.

A three-dimensional chip detector for each layer of an N-layer stacked component, comprising: a divide-by-two circuit coupled to a (N-1) signal; a first comparator coupled to the divide-by-two circuit, one of which inputs A is coupled to an initial layer number signal, an input B of the first comparator is coupled to an output of the divide-by-two circuit; a second comparator is coupled to the initial layer number through an input A of the second comparator, and a num is coupled to an input B of the second comparator; a first addition and subtraction circuit is coupled to num through an input A of the first addition and subtraction circuit, and is coupled to the first addition and subtraction circuit through an input B of the first addition and subtraction circuit A comparator, coupled to the second comparator through one of the input "+/-" signals of the first addition and subtraction circuit; and a second addition and subtraction circuit, coupled to the input A of the second addition and subtraction circuit connected to the first comparator, and coupled to num through one input B of the second addition and subtraction circuit.

The output A of the first comparator is equal to the output B of the first comparator, and the output of one of the first comparators is 0; the output A of the first comparator is not equal to the output B of the first comparator, and one of the first comparators The output is 1.

The detector further includes a one-plus-one circuit coupled between the initial layer number signal and the next layer's initial layer number.

Wherein the output A of the second comparator is not equal to the output B of the second comparator, and one of the outputs of the second comparator is 0. The output A of the second comparator is equal to the output B of the second comparator, and one of the outputs of the first comparator is 1. One of the second addition and subtraction circuits inputs a "+/-" signal, and one of the coupled second comparators outputs a "+/-" signal. Among them, when the input "+/-" signal is 1, one output of the first addition and subtraction circuit is (A+B), and one output of the second addition and subtraction circuit is (A+B); when the input "+/-" signal is 0, the output of one of the first addition and subtraction circuits is (A-B), and the output of one of the second addition and subtraction circuits is (A-B). Finally, the layer identification number is output from the second addition and subtraction circuit.

A method for detecting a layer identification number of a three-dimensional chip in each layer of an N-layer stacked component, comprising: generating an initial layer number by incrementing from 0 to (N-1) by a detector of each layer; Specify a num of each layer by N/2, and then increase from 0 to a quotient and decrement from the quotient to 0 respectively by the detector, and take the quotient as the num of each layer; by detecting assigning "+/-" to each layer by the detector based on num and the initial layer number; and generating a layer identification number to each layer by the detector based on num, the initial layer number and "+/-".

Description of drawings

The above-mentioned components, as well as other features and advantages of the present invention, will be more apparent after reading the content and drawings of the embodiments:

Fig. 1 shows a flowchart of an embodiment of an identification number detector according to the present invention.

Figure 2 shows a functional block diagram of the detector of the present invention.

FIG. 3 shows a functional block diagram of a six-layer stacked device of the present invention.

Description of main component symbols:

100 steps

110 steps

120 steps

130 steps

200 detectors

210 divide by two (frequency) circuit

220 first comparator

230 plus one circuit

240 second comparator

250 The first addition and subtraction circuit

260 Second addition and subtraction circuit

Detailed ways

The present invention will be described in detail below with its preferred embodiments and accompanying drawings. It should be understood that all the preferred embodiments in the present invention are for illustration only, not for limitation. Therefore, except for the preferred embodiment herein, the present invention can also be widely applied in other embodiments. And the present invention is not limited to any embodiment, but should be determined by the appended claims and their equivalents.

As shown in Table 1, the detection layer identification number (layer ID) weaving method includes a first step 100, by adding one circuit for each layer to define each initial layer number from 0 to (N-1) to each One layer, where the stack assembly has N layers of chips. Referring to Table 1, the first row indicates the layer number of each layer. If the stacked assembly has 6 layers of chips, the initial layer numbers 0 to 5 are provided for each layer respectively. Next, in step 110, the detector specifies the order of num, and its rule is to increase from 0 to N/2 (take the quotient, regardless of the remainder), repeat once and then decrease from N/2 to 0. For example, from Table 1, the initial layers are numbered from 0 to 5. Then, N is 5, and the num of each layer is incremented from 0 to N/2, and then decremented from N/2 to 0. The order can be reversed. In other words, the order of increasing 1 is from 0 to 2 (5/2=2+1/2; take the integer 2), and the order of decreasing 1 is from 2 to 0. For the order of num, please refer to the second row of Table 1, where num is 0, 1, 2, 2, 1, 0 respectively.

Table I

Next, in step 120, it is determined whether the initial layer number is equal to num. If the initial layer number is equal to num, the detector assigns addition ("+") to this layer, otherwise assigns subtraction ("-") to this layer. This work can be performed by an add/subdevice, which will be described in FIG. 2 and FIG. 3 . Afterwards, in step 130, the detector 200 redefines the layer identification number according to the sign "+" or "-" by incrementing (or decrementing) even and odd numbers, thereby separating the layer identification numbers into two groups, including one Odd group and an even group, refer to the fourth row of Table 1. In one example, the layer identification numbers are 0, 2, 4, 1, 3, 5. This type of layer identification number is called a discontinuous type layer identification number. Table 2 is another example, where the number of layers is from 0 to 8, and the stacked component has 9 layers of chips. N equals 8, num is incremented from 0 to 4, and then decremented from 4 to 0. As a result, the layer identification numbers are divided into even groups 0, 2, 4, 6, 8 and odd groups 1, 3, 5, 7.

Table II

Figure 2 shows an embodiment of detectors for each layer (N) of the stack. The detector 200 includes a divide-by-two (frequency) circuit 210 coupled to a (N-1) signal. A first comparator 220 is coupled to the divide-by-two circuit 210 through its input B, and its input A is coupled to a layer signal (N−1). When the input A is equal to the input B, the output of the first comparator 220 is 0. Conversely, when the input A is not equal to the input B, the output of the first comparator 220 is 1. The plus-one circuit 230 is coupled between the initial layer number 1 of the current layer and the initial layer number of the next (or previous) layer. By adding one circuit 230, the initial layer number of the next layer will be one more than the current one of the layer.

A second comparator 240 is coupled to the initial layer number through its input A, and a num is coupled to the input B of the second comparator 240 . The function of the second comparator 240 is to determine whether the sign of each corresponding layer is "+" or "-" according to the input of num and the initial layer number. When the input A is not equal to the input B, the output of the second comparator 240 is 0. On the other hand, when the input A is equal to the input B, the output of the second comparator 240 is 1.

Next, a first addition and subtraction circuit (Add/sub circuit) 250 is coupled to num through its input A, coupled to the first comparator 220 through input B, and coupled to Connect to the second comparator 240 . The input “+/−” terminal of the first addition and subtraction circuit 250 is coupled to the output signal of the second comparator 240 . When the input "+/-" is 1, the output of the first addition and subtraction circuit 250 is (A+B). On the contrary, when the input "+/-" is 0, the output of the first addition and subtraction circuit 250 is (A-B). The first addition and subtraction circuit 250 is used to determine (A+B) or (A-B) according to the input of num and the output of the first comparator 220 . In other words, based on the input of num, the first comparator 220 and the second comparator 240 , the addition and subtraction signals can be specified through the first addition and subtraction circuit 250 .

A second addition and subtraction circuit 260 is coupled to the first comparator 220 through the first input A, and coupled to num through the second input B. Moreover, the third input “+/−” of the second adding and subtracting circuit 260 is coupled to the output “+/−” signal of the second comparator 240 . When the input "+/-" is 1, the output of the second addition and subtraction circuit 260 is (A+B). On the contrary, when the input "+/-" is 0, the output of the second addition and subtraction circuit 260 is (A-B). The layer identification number will be output from the second addition and subtraction circuit 260 . In other words, based on the input of the initial layer number, num and the input "+/-" of the second comparator 240, the second addition and subtraction circuit 260 is used to determine the identification number of each corresponding layer.

By using the detector set up in Fig. 2 and the method in Fig. 1, layer identification numbers will thus be defined. Figure 3 shows an example of a stacked component with six layers. The uppermost layer, for example, the initial layer number (N−1) is 5, which will be fed into the divide-by-two circuit 210 and output as 2. It can be found from Table 1 that num is 0, and the initial layer number is also 0. Since the input of A is 2, the input B is 0, and A is not equal to B, the output of the first comparator 220 will be 1. However, since the input of A is equal to the input of B, the output of the second comparator 240 will be 1. Communication wires in each layer can be formed by TSVs.

The input A, input B and input "+/-" of the first addition and subtraction circuit 250 are 0, 1, 1 respectively, so the output of the first addition and subtraction circuit 250 is 1. Similarly, the input A, input B and input "+/-" of the second addition and subtraction circuit 260 are 0, 0, and 1 respectively, so the output of the second addition and subtraction circuit 260 is 0, which is the layer identification of the current layer serial number.

By using the same method, the layer and num of the next layer are 1, and by operating the above method, the output of the second addition and subtraction circuit 260 of the next layer is 2, which is the layer identification number of the next layer. The identification numbers of other layers can be obtained in the same way. Therefore no further details will be given.

An embodiment is an example or example of the invention. References in the specification to "one embodiment," "some embodiments" or "other embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least some of the embodiments, but not Required for all instances. Different statements such as "one embodiment" or "some embodiments" mean that reference to these embodiments is not necessary. It is worth noting that in the foregoing descriptions of specific embodiments of the invention, various features may sometimes be grouped together in a single embodiment, drawing, or description to simplify illustration and to facilitate understanding of one or more different aspects of the invention. understand. However, the method of disclosure should not be used to reflect the scope of the claimed invention, so features of the described examples are added to each claim. Rather, the inventive concepts reflected in the following claims lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims are intended to cover the described embodiments, and each claim is itself considered a separate embodiment of the invention.

Claims (10)

1. A three-dimensional chip detector for each layer of an N-layer stack assembly, characterized in that it comprises: A divide-by-two circuit, coupled to a (N-1) layer number signal; A first comparator, coupled to the divide-by-two circuit, wherein an input A is coupled to an initial layer number signal, and an input B of the first comparator is coupled to an output of the divide-by-two circuit; a second comparator, coupled to the initial layer number signal through an input A of the second comparator, a num coupled to an input B of the second comparator, and the num is a sequence signal; A first addition and subtraction circuit, coupled to the num through an input A of the first addition and subtraction circuit, coupled to the first comparator through an input B of the first addition and subtraction circuit, and through the One of the first addition and subtraction circuits inputs a "+/-" signal and is coupled to the second comparator; and A second addition and subtraction circuit, coupled to the first comparator through an input A of the second addition and subtraction circuit, and coupled to the num through an input B of the second addition and subtraction circuit; Wherein the detector redefines the layer identification numbers by incrementing or decrementing even and odd numbers according to the input "+/-" signal, thereby dividing the layer identification numbers into two groups to form discontinuous type layer identification numbers. 2. The three-dimensional chip detector for each layer of an N-layer stacked component as claimed in claim 1, wherein the input A of the first comparator is equal to the input B of the first comparator, and the second An output of a comparator is 0; the input A of the first comparator is not equal to the input B of the first comparator, and an output of the first comparator is 1. 3. The three-dimensional chip detector for each layer of an N-layer stacked component as claimed in claim 1, further comprising a one-plus-one circuit for coupling the initial layer number signal and the next layer initial layer number signal between. 4. The three-dimensional chip detector for each layer of an N-layer stacked component as claimed in claim 1, wherein the input A of the second comparator is not equal to the input B of the second comparator, the An output of the second comparator is 0; the input A of the second comparator is equal to the input B of the second comparator, and an output of the second comparator is 1. 5. The three-dimensional chip detector for each layer of N-layer stacked components as claimed in claim 1, characterized in that one of the second addition and subtraction circuits inputs a "+/-" signal and is coupled to the second comparator One of them outputs "+/-" signal. 6. The three-dimensional chip detector for each layer of N-layer stacked components as claimed in claim 1, wherein when the input "+/-" signal is 1, one of the outputs of the first addition and subtraction circuit is (A+B), one output of the second addition and subtraction circuit is (A+B); when the input "+/-" signal is 0, one output of the first addition and subtraction circuit is (A-B), the first addition and subtraction circuit One of the outputs of the two addition and subtraction circuits is (A-B); one of the layers of identification numbers is output from the second addition and subtraction circuit. 7. A method for detecting the layer identification number of each layer of an N-layer stack assembly, characterized in that it comprises: generating an initial layer number by incrementing one detector of each layer from 0 to (N-1); Designate a num of each layer by N/2, then increment from 0 to a quotient and decrement from the quotient to 0 by the detector respectively, and take the quotient as the quotient of each layer The num, the quotient is the quotient of N/2; assigning an input "+/-" signal to each layer by the detector based on the num and the initial layer number; and generating a layer identification number at each layer by the detector based on the num, the initial layer number and the input "+/-" signal; Wherein the detector redefines the layer identification numbers by incrementing or decrementing even and odd numbers according to the input "+/-" signal, thereby dividing the layer identification numbers into two groups to form discontinuous type layer identification numbers. 8. The method for detecting the layer identification number of each layer of an N-layer stacked component as claimed in claim 7, wherein the layer identification number of each layer includes an odd group and an even group. 9. The method for detecting the layer identification number of each layer of an N-layer stacked component as claimed in claim 7, wherein the detector comprises: A divide-by-two circuit, coupled to a (N-1) layer number signal; A first comparator, coupled to the divide-by-two circuit, wherein an input A is coupled to an initial layer number signal, and an input B of the first comparator is coupled to an output of the divide-by-two circuit; a second comparator, coupled to the initial layer number signal through an input A of the second comparator, a num coupled to an input B of the second comparator, and the num is a sequence signal; A first addition and subtraction circuit, coupled to the num through an input A of the first addition and subtraction circuit, coupled to the first comparator through an input B of the first addition and subtraction circuit, and through the One of the first addition and subtraction circuits inputs a "+/-" signal and is coupled to the second comparator; and A second addition and subtraction circuit, coupled to the first comparator through an input A of the second addition and subtraction circuit, and coupled to the num through an input B of the second addition and subtraction circuit. 10. The method for detecting the layer identification number of each layer of an N-layer stacked component as claimed in claim 7, wherein the input "+/-" signal of each layer is detected by the second comparator Determine, the layer identification number of each layer is determined by the second addition and subtraction circuit.