CN102332428A - Method for manufacturing damascene structure - Google Patents
Method for manufacturing damascene structure Download PDFInfo
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- CN102332428A CN102332428A CN201110328098A CN201110328098A CN102332428A CN 102332428 A CN102332428 A CN 102332428A CN 201110328098 A CN201110328098 A CN 201110328098A CN 201110328098 A CN201110328098 A CN 201110328098A CN 102332428 A CN102332428 A CN 102332428A
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- Prior art keywords
- dielectric layer
- redundant
- hard mask
- layer
- metallic channel
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 62
- 239000002184 metal Substances 0.000 claims abstract description 62
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000126 substance Substances 0.000 claims abstract description 8
- 239000004020 conductor Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000003701 mechanical milling Methods 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical group [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 230000008878 coupling Effects 0.000 abstract description 9
- 238000010168 coupling process Methods 0.000 abstract description 9
- 238000005859 coupling reaction Methods 0.000 abstract description 9
- 238000007517 polishing process Methods 0.000 abstract 1
- 238000010276 construction Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a method for manufacturing a damascene structure, which comprises the following steps of: forming a first dielectric layer on a semiconductor substrate; forming a metal conducting wire groove and a redundant metal groove in the first dielectric layer, wherein the metal conducting wire groove is exposed out of the semiconductor substrate; forming metal layers in the metal conducting wire groove and the redundant metal groove and on the first dielectric layer; removing the metal layer on the first dielectric layer by a chemical mechanical polishing process, and forming a metal conducting wire in the metal conducting wire groove and a redundant metal wire in the redundant metal groove; forming a graphical hard mask layer on the first dielectric layer, wherein the graphical hard mask layer is exposed out of the redundant metal wire; etching to remove the redundant metal wire by using the graphical hard mask layer as a mask so as to expose the redundant metal groove; and filling a second dielectric layer in the redundant metal groove from which the redundant metal wire is removed. By the method for manufacturing the damascene structure, coupling capacitance between the redundant metal wire and the redundant metal wire, and between the redundant metal wire and the metal conducting wire can be removed.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of damascene structure manufacture method.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled.Enter into after 130 nm technology node, receive the restriction of the high-ohmic of aluminium, copper-connection substitution of Al interconnection gradually becomes metal interconnected main flow.Because the dry etch process of copper is difficult for realizing that the manufacture method of copper conductor can not obtain through etching sheet metal as aluminum conductor.The manufacture method of the copper conductor that extensively adopts now is the embedding technique of Damascus technics.This technology comprises the single Damascus technics of only making plain conductor and the dual damascene process of making contact hole and plain conductor simultaneously.
Particularly, this Damascus technics comprises the steps:
At first, on Semiconductor substrate 100, form first dielectric layer 110, please refer to Figure 1A;
Secondly, in said first dielectric layer 110, form metallic channel 111 and redundant metallic channel 112, said metallic channel 111 exposes said Semiconductor substrate 100, please refer to Figure 1B;
Once more, form metal level 120 in said metallic channel 111 and redundant metallic channel 112 and on first dielectric layer 110, please refer to Fig. 1 C;
At last, remove the metal level 120 on said first dielectric layer 110,, and in said redundant metallic channel 112, form redundant metal wire 122, please refer to Fig. 1 D with formation plain conductor 121 in said metallic channel 111 through chemical mechanical milling tech.
Wherein, Redundant metallic channel 112 and interior redundant metal wire 122 thereof design for the needs of chemical mechanical milling tech; Because the rate that removes of metal and dielectric layer material is generally inequality; Therefore can cause depression and the erosion do not expected to the selectivity of cmp; Depression occurs in metal often and goes down to the plane of contiguous dielectric layer or exceed more than the plane of contiguous dielectric layer, and corroding then is that the part of dielectric layer is thin excessively, and depression is subject to the structure of figure with erosion and the density of figure influences.Therefore, require the metallic pattern density on the Semiconductor substrate even as far as possible, when forming metallic channel 111, also form redundant metallic channel 112 usually, for this reason so that when cmp, reach uniform grinding effect.122 of redundant metal wires have no effect after carrying out cmp; And; Between redundant metal wire 122 and the redundant metal wire 122 and will produce coupling capacitance between redundant metal wire 122 and the plain conductor 121, and coupling capacitance can have influence on the electric property of plain conductor 121, for example; Coupling capacitance can have influence on the speed that the electric current of plain conductor 121 passes through, thereby influence is with the speed of the chip of plain conductor 121 interconnection.
Summary of the invention
Technical problem to be solved by this invention provides a kind of damascene structure manufacture method, to remove between redundant metal wire and the redundant metal wire and the coupling capacitance between redundant metal wire and the plain conductor.
In order to solve the problems of the technologies described above, technical scheme of the present invention is: a kind of damascene structure manufacture method comprises: on Semiconductor substrate, form first dielectric layer; In said first dielectric layer, form metallic channel and redundant metallic channel, said metallic channel exposes said Semiconductor substrate; In said metallic channel and redundant metallic channel and on first dielectric layer, form metal level; Remove the metal level on said first dielectric layer through chemical mechanical milling tech, in said metallic channel, forming plain conductor, and in said redundant metallic channel, form redundant metal wire; On said first dielectric layer, form patterned hard mask layer, said patterned hard mask layer exposes said redundant metal wire; With said patterned hard mask layer is mask, and etching is removed said redundant metal wire, exposes said redundant metallic channel; In the redundant metallic channel of the said redundant metal wire of said removal, fill second dielectric layer.
Further, in said redundant metallic channel, fill before second dielectric layer, also comprise: remove said patterned hard mask layer.
Further, in said redundant metallic channel, fill after second dielectric layer, also comprise: remove said patterned hard mask layer.
Further, comprise in the step that forms patterned hard mask layer on said first dielectric layer: on said first dielectric layer, form hard mask layer; On said hard mask layer, form patterned photoresist layer; With patterned photoresist layer is mask, and the said hard mask layer of etching forms patterned hard mask layer.
Further, comprise in the step that forms patterned photoresist layer on the said hard mask layer: on said hard mask layer, form photoresist layer, form patterned photoresist layer through exposure and developing process.
Further, the material of said first dielectric layer is a silicon dioxide.
Further, said first dielectric layer is identical with the material of second dielectric layer.
Further, the material of said first dielectric layer and second dielectric layer is inequality.
Further, the material of said hard mask layer is a silicon nitride.
Further, the material of said hard mask layer is a titanium nitride.
Compared with prior art; The advantage of damascene structure manufacture method of the present invention is: after chemical mechanical milling tech, removed redundant metal wire; And fill and same or different second dielectric layer of first dielectric layer in the redundant metallic channel after removing redundant metal wire; Thereby make the big horse scholar structure that adopts the present invention to make just not exist between redundant metal wire and the redundant metal wire and the coupling capacitance that produces between redundant metal wire and the plain conductor; Electric current just can not receive the influence of coupling capacitance through the speed of plain conductor, then adopts the speed of the chip of plain conductor interconnection just can not be affected.
Description of drawings
Figure 1A～1D adopts existing big horse scholar construction manufacturing method to make the cross-sectional view of the corresponding steps of big horse scholar structure;
Fig. 2 is the flow chart of the big horse scholar construction manufacturing method that provides of the embodiment of the invention;
Fig. 3 A～3J is the cross-sectional view that big horse scholar construction manufacturing method that the embodiment of the invention provides is made the corresponding steps of big horse scholar structure.
Embodiment
Below in conjunction with accompanying drawing the present invention is described in detail:
Please refer to Fig. 2, the big horse scholar of the present invention construction manufacturing method may further comprise the steps:
At first, execution in step S201 please refer to Fig. 3 A; On Semiconductor substrate 300, form first dielectric layer 310; Wherein, the material of said first dielectric layer 310 is a silicon dioxide for example, as preferred implementation; It is black diamond (Black Dimond, silicon oxide carbide BD) or the silica of carbon dope that the material of said first dielectric layer adopts brand name;
Then; Execution in step S202 please refer to Fig. 3 B, in said first dielectric layer 310, forms metallic channel 311 and redundant metallic channel 312; Said metallic channel 311 exposes said Semiconductor substrate 310; The degree of depth of said redundant metallic channel 312 can be identical with metallic channel 311, and perhaps, the degree of depth of said redundant metallic channel 312 is less than the degree of depth of metallic channel 311;
Then, execution in step S203 please refer to Fig. 3 C, forms metal level 320 in said metallic channel 311 and redundant metallic channel 312 and on first dielectric layer 310;
Then; Execution in step S204 please refer to Fig. 3 D, removes the metal level 320 on said first dielectric layer 310 through chemical mechanical milling tech; With formation plain conductor 321 in said metallic channel 311, and in said redundant metallic channel 312, form redundant metal wire 322;
Then, execution in step S205 forms patterned hard mask layer 330 on said first dielectric layer 310, and said patterned hard mask layer 330 exposes said redundant metal wire 322; Shown in Fig. 3 E～3H; Step forming patterned hard mask layer 330 on said first dielectric layer 310 comprises: at first on said first dielectric layer 310, form hard mask layer 330 '; The material of said hard mask layer 330 ' for example is silicon nitride or titanium nitride; Go up at said hard mask layer 330 ' then and form photoresist layer 340 '; Forming patterned photoresist layer 340 through exposure and developing process subsequently, is that the said hard mask layer 330 ' of mask etching forms patterned hard mask layer 330 with patterned photoresist layer 340 again, and said patterned photoresist layer 340 also is etched away simultaneously;
Then; Execution in step S206 please refer to Fig. 3 I, is mask with said patterned hard mask layer 330; Etching is removed said redundant metal wire 322; Expose said redundant metallic channel 312, because said patterned hard mask layer 330 has covered plain conductor 321, this plain conductor 321 can not be damaged;
Then, execution in step S207 please refer to Fig. 3 J; In redundant metallic channel 312, fill second dielectric layer 350, preferable, second dielectric layer 350 is identical with the material of first dielectric layer 310; For example be the silica of non-doped silica or carbon dope, in addition, the material of said second dielectric layer 350 and first dielectric layer 310 also can be inequality; For example first dielectric layer 310 is non-doped silica, and second dielectric layer 350 is the silica of carbon dope.
In this example, in said redundant metallic channel 312, fill before second dielectric layer 350, remove said patterned hard mask layer 330 earlier.Yet will be appreciated that, also can in said redundant metallic channel 312, fill after second dielectric layer 350, remove said patterned hard mask layer 330 again.
Compared with prior art; The advantage of damascene structure manufacture method of the present invention is: after chemical mechanical milling tech, removed redundant metal wire 322; And fill and first dielectric layer, 310 same or different second dielectric layers 350 in the redundant metallic channel 312 after removing redundant metal wire 322; Thereby make the coupling capacitance of big horse scholar structure that adopts the present invention to make with regard to not existing between redundant metal wire 322 and the redundant metal wire 322 and producing between redundant metal wire 322 and the plain conductor 321; Electric current just can not receive the influence of coupling capacitance through the speed of plain conductor, then adopts the speed of the chip of plain conductor interconnection just can not be affected.
Claims (10)
1. a damascene structure manufacture method is characterized in that, may further comprise the steps:
On Semiconductor substrate, form first dielectric layer;
In said first dielectric layer, form metallic channel and redundant metallic channel, said metallic channel exposes said Semiconductor substrate;
In said metallic channel and redundant metallic channel and on first dielectric layer, form metal level;
Remove the metal level on said first dielectric layer through chemical mechanical milling tech, in said metallic channel, forming plain conductor, and in said redundant metallic channel, form redundant metal wire;
On said first dielectric layer, form patterned hard mask layer, said patterned hard mask layer exposes said redundant metal wire;
With said patterned hard mask layer is mask, and etching is removed said redundant metal wire, exposes said redundant metallic channel;
In the redundant metallic channel of the said redundant metal wire of said removal, fill second dielectric layer.
2. damascene structure manufacture method according to claim 1 is characterized in that, in said redundant metallic channel, fills before second dielectric layer, also comprises: remove said patterned hard mask layer.
3. damascene structure manufacture method according to claim 1 is characterized in that, in said redundant metallic channel, fills after second dielectric layer, also comprises: remove said patterned hard mask layer.
4. damascene structure manufacture method according to claim 1 is characterized in that, the step that on said first dielectric layer, forms patterned hard mask layer comprises:
On said first dielectric layer, form hard mask layer;
On said hard mask layer, form patterned photoresist layer;
With patterned photoresist layer is mask, and the said hard mask layer of etching forms patterned hard mask layer.
5. damascene structure manufacture method according to claim 4 is characterized in that, the step that on said hard mask layer, forms patterned photoresist layer comprises:
On said hard mask layer, form photoresist layer, form patterned photoresist layer through exposure and developing process.
6. damascene structure manufacture method according to claim 1 is characterized in that: the material of said first dielectric layer is a silicon dioxide.
7. according to any described damascene structure manufacture method in the claim 1 to 5, it is characterized in that said first dielectric layer is identical with the material of second dielectric layer.
8. according to any described damascene structure manufacture method in the claim 1 to 5, it is characterized in that the material of said first dielectric layer and second dielectric layer is inequality.
9. damascene structure manufacture method according to claim 1 is characterized in that: the material of said hard mask layer is a silicon nitride.
10. damascene structure manufacture method according to claim 1 is characterized in that: the material of said hard mask layer is a titanium nitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110328098A CN102332428A (en) | 2011-10-25 | 2011-10-25 | Method for manufacturing damascene structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110328098A CN102332428A (en) | 2011-10-25 | 2011-10-25 | Method for manufacturing damascene structure |
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| CN102332428A true CN102332428A (en) | 2012-01-25 |
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| CN201110328098A Pending CN102332428A (en) | 2011-10-25 | 2011-10-25 | Method for manufacturing damascene structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332429A (en) * | 2011-10-25 | 2012-01-25 | 上海华力微电子有限公司 | Method for manufacturing damascene structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849549B1 (en) * | 2003-12-04 | 2005-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming dummy structures for improved CMP and reduced capacitance |
| US20080102622A1 (en) * | 2006-10-31 | 2008-05-01 | Hynix Semiconductor Inc. | Method of forming metal line in semiconductor device |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
| US20100261095A1 (en) * | 2009-04-08 | 2010-10-14 | International Business Machines Corporation | Methods, Photomasks and Methods of Fabricating Photomasks for Improving Damascene Wire Uniformity Without Reducing Performance |
| CN102201365A (en) * | 2010-03-22 | 2011-09-28 | 中芯国际集成电路制造(上海)有限公司 | Method for producing semiconductor device |
-
2011
- 2011-10-25 CN CN201110328098A patent/CN102332428A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6849549B1 (en) * | 2003-12-04 | 2005-02-01 | Taiwan Semiconductor Manufacturing Co., Ltd | Method for forming dummy structures for improved CMP and reduced capacitance |
| US20080102622A1 (en) * | 2006-10-31 | 2008-05-01 | Hynix Semiconductor Inc. | Method of forming metal line in semiconductor device |
| US20090121353A1 (en) * | 2007-11-13 | 2009-05-14 | Ramappa Deepak A | Dual damascene beol integration without dummy fill structures to reduce parasitic capacitance |
| US20100261095A1 (en) * | 2009-04-08 | 2010-10-14 | International Business Machines Corporation | Methods, Photomasks and Methods of Fabricating Photomasks for Improving Damascene Wire Uniformity Without Reducing Performance |
| CN102201365A (en) * | 2010-03-22 | 2011-09-28 | 中芯国际集成电路制造(上海)有限公司 | Method for producing semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102332429A (en) * | 2011-10-25 | 2012-01-25 | 上海华力微电子有限公司 | Method for manufacturing damascene structure |
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Application publication date: 20120125 |