CN102332920A

CN102332920A - A High SFDR Multi-Channel Time-Interleaved Successive Approximation Analog-to-Digital Converter

Info

Publication number: CN102332920A
Application number: CN201110200434A
Authority: CN
Inventors: 许俊; 林涛; 王明硕; 顾尉如; 任俊彦; 叶凡; 李宁
Original assignee: Fudan University
Current assignee: Fudan University
Priority date: 2011-07-18
Filing date: 2011-07-18
Publication date: 2012-01-25

Abstract

The invention belongs to the technical field of integrated circuits, in particular to a high SFDR multi-channel time-interleaved successive approximation analog-to-digital converter. The capacitor arrays used for sampling and quantizing the front-end of each channel of the traditional multi-channel time-interleaved SARADC are usually independent and fixed. Capacitor Pool". It is randomly assigned to each channel before each sampling, so that the inherent error of each channel will be reduced and randomized. From the perspective of the energy spectrum, the energy of the harmonic component is turned into noise, which is classified into the noise The bottom goes up, thus effectively improving the nonlinearity introduced by the capacitance mismatch.

Description

A kind of high SFDR multichannel time interleaving gradual approaching A/D converter

Technical field

The invention belongs to technical field of integrated circuits, be specifically related to a kind of multichannel gradual approaching A/D converter.

Background technology

Common multichannel gradual approaching A/D converter structural representation is as shown in Figure 1, and is for the ease of analyzing, existing that the equivalent electric circuit of each passage is as shown in Figure 2.The DAC that mainly forms, be that digital control unit, comparator and the switch arrays of core constitute with the shift register by track and hold circuit, reference voltage, capacitor array.Transfer process is as shown in Figure 3 under its normal condition.At first the sampling of digital control logic unit (the SAR Logic among Fig. 2) control sample holding unit is controlled DAC array highest order then and is met V _Ref(shown in Figure 3), output V _Ref/ 2, comparator will be imported V _InCompare with the output of DAC.If input is big, then the highest order electric capacity of DAC meets V _RefConstant, an inferior high position is met V _RefIf Vin is littler than the output of DAC, then highest order meets Gnd, and an inferior high position meets V _RefBy that analogy.Input shown in Figure 3, the digital code of output is 0001111 at last.If electric capacity does not match, then can cause quantizing to make mistakes, the digital code of output has become 000101, sees shown in Figure 4.Therefore when electric capacity does not match, between different passages, introduce different errors, when the coding output module of process integral body (seeing figure one), can influence the whole linearity.

Summary of the invention

The object of the present invention is to provide a kind of nonlinear multichannel time interleaving gradual approaching A/D converter that can effectively improve by the capacitance mismatch introducing.

Multichannel time interleaving gradual approaching A/D converter provided by the invention, its integrated circuit structure keeps module 17, capacitance pool 21, pseudorandom number generator 23, decoder 24 to constitute by switch arrays 4 ~ 9, sampling switch array 13, comparator array 10 ~ 12, clock generating and coding output module 25, digital control module 14 ~ 16, sampling.If the passage of this analog to digital converter is N, be designated as passage one successively, passage two ..., passage N; Then

switch arrays

4,5 are the switch arrays of passage one, and switch arrays 6,7 are the switch arrays of passage two, and

switch arrays

8,9 are the switch arrays of passage N; Comparator 10 is the comparator of passage one; Comparator 11 is the comparator of passage two; Comparator 12 is the comparator of passage N; Digital control module 14 is the digital control module of passage N; Digital control module 15 is the digital control module of passage two; Digital control module 16 is the digital control module of passage one; Each passage is provided with electric capacity 20 at random;

Wherein, Public capacitance pool 21 is made up of the electric capacity that natural capacity 19 flocks together and one group redundant of each passage, before each sampling, produces one group of random number by pseudorandom number generator 23; Control decoder 24 is chosen the capacitor array of one group of electric capacity as sampling next time remaining two groups of electric capacity in the middle of capacitance pool 21; Thereby periodically error randomization, the energy of reduction harmonic wave is realized high SFDR (SFDR); Get over for a long time when port number, the effect of improvement is obvious more.

Among the present invention; When circuit has just begun to sample; Produce the reset signal of the control clock 22 (CLK1) of a pseudorandom number generator, control decoder 24 is assigned to each passage with the electric capacity of 21 li of capacitance pools and gets on, and the function of each sequential and realization constantly is following subsequently:

(1) when first high level of CLK2 ~ CLK5,, only realizes that the sampling of each corresponding passage and conversion get final product by first group of work in the decoder 24.Final data is carried out Unified coding output at clock generating and coding output module 25;

(2) when second high level of CLK2 ~ CLK5; Organize altogether by second group of decoder 24; Except the sampling and conversion that realize each corresponding passage, also realize choosing one group from remaining two groups of electric capacity the inside respectively each time, be used as the capacitor array of sampling next time;

(3) the rest may be inferred, and the function that the function of later CLK2 ~ CLK5 all repeats step 2 li gets final product.

Here, CLK2 is passage 1 sampling clock, and CLK3 is passage 2 sampling clocks, by that analogy.

In the such scheme; The present invention's mismatch electric capacity that each passage of original multichannel gradual approaching A/D converter is intrinsic gathers forms " capacitance pool " 21 together; The own capacitor array that is about to each passage of front end splits into equal module, constitutes " capacitance pool ", sees shown in Figure 5.Before the improvement, all there is intrinsic mismatch between each passage, when traditional multichannel time interleaving type SAR ADC switches, can introduces periodic error between different passages, have a strong impact on the system linearity degree.After the improvement, the intrinsic mismatch electric capacity of all passages has been constituted a capacitance pool, before each sampling; Through pseudorandom number generator 23 (PRG module); Produce one group of random number, the electric capacity with 21 li of capacitance pools is at random distributed to each passage, thereby unborn fixing periodic error has been become noise at random; Analyze from energy spectrum; To eliminate because of the high-frequency harmonic that original periodic nonlinearity erron causes exactly, become white noise at random, and be evenly distributed to make an uproar at the end (nosie floor) and get on.Thereby improve the performance of multichannel gradual approaching A/D converter.

Analog to digital converter of the present invention is the low power consumption folded interpolating analog to digital converter that a seed transducer is shared, and is based on the method for proofreading and correct the imbalance of multichannel gradual approaching A/D converter interchannel capacitor array and designs.

In addition, when many more, the traditional stranded and interchannel mismatches of multichannel time interleaving type SAR ADC of port number, it is serious more that the linearity descends; And the randomization effect of the modified model multichannel time interleaving type SAR ADC structure of the high SFDR that the present invention proposes is better on the contrary; Can be effectively harmonic energy being assigned to the end of making an uproar gets on; Thereby improve the system linearity degree more significantly, well remedied traditional structural deficiency of multichannel time interleaving type SAR ADC.

Description of drawings

Fig. 1 tradition multichannel time interleaving gradual approaching A/D converter structural representation.

The rough schematic view of each passage of Fig. 2 multichannel time interleaving gradual approaching A/D converter.

Transducer work sketch map when Fig. 3 electric capacity matees fully.

Fig. 4 is because the sketch map of error appears in the transducer that capacitance mismatch causes.

The high SFDR multichannel of Fig. 5 time interleaving gradual approaching A/D converter highest order electric capacity improves sketch map.

Fig. 6 pseudorandom number generator sketch map.

Fig. 7 improves back multichannel gradually-appoximant analog-digital converter sequential chart.

Label among the figure: 1 expression multichannel time interleaving gradual approaching A/D converter passage one; 2 expression multichannel time interleaving gradual approaching A/D converter passages two; 3 expression multichannel time interleaving gradual approaching A/D converter passage N; 4, the switch arrays of 5 expression passages one, the switch arrays of 6,7 expression passages two;

8, the switch arrays of 9 expression passage N, the comparator of 10 expression passages one, the comparator of 11 expression passages two; The comparator of 12 expression passage N, 13 expression sampling switch arrays, the digital control module of 14 expression passage N; The digital control module of 15 expression passages two, the digital control module of 16 expression passages one, 17 expression samplings keep module; 18 expressions are as the capacitor array of DAC, and 19 improve the intrinsic mismatch electric capacity of each preceding passage, the electric capacity at random of each passage after 20 improvement; Capacitance pool after 21 improvement, the control clock of 22 pseudorandom number generators, 23 pseudorandom number generators; 24 decoders (constituting) by two groups of decoders, 25 expression clock generating and coding output module.

Embodiment

To combine diagram to further specify the implementation method of circuit below:

Electric capacity 19 by each original passage has been formed capacitance pool module 21 jointly with one group of redundant capacitor array.

Fig. 6 is the concrete implementation method of pseudorandom number generator 23, employing be the method for the linear feedback shift register (LFSR) after improving, have simple in structurely, realize easily and the cycle of random number and the relation of number of registers exponentially growth.Can only increase the cycle period of pseudo random number in the time of necessary through the number that increases each grade shift register.Under the control of clock CLK1 22, choose the output node that needs from PRG 23 the insides, then through a decoder 24, with randomized electric capacity each time be connected to each passage above go, as the capacitor array of sampling each time and quantizing.

Improve the whole SECO in back by 25 controls of the clock & output module in the middle of the figure one, concrete sequential is seen Fig. 7.Wherein CLK1 is the clock cycle that pseudo random number produces and electric capacity distributes, and CLK2 is passage one sampling clock, and CLK3 is passage two sampling clocks, by that analogy.Compare with traditional multichannel gradual approaching A/D converter, increased an extra clock cycle to produce pseudo random number and distribute electric capacity.

For the ease of narration, be example with 4 passages below, the concrete workflow of the improvement structure of this high SFDR is described:

1) at first under the control of clock generating and coding output module 25; CLK1 produces high level; Control pseudorandom number generator 23 produces one group of random number (being equivalent to the initialization of PRG 23 modules), and random number is delivered to decoder 24 the insides; The electric capacity of capacitance pool is assigned randomly to all passages according to the result of decoding gets on, as sampling with quantize the capacitor array of usefulness.

2) as shown in Figure 7 subsequently, under the control of clock generating and coding output module 25, order produces the high level of CLK2, CLK3, CLK4, and control sampling switch array 13 lets passage one, two, three sample and change.

3) as shown in Figure 7; Under the control of clock generating and coding output module 25; CLK5 produces high level, and control channel 4 is sampled and changed, and clock generating and coding output module 25 are accepted the first group of transformation result and the coding of digital control module 16 generations of passage one and exported.Meanwhile, the high level of CLK5 is controlled the capacitor array that decoder is sampled as passage one from one group of capacitor array of capacitor array the inside picked at random of redundant capacitor array and passage one release just next time.

4) clock generating and coding output module 25 control CLK2 produce high level, the capacitor array that the control decoder selects remaining capacitor array the inside and unnecessary capacitor array the inside picked at random capacitor array to sample as passage two at CLK5 next time.Afterwards the cycle the inside step above repeating.

Like this, under clock generating and coding output module 25 were controlled, passage one was changed to passage N successively, and capacitor array each time all produces at random.Output is with traditional the same, after the sampling through N-1 clock cycle (N is a port number) dateout.Adopt very little cost; Overcome traditional multichannel time interleaving type SAR ADC because the intrinsic mismatch of interchannel capacitor array; The remarkable decline of the linearity that causes; And, will significantly improve the SFDR (SFDR) of multichannel time interleaving type SAR ADC along with the change of number of active lanes is many.

Claims

1. A method for correcting the misalignment of capacitor arrays between channels of a multi-channel time-interleaved successive approximation analog-to-digital converter. The overall circuit structure of the analog-to-digital converter includes: a switch array (4~9), a sampling switch array (13), a comparison device array (10~12), clock generation and encoding output module (25), digital control module (14~16), pseudo-random number generator (23), decoder (24); it is characterized in that each channel The inherent capacitances of the capacitors are gathered together and a group of redundant capacitors form a common capacitor pool (21). Before each sampling, a group of random numbers is generated by a pseudo-random number generator (23), and the control decoder (24) is controlled from A group of capacitors is selected from the remaining two groups of capacitors in the capacitor pool (21) as the capacitor array for the next sampling, so as to randomize the original periodic error, reduce the energy of harmonics, and achieve a high spurious-free dynamic range. the

2. A multi-channel time-interleaved successive approximation analog-to-digital converter, characterized in that: its overall circuit structure consists of a switch array (4~9), a sampling switch array (13), a comparator array (10~12), a clock Generation and encoding output module (25), digital control module (14~16), sample and hold module 17, capacitor pool (21), pseudo-random number generator (23), decoder (24); There are N channels of the converter, which are sequentially recorded as channel one, channel two, ..., channel N; then the switch array (4, 5) is the switch array of channel one, and the switch array (6, 7) is the switch of channel two array, the switch array (8, 9) is the switch array of channel N; the comparator (10) is the comparator of channel one; the comparator (11) is the comparator of channel two; the comparator (12) is the comparator of channel N The digital control module (14) is the digital control module of channel N; the digital control module (15) is the digital control module of channel two; the digital control module (16) is the digital control module of channel one; each channel is provided with random capacitance(20);

Among them, the common capacitance pool (21) is composed of the inherent capacitance (19) of each channel and a set of redundant capacitances. Before each sampling, a set of random numbers is generated by the pseudo-random number generator (23). , control the decoder (24) to select a group of capacitors from the remaining two groups of capacitors in the capacitor pool (21) as the capacitor array for the next sampling, so as to randomize the original periodic error, reduce the energy of harmonics, and realize High spurious-free dynamic range.

3. The multi-channel time-interleaved successive approximation analog-to-digital converter according to claim 2, characterized in that: when the analog-to-digital converter circuit just starts sampling, a reset signal of CLK1 (22) is generated to control the decoder (24) Distribute the capacitance in the capacitance pool (21) to each channel, and then the timing and realized functions at each moment are as follows:

(1) At the first high level of CLK2~CLK5, the first group in the decoder (24) works, only the sampling and conversion of each corresponding channel can be realized; the final data is generated in the clock and The encoding output module (25) performs unified encoding output;

(2) At the second high level of CLK2~CLK5, the second group of the decoder (24) is grouped together to realize the sampling and conversion of each corresponding channel, and realize each time from the remaining two groups Select a group of capacitors to be used as the capacitor array for the next sampling;

(3) By analogy, the functions of CLK2~CLK5 can be repeated in step (2) in the future;

Here, CLK1 is the control clock of the pseudo-random number generator, CLK2 is the sampling clock of channel 1, CLK3 is the sampling clock of channel 2, and so on.