CN102354245B

CN102354245B - Band gap voltage reference source

Info

Publication number: CN102354245B
Application number: CN 201110222964
Authority: CN
Inventors: 周泽坤; 王会影; 石跃; 蔡小祥; 鲍小亮; 王易; 明鑫; 张波
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2011-08-05
Filing date: 2011-08-05
Publication date: 2013-06-12
Anticipated expiration: 2031-08-05
Also published as: CN102354245A

Abstract

The invention discloses a band gap voltage reference source. The band gap voltage reference source comprises a biasing circuit, a start circuit and a first-order reference circuit, and is characterized by also comprising a temperature compensation circuit and an error amplifier circuit, wherein the temperature compensation circuit comprises an NPN transistor, a first N-channel metal oxide semiconductor (NMOS) transistor, a fifth resistor, a sixth resistor and a seventh resistor. In the band gap voltage reference source provided by the invention, temperature compensation is realized, namely a reference voltage is obtained by adding a collector current and the drain current of a metal oxide semiconductor (MOS) transistor in a sub-threshold region of a bipolar device into a conventional first-order temperature compensation band gap reference circuit, so that an output reference voltage has a smaller temperature coefficient.

Description

A Bandgap Voltage Reference Source

技术领域technical field

本发明属于电子技术领域，具体涉及一种电压基准源（Voltage Reference）的设计。The invention belongs to the technical field of electronics, and in particular relates to the design of a voltage reference source (Voltage Reference).

背景技术Background technique

电压基准源广泛应用于振荡器、锁相环（PLL，Phase Locked Loop）和数据转换器等各种模拟和数模混合集成电路中，其温度系数（TC，Temperature Coefficient）和电源抑制比（PSRR,Power Supply Rejection Ratio）很大程度上决定了系统性能的优劣。Voltage reference sources are widely used in various analog and digital-analog hybrid integrated circuits such as oscillators, phase-locked loops (PLL, Phase Locked Loop) and data converters. Their temperature coefficient (TC, Temperature Coefficient) and power supply rejection ratio (PSRR) ,Power Supply Rejection Ratio) largely determines the pros and cons of system performance.

传统的基于V_BE和热电压V_T相互补偿的带隙电压基准源应用较广泛，如图1所示，由于误差放大器的钳位作用，使得V_X与V_Y两点的电压基本相等，即V_X=V_Y=V_BE2，同时，两边电路中的电流也相等，则有： $I_{X} = I_{Y} = \frac{V_{BE 2} - V_{BE 1}}{R_{1}} = \frac{V_{T} \ln N}{R_{1}} .$ The traditional bandgap voltage reference based on mutual compensation of V _BE and thermal voltage V _T is widely used. As shown in Figure 1, due to the clamping effect of the error amplifier, the voltages of V _X and V _Y are basically equal, that is, V _X =V _Y =V _BE2 , at the same time, the currents in the circuits on both sides are also equal, then: $I_{x} = I_{Y} = \frac{V_{BE 2} - V_{BE 1}}{R_{1}} = \frac{V_{T} \ln N}{R} .$

由于则电流为正比于绝对温度（PTAT，Proporational To Absolute Temperature）电流，此电流经过电流镜的镜像以后，便成为整个芯片的偏置电流。because Then the current is proportional to the absolute temperature (PTAT, Proporational To Absolute Temperature) current, after this current is mirrored by the current mirror, it becomes the bias current of the entire chip.

根据电流的表达式，可以得出带隙电压的表达式为：

According to the expression of the current, the expression of the bandgap voltage can be obtained as:

由于V_T为正温度系数，同时V_BE2为负温度系数，合理的调节系数

N的大小，便可以在一定温度下实现基准随温度的变化为零，从而为整个芯片提供了一个随温度变化很小的基准参考电压。Since V _T is a positive temperature coefficient and V _BE2 is a negative temperature coefficient, a reasonable adjustment coefficient

The size of N can realize zero variation of the reference with temperature at a certain temperature, thus providing a reference voltage with little change with temperature for the whole chip.

然而由于V_BE的非线性，只进行一阶补偿，电压基准源的温度系数较大。However, due to the nonlinearity of V _BE , only first-order compensation is performed, and the temperature coefficient of the voltage reference source is relatively large.

发明内容Contents of the invention

本发明的目的是为了解决现有的一阶补偿带隙电压基准源存在的问题，提出了一种带隙电压基准源。The object of the present invention is to solve the problems existing in the existing first-order compensation bandgap voltage reference source, and propose a bandgap voltage reference source.

本发明的技术方案是：一种带隙电压基准源包括：包括：偏置电路、启动电路和一阶基准电路，其特征在于，还包括，温度补偿电路和误差放大器电路，其中，所述的偏置电路为所述的带隙电压基准源提供偏置电压，所述的启动电路用于使一阶基准电路正常工作，所述一阶基准电路产生低温度系数的基准电压，所述的温度补偿电路用于对一阶基准电路进行温度补偿，所述误差放大器电路用于稳定一阶基准电路的工作点；The technical solution of the present invention is: a bandgap voltage reference source includes: including: a bias circuit, a start-up circuit and a first-order reference circuit, and it is characterized in that it also includes a temperature compensation circuit and an error amplifier circuit, wherein the The bias circuit provides a bias voltage for the bandgap voltage reference source, the start-up circuit is used to make the first-order reference circuit work normally, the first-order reference circuit generates a reference voltage with a low temperature coefficient, and the temperature The compensation circuit is used for temperature compensation of the first-order reference circuit, and the error amplifier circuit is used for stabilizing the operating point of the first-order reference circuit;

所述一阶基准电路包括第一NPN管、第二NPN管、第一PMOS管、第二PMOS管、第一电阻、第二电阻、第三电阻和第四电阻；The first-order reference circuit includes a first NPN transistor, a second NPN transistor, a first PMOS transistor, a second PMOS transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor;

所述的温度补偿电路包括第三NPN管、第一NMOS管、第五电阻、第六电阻和第七电阻；The temperature compensation circuit includes a third NPN transistor, a first NMOS transistor, a fifth resistor, a sixth resistor, and a seventh resistor;

所述的启动电路包括第四NPN管、第五NPN管、第六NPN管、第三PMOS管、第四PMOS管、第八电阻、第九电阻和第十电阻；The startup circuit includes a fourth NPN transistor, a fifth NPN transistor, a sixth NPN transistor, a third PMOS transistor, a fourth PMOS transistor, an eighth resistor, a ninth resistor, and a tenth resistor;

具体连接关系如下：The specific connection relationship is as follows:

第一NPN管的基极与第二NPN管的基极、所述启动电路的第四NPN管的发射极相连，同时作为基准输出电压，第一NPN管和第二NPN管的集电极分别与第一电阻和第二电阻的一端相连，同时第一NPN管和第二NPN管的集电极分别与误差放大器电路的负向输入端和正向输入端相连，第一电阻和第二电阻的另一端与第二PMOS管的漏极相连，第二PMOS管的源极与外部电源相连，栅极与所述启动电路的第四PMOS管的栅极相连，第一PMOS管的源极与第二PMOS管的漏极相连，栅极连接于所述启动电路的第八电阻和第九电阻的之间，漏极与地相连，第一NPN管的发射极与第三电阻的一端相连，第三电阻的另一端通过第四电阻接地；The base of the first NPN transistor is connected to the base of the second NPN transistor and the emitter of the fourth NPN transistor of the startup circuit, and simultaneously serves as a reference output voltage, and the collectors of the first NPN transistor and the second NPN transistor are respectively connected to The first resistor is connected to one end of the second resistor, and the collectors of the first NPN transistor and the second NPN transistor are respectively connected to the negative input terminal and the positive input terminal of the error amplifier circuit, and the other end of the first resistor and the second resistor It is connected to the drain of the second PMOS transistor, the source of the second PMOS transistor is connected to the external power supply, the gate is connected to the gate of the fourth PMOS transistor of the startup circuit, and the source of the first PMOS transistor is connected to the second PMOS transistor. The drain of the tube is connected, the gate is connected between the eighth resistor and the ninth resistor of the startup circuit, the drain is connected to the ground, the emitter of the first NPN tube is connected to one end of the third resistor, and the third resistor The other end of the ground through the fourth resistance;

第五电阻、第六电阻和第七电阻顺次相连于一阶基准电路中第一NPN管与第二NPN管的基极与地之间，第三NPN管的集电极与一阶基准电路中第二NPN管集电极相连，第三NPN管的基极与第六电阻和第七电阻有共同连接的那一端相连；第一NMOS管的漏极与第三NPN管QN6的集电极相连，栅极与第五电阻和第六电阻有共同连接的那一端相连，第三NPN管的发射极和第一NMOS管的源极相连，并与一阶基准电路中的第三电阻和第四电阻有共同连接的那一端相连；The fifth resistor, the sixth resistor and the seventh resistor are connected in sequence between the bases of the first NPN transistor and the second NPN transistor in the first-order reference circuit and the ground, and the collector of the third NPN transistor is connected to the ground in the first-order reference circuit. The collector of the second NPN transistor is connected, the base of the third NPN transistor is connected to the end that is commonly connected to the sixth resistor and the seventh resistor; the drain of the first NMOS transistor is connected to the collector of the third NPN transistor QN6, and the gate The electrode is connected to the end of the common connection between the fifth resistor and the sixth resistor, the emitter of the third NPN transistor is connected to the source of the first NMOS transistor, and is connected to the third resistor and the fourth resistor in the first-order reference circuit. The ends that are commonly connected are connected;

第五NPN管的基极与集电极短接，并与第六NPN管的发射极相连，第五NPN管的发射极与地相连，第六NPN管的基极与集电极短接，并分别连接于第四NPN管的基极和第四PMOS管管的漏极，第四PMOS管的栅极与偏置电路的一个输出端相连，同时连接于一阶基准电路的第二PMOS管的栅极，第八电阻、第九电阻和第十电阻顺次连接于第四NPN管的发射极与地之间，第四NPN管的集电极与第三PMOS管的漏极相连，第三PMOS管的栅极与漏极短接，第三PMOS管和第四PMOS管的源极与外部电源相连。The base of the fifth NPN transistor is short-circuited to the collector and connected to the emitter of the sixth NPN transistor, the emitter of the fifth NPN transistor is connected to the ground, the base of the sixth NPN transistor is short-circuited to the collector, and respectively Connected to the base of the fourth NPN transistor and the drain of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to an output terminal of the bias circuit, and connected to the gate of the second PMOS transistor of the first-order reference circuit The eighth resistor, the ninth resistor and the tenth resistor are sequentially connected between the emitter of the fourth NPN transistor and the ground, the collector of the fourth NPN transistor is connected to the drain of the third PMOS transistor, and the third PMOS transistor The gate of the PMOS transistor is short-circuited to the drain, and the sources of the third PMOS transistor and the fourth PMOS transistor are connected to an external power supply.

本发明的有益效果：本发明的带隙基准电压源通过将双极型器件的集电极电流和亚阈值区的MOS管漏电流加入到传统的一阶温度补偿带隙基准电路中，即通过温度补偿电路中的第三NPN管和第一NMOS管实现温度补偿，得到基准电压，运用这种技术，可以使得输出基准电压具有较小的温度系数。Beneficial effects of the present invention: the bandgap reference voltage source of the present invention adds the collector current of the bipolar device and the MOS tube leakage current in the subthreshold region to the traditional first-order temperature compensation bandgap reference circuit, that is, through the temperature The third NPN transistor and the first NMOS transistor in the compensation circuit implement temperature compensation to obtain a reference voltage. Using this technology, the output reference voltage can have a smaller temperature coefficient.

附图说明Description of drawings

图1为传统的带隙电压基准源结构示意图。Figure 1 is a schematic diagram of the structure of a traditional bandgap voltage reference source.

图2为本发明的带隙电压基准源的电路结构示意图。FIG. 2 is a schematic diagram of the circuit structure of the bandgap voltage reference source of the present invention.

图3为本发明的误差放大器电路结构示意图。FIG. 3 is a schematic structural diagram of the error amplifier circuit of the present invention.

图4为本发明的带隙电压基准源I_{C_QN3}的温度特性和dI_{C_QN3}/dT的温度特性示意图。FIG. 4 is a schematic diagram of the temperature characteristic of the bandgap voltage reference source I _{C_QN3} and the temperature characteristic of dI _{C_QN3} /dT of the present invention.

图5为本发明的带隙电压基准源I_{DS_MN1}的温度特性和dI_{DS_MN1}/dT的温度特性示意图。FIG. 5 is a schematic diagram of the temperature characteristic of the bandgap voltage reference source I _{DS_MN1} and the temperature characteristic of dI _{DS_MN1} /dT of the present invention.

图6为本发明的带隙电压基准源输出电压的温度特性示意图。FIG. 6 is a schematic diagram of the temperature characteristic of the output voltage of the bandgap voltage reference source of the present invention.

图7为本发明的带隙电压基准源的启动时间示意图。FIG. 7 is a schematic diagram of the start-up time of the bandgap voltage reference source of the present invention.

图8为本发明带隙电压基准源的电源抑制比示意图。FIG. 8 is a schematic diagram of the power supply rejection ratio of the bandgap voltage reference source of the present invention.

图9为本发明带隙电压基准源的输出电压与电源电压的关系示意图。FIG. 9 is a schematic diagram of the relationship between the output voltage and the power supply voltage of the bandgap voltage reference source of the present invention.

具体实施方式Detailed ways

下面结合附图和具体的实施例对本发明作进一步的阐述。The present invention will be further elaborated below in conjunction with the accompanying drawings and specific embodiments.

本发明的带隙电压基准源如图2所示，包括：偏置电路、启动电路、一阶基准电路、温度补偿电路和误差放大器电路，其中，所述的偏置电路为所述的带隙电压基准源提供偏置电压，所述的启动电路用于使一阶基准电路正常工作，所述一阶基准电路产生低温度系数的基准电压，所述的温度补偿电路用于对一阶基准电路进行温度补偿，所述误差放大器电路用于稳定一阶基准电路的工作点。The bandgap voltage reference source of the present invention is shown in Figure 2, comprises: bias circuit, start-up circuit, first-order reference circuit, temperature compensation circuit and error amplifier circuit, wherein, described bias circuit is described bandgap The voltage reference source provides a bias voltage, the start-up circuit is used to make the first-order reference circuit work normally, the first-order reference circuit generates a reference voltage with a low temperature coefficient, and the temperature compensation circuit is used to correct the first-order reference circuit For temperature compensation, the error amplifier circuit is used to stabilize the operating point of the first-order reference circuit.

这里，一阶基准电路包括第一NPN管QN1、第二NPN管QN2、第一PMOS管MP1、第二PMOS管MP2、第一电阻R1、第二电阻R2、第三电阻R3和第四电阻R4。Here, the first-order reference circuit includes a first NPN transistor QN1, a second NPN transistor QN2, a first PMOS transistor MP1, a second PMOS transistor MP2, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4 .

这里，温度补偿电路包括第三NPN管QN3、第一NMOS管MN1、第五电阻R5、第六电阻R6和第七电阻R7；Here, the temperature compensation circuit includes a third NPN transistor QN3, a first NMOS transistor MN1, a fifth resistor R5, a sixth resistor R6 and a seventh resistor R7;

这里，启动电路包括第四NPN管QN4、第五NPN管QN5、第六NPN管QN6、第三PMOS管MP3、第四PMOS管MP4、第八电阻R8、第九电阻R9和第十电阻R10；Here, the startup circuit includes a fourth NPN transistor QN4, a fifth NPN transistor QN5, a sixth NPN transistor QN6, a third PMOS transistor MP3, a fourth PMOS transistor MP4, an eighth resistor R8, a ninth resistor R9 and a tenth resistor R10;

具体连接关系如下：The specific connection relationship is as follows:

第一NPN管QN1的基极与第二NPN管QN2的基极、启动电路的第四NPN管QN4的发射极相连，同时作为基准输出电压，第一NPN管QN1和第二NPN管QN2的集电极分别与第一电阻R1和第二电阻R2的一端相连，同时第一NPN管QN1和第二NPN管QN2的集电极分别与误差放大器电路的负向输入端V2和正向输入端V1相连，第一电阻R1和第二电阻R2的另一端与第二PMOS管MP2的漏极相连，第二PMOS管MP2的源极与外部电源相连，栅极与启动电路的第四PMOS管MP4的栅极相连，第一PMOS管MP1的源极与第二PMOS管MP2的漏极相连，栅极连接于启动电路的第八电阻R8和第九电阻R9的之间，漏极与地相连，第一NPN管QN1的发射极与第三电阻R3的一端相连，第三电阻R3的另一端通过第四电阻R4接地；The base of the first NPN transistor QN1 is connected to the base of the second NPN transistor QN2 and the emitter of the fourth NPN transistor QN4 of the starting circuit, and simultaneously serves as a reference output voltage, the set of the first NPN transistor QN1 and the second NPN transistor QN2 The electrodes are respectively connected to one end of the first resistor R1 and the second resistor R2, while the collectors of the first NPN transistor QN1 and the second NPN transistor QN2 are respectively connected to the negative input terminal V2 and the positive input terminal V1 of the error amplifier circuit. The other end of the first resistor R1 and the second resistor R2 are connected to the drain of the second PMOS transistor MP2, the source of the second PMOS transistor MP2 is connected to the external power supply, and the gate is connected to the gate of the fourth PMOS transistor MP4 of the startup circuit , the source of the first PMOS transistor MP1 is connected to the drain of the second PMOS transistor MP2, the gate is connected between the eighth resistor R8 and the ninth resistor R9 of the startup circuit, the drain is connected to the ground, and the first NPN transistor The emitter of QN1 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is grounded through the fourth resistor R4;

第五电阻R5、第六电阻R6和第七电阻R7顺次相连于一阶基准电路中第一NPN管QN1与第二NPN管QN2的基极与地之间，第三NPN管QN3的集电极与一阶基准电路中第二NPN管集电极QN2相连，第三NPN管QN3的基极与第六电阻R6和第七电阻R7有共同连接的那一端相连；第一NMOS管MN1的漏极与第三NPN管QN3的集电极相连，栅极与第五电阻R5和第六电阻R6有共同连接的那一端相连，第三NPN管QN3的发射极和第一NMOS管MN1的源极相连，并与一阶基准电路中的第三电阻R3和第四电阻R4有共同连接的那一端相连；The fifth resistor R5, the sixth resistor R6 and the seventh resistor R7 are sequentially connected between the bases of the first NPN transistor QN1 and the second NPN transistor QN2 and the ground in the first-order reference circuit, and the collector of the third NPN transistor QN3 It is connected to the collector electrode QN2 of the second NPN transistor in the first-order reference circuit, and the base electrode of the third NPN transistor QN3 is connected to the end of the common connection between the sixth resistor R6 and the seventh resistor R7; the drain electrode of the first NMOS transistor MN1 is connected to the The collector of the third NPN transistor QN3 is connected, the gate is connected to the common connection end of the fifth resistor R5 and the sixth resistor R6, the emitter of the third NPN transistor QN3 is connected to the source of the first NMOS transistor MN1, and connected to the end of the common connection between the third resistor R3 and the fourth resistor R4 in the first-order reference circuit;

第五NPN管QN5的基极与集电极短接，并与第六NPN管QN6的发射极相连，第五NPN管QN5的发射极与地相连，第六NPN管QN6的基极与集电极短接，并分别连接于第四NPN管QN4的基极和第四PMOS管MP4的漏极，第四PMOS管MP4的栅极与偏置电路的一个输出端相连，同时连接于一阶基准电路的第二PMOS管MP2的栅极，第八电阻R8、第九电阻R9和第十电阻R9顺次连接于第四NPN管QN4的发射极与地之间，第四NPN管QN4的集电极与第三PMOS管MP3的漏极相连，第三PMOS管MP3的栅极与漏极短接，第三PMOS管MP3和第四PMOS管MP4的源极与外部电源相连。The base of the fifth NPN transistor QN5 is shorted to the collector, and connected to the emitter of the sixth NPN transistor QN6, the emitter of the fifth NPN transistor QN5 is connected to the ground, and the base of the sixth NPN transistor QN6 is shorted to the collector. connected, and respectively connected to the base of the fourth NPN transistor QN4 and the drain of the fourth PMOS transistor MP4, the gate of the fourth PMOS transistor MP4 is connected to an output end of the bias circuit, and is connected to the first-order reference circuit at the same time The gate of the second PMOS transistor MP2, the eighth resistor R8, the ninth resistor R9 and the tenth resistor R9 are sequentially connected between the emitter of the fourth NPN transistor QN4 and the ground, and the collector of the fourth NPN transistor QN4 is connected to the ground of the fourth NPN transistor QN4. The drains of the three PMOS transistors MP3 are connected, the gate and the drain of the third PMOS transistor MP3 are short-circuited, and the sources of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to an external power supply.

启动电路使得一阶基准电路正常工作，产生基准输出电压。启动电路只在电压基准源上电时发挥作用，当电压基准源启动完成以后，启动电路停止工作，避免了启动电路对后面电路的影响。The start-up circuit makes the first-order reference circuit work normally and generates a reference output voltage. The startup circuit only plays a role when the voltage reference source is powered on. After the voltage reference source is started, the startup circuit stops working, which avoids the influence of the startup circuit on the subsequent circuits.

偏置电路包括：NPN管QN8、QN9、QN10、QN11和QN12，PMOS管MP6、MP7、MP8、MP9、MP10和MP0，NMOS管MN2，电阻R11和R12。其中，QN8、QN9、QN10、QN11、QN12和R11用来产生PTAT电流，MP6、MP7、MP8、MP9和MN2用来镜像产生的PTAT电流以此来给其它电路提供偏置电流；MP0为启动管，VBIAS接MP0的栅极作为输入端，MP9和MP10、MP6和MP7、MN2的栅极电压VB1、VB2、VB3作为偏置电路的输出端为误差放大器电路以及启动电路提供偏置电压。The bias circuit includes: NPN transistors QN8, QN9, QN10, QN11 and QN12, PMOS transistors MP6, MP7, MP8, MP9, MP10 and MP0, NMOS transistor MN2, resistors R11 and R12. Among them, QN8, QN9, QN10, QN11, QN12 and R11 are used to generate PTAT current, MP6, MP7, MP8, MP9 and MN2 are used to mirror the generated PTAT current to provide bias current to other circuits; MP0 is the start tube , VBIAS is connected to the gate of MP0 as the input terminal, and the gate voltages VB1, VB2 and VB3 of MP9 and MP10, MP6 and MP7, and MN2 are used as the output terminal of the bias circuit to provide bias voltage for the error amplifier circuit and the start-up circuit.

这里误差放大器电路可以采用如下一种方案，具体如图3所示，包括：NPN管QAN1、QAN2、QAN3、QAN4、QAN5和QAN6，PNP管QAP1和QAP2，PMOS管MAP1、MAP2、MAP3、MAP4、MAP5、MAP6、MAP7和MP5，NMOS管MAN1、MAN2、MAN3和MAN4，电阻RAP1、RAP2、RAP3和RAP4，电容C0。其中，MAP1、MAP3、MAP5和MAP7的源极与电源相连，栅极相连，并连接于偏置电路的VB2点，MAP1、MAP3和MAP5的漏极分别与MAP2、MAP4和MAP6的源极相连，MAP2、MAP4和MAP6的栅极相连，并连接于偏置电路的VB3点，MP7的漏极与MAN4的漏极相连，并作为误差放大器电路的输出端，MAN4的源极与地相连，栅极与MAN3的漏极相连，MAN1、MAN2和MAN3的源极接地，栅极相连，并接于偏置电路的VB1点；QAN1和QAN2的基极为误差放大器电路的输入端，集电极与电源相连，QAN1的发射极与QAP1的基极、MAN1的漏极相连，QAN2的发射极与QAP2的基极、MAN2的漏极相连，QAP1和QAP2的发射极相连，并连接与MAP2的漏极相连，QAP1的集电极（即为SS点）与QAN3的发射极、MP5的漏极相连，MP5的源极与外部电源相连；QAP2的集电极与QAN4的发射极相连，QAN3和QAN4的基极、QAN5的发射极相连，QAN3和QAN4的集电极分别与MAP4和MAP6的漏极相连，QAN5的基极与QAN3的发射极相连，集电极与电源相连，电阻RAP1、RAP2、RAP3分别连接与QAN3、QAN4和QAN5的发射极与地之间，QAN6的基极、发射极与QAN4的集电极、MAN3的漏极相连，电阻RA4和电容C0顺次连接于QAN6的基极和MAN4的漏极之间。Here the error amplifier circuit can adopt the following scheme, as shown in Figure 3, including: NPN transistors QAN1, QAN2, QAN3, QAN4, QAN5 and QAN6, PNP transistors QAP1 and QAP2, PMOS transistors MAP1, MAP2, MAP3, MAP4, MAP5, MAP6, MAP7 and MP5, NMOS transistors MAN1, MAN2, MAN3 and MAN4, resistors RAP1, RAP2, RAP3 and RAP4, capacitor C0. Among them, the sources of MAP1, MAP3, MAP5 and MAP7 are connected to the power supply, the gates are connected, and connected to the VB2 point of the bias circuit, and the drains of MAP1, MAP3 and MAP5 are respectively connected to the sources of MAP2, MAP4 and MAP6, The gates of MAP2, MAP4 and MAP6 are connected and connected to the VB3 point of the bias circuit, the drain of MP7 is connected with the drain of MAN4, and is used as the output terminal of the error amplifier circuit, the source of MAN4 is connected to the ground, and the gate Connected to the drain of MAN3, the sources of MAN1, MAN2 and MAN3 are grounded, the gates are connected, and connected to the VB1 point of the bias circuit; the bases of QAN1 and QAN2 are the input terminals of the error amplifier circuit, and the collectors are connected to the power supply. The emitter of QAN1 is connected to the base of QAP1 and the drain of MAN1, the emitter of QAN2 is connected to the base of QAP2 and the drain of MAN2, the emitters of QAP1 and QAP2 are connected, and connected to the drain of MAP2, QAP1 The collector (that is, SS point) is connected to the emitter of QAN3 and the drain of MP5, and the source of MP5 is connected to the external power supply; the collector of QAP2 is connected to the emitter of QAN4, the bases of QAN3 and QAN4, and the base of QAN5 The emitters are connected, the collectors of QAN3 and QAN4 are connected to the drains of MAP4 and MAP6 respectively, the base of QAN5 is connected to the emitter of QAN3, the collector is connected to the power supply, and the resistors RAP1, RAP2, and RAP3 are respectively connected to QAN3, QAN4 and Between the emitter of QAN5 and the ground, the base and emitter of QAN6 are connected to the collector of QAN4 and the drain of MAN3, and the resistor RA4 and capacitor C0 are sequentially connected between the base of QAN6 and the drain of MAN4.

作为一个较佳的方案，将误差放大器电路中的PMOS管MP5栅极与启动电路的第三PMOS管MP3的栅极相连，这样，在刚刚上电时引入失调电流到误差放大器电路，以此来缩短启动时间。As a better solution, the gate of the PMOS transistor MP5 in the error amplifier circuit is connected to the gate of the third PMOS transistor MP3 of the start-up circuit, so that an offset current is introduced into the error amplifier circuit when the power is just turned on, so that Reduce startup time.

此外还有NPN管QN7、NMOS管MN0和电容C1连接于此带隙电压基准源，其中QN7的集电极接外部电源，基极与误差放大器电路输出端相连，发射极与MN0漏极相连，MN0源极接地，栅极接于误差放大器电路中MAN4的栅极中。C1一端与地相连，另一端接电压基准源的输出。这里，QN7和MN0作为电压基准源的输出缓冲级，C0作为滤波电容。In addition, NPN transistor QN7, NMOS transistor MN0 and capacitor C1 are connected to this bandgap voltage reference source, wherein the collector of QN7 is connected to the external power supply, the base is connected to the output terminal of the error amplifier circuit, the emitter is connected to the drain of MN0, and the MN0 The source is grounded, and the gate is connected to the gate of MAN4 in the error amplifier circuit. One end of C1 is connected to the ground, and the other end is connected to the output of the voltage reference source. Here, QN7 and MN0 are used as the output buffer stage of the voltage reference source, and C0 is used as a filter capacitor.

分别从以下几个方面进行阐述。Elaborate from the following aspects respectively.

1.本发明的电压基准源的整体原理说明：1. The overall principle description of the voltage reference source of the present invention:

不考虑基极电流，误差放大器电路使得V1=V2，因此电压基准源的输出电压V_REF为：Regardless of the base current, the error amplifier circuit makes V1=V2, so the output voltage V _REF of the voltage reference source is:

${V V}_{REF REF} \approx \approx {V V}_{BE BE 22} + + \frac{{22 R R}_{44}}{{R R}_{33}} {V V}_{T T} ln ln N N \frac{{I I}_{C C 11} - - {I I}_{DS DS__MN MN 11} - - {I I}_{C C__QN QN 33}}{{I I}_{C C 11}} + + {I I}_{DS DS__MN MN 11} {R R}_{44} + + {I I}_{C C__QN QN 33} {R R}_{44} - - - - - - ((11))$

其中，N是QN1和QN2的发射极面积之比，V_T为热电压，I_{DS_MN1}是MN2的漏电流，I_{C_QN3}为QN3的发射极电流，同时所有的电阻都是用相同材料实现的。其中BE结电压为：Among them, N is the ratio of the emitter area of QN1 and QN2, V _T is the thermal voltage, I _{DS_MN1} is the leakage current of MN2, I _{C_QN3} is the emitter current of QN3, and all the resistors are realized with the same material. where the BE junction voltage is:

V_BE=V_G0+mV_T-(η-α)V_TlnT （2）V _BE =V _G0 +mV _T -(η-α)V _T lnT (2)

${V V}_{T T} ln ln = = \frac{k k}{q q} [[((T T - - {T T}_{00})) + + \frac{11}{22} {((T T - - {T T}_{00}))}^{22} - - \frac{11}{66} {((T T - - {T T}_{00}))}^{33} + + \frac{11}{1212} {((T T - - {T T}_{00}))}^{44}]] - - - - - - ((33))$

由图2及式（2）、（3）可知，电压基准源的输出电压V_REF为：From Figure 2 and formulas (2) and (3), we can see that the output voltage V _REF of the voltage reference source is:

${V V}_{REF REF} = = {V V}_{G G 00} + + m m {V V}_{T T} - - ((η η - - α α)) {V V}_{T T} ln ln T T + + \frac{{22 R R}_{44}}{{R R}_{33}} + + {V V}_{T T} ln ln N N \frac{{I I}_{C C 11} - - {I I}_{DS DS__MN MN 11} - - {I I}_{C C__QN QN 33}}{{I I}_{C C 11}} + + {I I}_{DS DS__MN MN 11} {R R}_{44} + + {I I}_{C C__QN QN 33} {R R}_{44} - - - - - - ((44))$

这里的m是与温度无关的常数，α为I_C关于温度的表达式中的阶数，R₃、R₄分别为第三电阻R3和第四电阻R4的阻值，V_T为热电压，V_T=kT/q，V_G0是硅在0K时的本征带隙电压，η是一个介于3和4之间的常数，通常情况下为3.45左右。从（3）可知，V_TlnT显示出V_BE的高阶温度非线性项，而一阶温度补偿仅仅抵消温度T的一次项，因此需要进行高阶温度补偿。对（4）求导可得：Here m is a constant that has nothing to do with temperature, α is the order number in the expression of _IC with respect to temperature, R ₃ and R ₄ are the resistance values of the third resistor R3 and the fourth resistor R4 respectively, V _T is the thermal voltage, V _T =kT/q, V _G0 is the intrinsic bandgap voltage of silicon at 0K, and η is a constant between 3 and 4, usually around 3.45. It can be known from (3) that V _T lnT shows a high-order temperature nonlinear term of V _BE , and the first-order temperature compensation only cancels the first-order term of temperature T, so high-order temperature compensation is required. Derivation of (4) can get:

$\frac{&PartialD; &PartialD; {V V}_{REF REF}}{&PartialD; &PartialD; T T} = = m m \frac{k k}{q q} - - ((η η - - α α)) \frac{k k}{q q} ((11 + + ln ln T T)) + + \frac{22 {R R}_{44}}{{R R}_{33}} \frac{k k}{q q} ln ln N N \frac{{I I}_{C C 11} - - {I I}_{DS DS__MN MN 11} - - {I I}_{C C__QN QN 33}}{{I I}_{C C 11}}$

（5）(5)

$+ + \frac{{22 R R}_{44}}{{R R}_{33}} {V V}_{T T} \frac{11}{{I I}_{C C 11} - - {I I}_{DS DS__MN MN 11} - - {I I}_{C C__QN QN 33}} ((- - \frac{&PartialD; &PartialD; {I I}_{DS DS__MN MN 11}}{&PartialD; &PartialD; T T} - - \frac{{&PartialD; &PartialD; I I}_{C C__QN QN 33}}{&PartialD; &PartialD; T T})) + + {R R}_{44} \frac{{&PartialD; &PartialD; I I}_{DS DS__MN MN 11}}{&PartialD; &PartialD; T T} + + {R R}_{44} \frac{{&PartialD; &PartialD; I I}_{C C__QN QN 33}}{&PartialD; &PartialD; T T}$

由于I_{DS_MN1}和I_{C_QN3}远远小于QN1和QN2的集电极电流，因I_C1-I_{DS_MN1}-I_{C_QN3}≈I_C1。所以上式可以近似为：Since I _{DS_MN1} and I _{C_QN3} are much smaller than the collector currents of QN1 and QN2, because I _C1 -I _{DS_MN1} -I _{C_QN3} ≈I _C1 . So the above formula can be approximated as:

$\frac{&PartialD; &PartialD; {V V}_{REF REF}}{&PartialD; &PartialD; T T} = = m m \frac{k k}{q q} - - ((η η - - α α)) \frac{k k}{q q} ((11 + + ln ln T T)) + + \frac{22 {R R}_{44}}{{R R}_{33}} \frac{k k}{q q} ln ln N N - - {R R}_{44} ((\frac{{22 V V}_{T T}}{{R R}_{33} {I I}_{C C 11}} \frac{{&PartialD; &PartialD; I I}_{DS DS__MN MN 11}}{&PartialD; &PartialD; T T} - - 11)) - - {R R}_{44} ((\frac{22 {V V}_{T T}}{{R R}_{33} {I I}_{C C 11}} \frac{&PartialD; &PartialD; {I I}_{DS DS__MN MN 11}}{&PartialD; &PartialD; T T} - - 11)) - - - - - - ((66))$

通过对一阶温度补偿的带隙基准进行温度补偿，即可得到三个极值点，即在T₁，T₂，T₃时的温度系数为零，其中T₁<T₂<T₃,令：By performing temperature compensation on the first-order temperature-compensated bandgap reference, three extreme points can be obtained, that is, the temperature coefficient at T ₁ , T ₂ , and T ₃ is zero, where T ₁ <T ₂ <T ₃ , make:

${f f}_{11} ((T T)) = = m m \frac{k k}{q q} - - ((η η - - α α)) \frac{k k}{q q} ((11 + + ln ln T T)) + + \frac{22 {R R}_{44}}{{R R}_{33}} \frac{k k}{q q} ln ln N N - - - - - - ((77))$

${f f}_{22} ((T T)) = = \frac{{&PartialD; &PartialD; I I}_{DS DS__MN MN 11}}{&PartialD; &PartialD; T T} {R R}_{44} ((\frac{{22 V V}_{T T}}{{R R}_{33} {I I}_{PTAT PTAT}} - - 11)) + + \frac{{&PartialD; &PartialD; I I}_{C C__QN QN 33}}{&PartialD; &PartialD; T T} {R R}_{44} ((\frac{22 {V V}_{T T}}{{R R}_{33} {I I}_{PTAT PTAT}} - - 11)) - - - - - - ((88))$

在T₁和T₃点为零，即为f₁(T₁)=f₂(T₁)，f₁(T₂)=f₂(T₂)，f₁(T₃)=f₂(T₃)，联立以上三个式子，即可得到

（后面将详细介绍）和

来满足上述三个式子。It is zero at T ₁ and T ₃ , that is, f ₁ (T ₁ )=f ₂ (T ₁ ), f ₁ (T ₂ )=f ₂ (T ₂ ), f ₁ (T ₃ )=f ₂ ( T ₃ ), combining the above three formulas, we can get

(more on this later) and

to satisfy the above three formulas.

2.双极性器件集电极电流的温度特性：2. Temperature characteristics of bipolar device collector current:

曲率补偿是通过MN1和QN3来实现的，其中QN3的集电极电流为I_{C_QN3}为：Curvature compensation is realized through MN1 and QN3, where the collector current of QN3 is I _{C_QN3} as:

${I I}_{C C__QN QN 33} = = {I I}_{ES ES 33} [[exp exp ((\frac{q q {V V}_{BE BE 33}}{kT kT})) - - 11]] - - - - - - ((99))$

其中，QN3的基极电压是与V_REF成比例的，是与温度无关的电压，而它的发射极电压是一阶基准电路产生的PTAT电流在电阻上产生的PTAT电压，所以为正温系数的电压，因此V_BE3是与温度成负温系数的电压。Among them, the base voltage of QN3 is proportional to _VREF , which is a temperature-independent voltage, and its emitter voltage is the PTAT voltage generated by the PTAT current generated by the first-order reference circuit on the resistance, so it is a positive temperature coefficient , so V _BE3 is a voltage that has a negative temperature coefficient with temperature.

${I I}_{C C__QN QN 33} = = {I I}_{ES ES 33} [[exp exp ((\frac{q q ((\frac{{R R}_{77}}{{R R}_{55} + + {R R}_{66} + + {R R}_{77}} {V V}_{REF REF} - - {22 I I}_{PTAT PTAT 22} {R R}_{44}))}{kT kT})) - - 11]] - - - - - - ((1010))$

而I_ES3为发射结反偏时的饱和电流，通常为一常数，可以写成：And I _ES3 is the saturation current when the emitter junction is reverse-biased, usually a constant, which can be written as:

${I I}_{ES ES 33} = = {ET ET}^{γ γ} exp exp ((- - \frac{q q {V V}_{G G}}{kT kT})) - - - - - - ((1111))$

其中，E是与温度无关的常数，γ=4-n，而n与基极的掺杂水平相关。由（10）、（11）及图2可得：Among them, E is a temperature-independent constant, γ=4-n, and n is related to the doping level of the base. From (10), (11) and Figure 2, we can get:

${I I}_{C C__QN QN 33} \approx \approx {ET ET}^{γ γ} exp exp [[- - \frac{q q (({V V}_{G G} - - \frac{{R R}_{77}}{{R R}_{55} + + {R R}_{66} + + {R R}_{77}} {V V}_{REF REF} + + {22 I I}_{PTAT PTAT 22} {R R}_{44}))}{kT kT}]] - - - - - - ((1212))$

其中,V_G大约为1.2V， $\frac{R_{7}}{R_{5} + R_{6} + R_{7}} V_{REF} - {2 I}_{PTAT 2} R_{4} < 1.2 V,$ 所以：Among them, V _G is about 1.2V, $\frac{R_{7}}{R_{5} + R_{6} + R_{7}} V_{REF} - {2 I}_{PTAT 2} R_{4} < 1.2 V,$ so:

$V_{G} - \frac{R_{7}}{R_{5} + R_{6} + R_{7}} V_{REF} + {2 I}_{PTAT 2} R_{4} > 0,$ 因此I_{C_QN3}随温度的增加而增加。 $V_{G} - \frac{R_{7}}{R_{5} + R_{6} + R_{7}} V_{REF} + {2 I}_{PTAT 2} R_{4} > 0,$ Therefore _{IC_QN3} increases with temperature.

本发明进行温度补偿所用到的QN3管电流I_{C_QN3}和dI_{C_QN3}/dT的温度特性仿真曲线如图4所示，可以看出在整个温度范围内，温度系数为正，且随温度升高而逐渐增大。The temperature characteristic simulation curves of QN3 tube current I _{C_QN3} and dI _{C_QN3} /dT used for temperature compensation in the present invention are shown in Figure 4, as can be seen in the entire temperature range, the temperature coefficient is positive, and gradually increases with temperature increase.

3.亚阈值区的MOS管漏电流的温度特性：3. The temperature characteristics of the MOS tube leakage current in the sub-threshold region:

MN1工作在弱反型区，MN1的漏电流为：MN1 works in the weak inversion region, and the leakage current of MN1 is:

${I I}_{DS DS__MN MN 11} = = \frac{W W}{L L} μ μ (({T T}_{00})) {((\frac{T T}{{T T}_{00}}))}^{- - n no} {((\frac{kT kT}{q q}))}^{22} {C C}_{D D.} exp exp ((\frac{q q}{kT kT} \frac{{V V}_{GS GS__MN MN} - - {V V}_{TH TH}}{n no})) [[11 - - exp exp ((- - \frac{{qV wxya}_{DS DS__MN MN 11}}{kT kT}))]] - - - - - - ((1313))$

其中，μ_n为电子迁移率，C_D为沟道下的耗尽层电容，并且n=1+C_D/C_OX，C_OX为从栅极到沟道的单位面积的氧化物电容。Wherein, μ _n is the electron mobility, _CD is the depletion layer capacitance under the channel, and n=1+ _CD /C _OX , and C _OX is the oxide capacitance per unit area from the gate to the channel.

当V_{DS_MN1}＞＞kT/q时，式（13）可以近似为：When V _{DS_MN1} ＞＞kT/q, formula (13) can be approximated as:

${I I}_{DS DS__MN MN 11} \approx \approx \frac{W W}{L L} μ μ (({T T}_{00})) {((\frac{T T}{{T T}_{00}}))}^{- - n no} {((\frac{kT kT}{q q}))}^{22} {C C}_{D D.} exp exp ((\frac{q q}{kT kT} \frac{{V V}_{GS GS__MN MN 11} - - {V V}_{TH TH}}{n no})) - - - - - - ((1414))$

${V V}_{GS GS__MN MN 11} = = \frac{{R R}_{66} + + {R R}_{77}}{{R R}_{55} + + {R R}_{66} + + {R R}_{77}} {V V}_{REF REF} - - \frac{{22 R R}_{44}}{{R R}_{33}} {V V}_{T T} ln ln N N - - - - - - ((1515))$

将式（15）代入（14）并进行求导可得：Substituting (15) into (14) and deriving:

$\frac{{dI iGO}_{DS DS__MN MN 11}}{dT dT} = = \frac{W W}{L L} {C C}_{D D.} {((\frac{k k}{q q}))}^{22} μ μ (({T T}_{00})) \frac{11}{{T T}_{00}^{- - n no}} exp exp ((\frac{q q ((A A - - {V V}_{TH TH}))}{nkT wxya})) {T T}^{- - n no} [[((22 - - n no)) T T - - \frac{qT wxya}{kn k n} \frac{{&PartialD; &PartialD; V V}_{TH TH}}{&PartialD; &PartialD; T T} - - \frac{q q}{kn k n} ((A A - - {V V}_{TH TH}))]] - - - - - - ((1616))$

${V V}_{t t} = = {φ φ}_{ms ms} + + 22 {φ φ}_{f f} - - \frac{{Q Q}_{ss ss}}{{C C}_{ox ox}} + + γ γ ((\sqrt{{22 φ φ}_{f f} + + {V V}_{SB SB}} - - \sqrt{{22 φ φ}_{f f}})) - - - - - - ((1717))$

$\frac{{dV dV}_{t t}}{dT dT} = = - - \frac{11}{T T} ((\frac{{E E.}_{g g}}{22 q q} - - {φ φ}_{f f})) ((22 + + \frac{γ γ}{\sqrt{22 {φ φ}_{f f}}})) - - - - - - ((1818))$

因此，阈值电压与温度不是线性关系，温度系数绝对值会随着温度的增加而减小。可以看出，(2-n)T>0，

随温度的升高，(2-n)T逐渐增大，

逐渐减小，且减小速率大于(2-n)T增大的速率，

保持不变，由此可以得到如图5关于I_{DS_MN1}和dI_{DS_MN1}/dT的仿真曲线图，在温度较低（经测量为-38℃）时，温度系数为正；当温度升高时，温度系数为负。Therefore, the threshold voltage is not linearly related to temperature, and the absolute value of the temperature coefficient will decrease as the temperature increases. It can be seen that (2-n)T>0,

With the increase of temperature, (2-n)T gradually increases,

Gradually decreases, and the rate of decrease is greater than the rate of increase of (2-n)T,

Keeping unchanged, the simulation curves of I _{DS_MN1} and dI _{DS_MN1} /dT can be obtained as shown in Figure 5. When the temperature is low (measured as -38°C), the temperature coefficient is positive; when the temperature rises, the temperature The coefficient is negative.

4.误差放大器电路分析：4. Error amplifier circuit analysis:

从图3中可以看出，误差放大器电路（运放）采用折叠式两级结构，误差放大器电路的输入端采用射极跟随器将输入电压降低一个BE结电压，然后再将输入电压连接到运放的输入对管QAP1和QAP2，以满足运放的输入电压范围。QAN5的作用是将运放从双端输出变成单端输出，QAN5和电阻RA3的作用是增大QAN5上的电流，防止在某些情况下QAN5的电流为零，不能完成双端转单端。误差放大器电路的增益越大，其钳位性能越好，由有限增益所引起的系统误差越小，其中误差放大器电路的直流增益为：It can be seen from Figure 3 that the error amplifier circuit (op amp) adopts a folded two-stage structure. The input terminal of the error amplifier circuit uses an emitter follower to reduce the input voltage by a BE junction voltage, and then connects the input voltage to the op amp. The input pair of tubes QAP1 and QAP2 is used to meet the input voltage range of the op amp. The function of QAN5 is to change the op amp from double-ended output to single-ended output. The function of QAN5 and resistor RA3 is to increase the current on QAN5 to prevent the current of QAN5 from being zero in some cases, and the double-ended to single-ended cannot be completed. . The greater the gain of the error amplifier circuit, the better its clamping performance, and the smaller the system error caused by the finite gain. The DC gain of the error amplifier circuit is:

A_V=A_V1A_V2=g_mg_mq[g_mr_op3r_op4||r_oq(g_mqR_A1||r_oq)]r_op7r_0n4 (19)A _V =A _V1 A _V2 =g _m g _mq [g _m r _op3 r _op4 ||r _oq (g _mq R _A1 ||r _oq )]r _op7 r _0n4 (19)

其中，A_V1和A_V2分别为误差放大器电路第一级和第二级增益，g_m和g_mq分别为MOS管和双极型晶体管的跨导，r_oq为双极性晶体管的输出电阻，r_op3、r_op4、r_op7和r_on4分别为MAP3、MAP4、MAP7和MAN4的输出电阻。Among them, A _V1 and A _V2 are the gain of the first stage and the second stage of the error amplifier circuit respectively, g _m and g _mq are the transconductance of the MOS transistor and the bipolar transistor respectively, r _oq is the output resistance of the bipolar transistor, r _op3 , r _op4 , r _op7 and r _on4 are the output resistances of MAP3, MAP4, MAP7 and MAN4 respectively.

这里，电容C0为密勒电容，用于实现极点分离，确保环路具有足够的相位裕度，实现电路稳定；电阻RA4是零点补偿电阻，用于抵消右半平面零点对环路稳定性的影响；两级运放的高增益也保证了电压基准源的高PSRR。Here, the capacitor C0 is a Miller capacitor, which is used to achieve pole separation, to ensure that the loop has sufficient phase margin, and to achieve circuit stability; the resistor RA4 is a zero point compensation resistor, which is used to offset the influence of the right half plane zero point on the loop stability ; The high gain of the two-stage op amp also ensures the high PSRR of the voltage reference.

5.偏置电路说明：5. Bias circuit description:

当QN8和QN9基极有电流注入，使得MP6和MP7所在支路摆脱零简并点开始正常工作，为一阶基准电路提供一股PTAT电流，建立正常的工作点，其中：When the QN8 and QN9 bases have current injection, the branches where MP6 and MP7 are located get rid of the zero degeneracy point and start to work normally, providing a PTAT current for the first-order reference circuit to establish a normal operating point, where:

V_BEQN8+V_BEQN11=V_BEQN10+V_BEQN9+V_R11 (20)V _BEQN8 +V _BEQN11 =V _BEQN10 +V _BEQN9 +V _R11 (20)

忽略基极电流，I_CQN8=I_CQN10，I_CQN9=I_CQN11，而且QN9和QN10的并联数是分别为QN8和QN11的3倍，则有：Neglecting the base current, I _CQN8 = I _CQN10 , I _CQN9 = I _CQN11 , and the number of parallel connections of QN9 and QN10 is three times that of QN8 and QN11 respectively, then:

$Δ Δ {V V}_{BE BE} = = {V V}_{BEQN BEQN 88} - - {V V}_{BEQN BEQN 1010} + + {V V}_{BEQN BEQN 1111} - - {V V}_{BEQN BEQN 99} = = {V V}_{T T} ln ln ((\frac{{I I}_{SQN SQN 1010}}{{I I}_{SQN SQN 88}})) + + {V V}_{T T} ln ln ((\frac{{I I}_{SQN SQN 99}}{{I I}_{SQN SQN 1111}})) = = 22 {V V}_{T T} ln ln 33 = = {V V}_{R R 1111} - - - - - - ((21 twenty one))$

可得： $I_{PTAT 1} = I_{R 11} = \frac{V_{R 11}}{R_{11}} = \frac{{2 V}_{T} \ln 3}{R_{11}} - - - (22)$ Available: $I_{PTAT 1} = I_{R 11} = \frac{V_{R 11}}{R_{11}} = \frac{{2 V}_{T} \ln 3}{R_{11}} - - - (twenty two)$

从上式可以看出，R11上的电流为PTAT电流，则该电流通过MP6的镜像作用为其它支路提供偏置电流。通过MP2镜像到一阶基准电路电流为KI_PTAT1，其中K为MP2与MP6的宽长比的比例。有前面的分析可知，一阶基准电路产生另外一股PTAT电流为：It can be seen from the above formula that the current on R11 is PTAT current, and this current provides bias current for other branches through the mirror effect of MP6. The current mirrored to the first-order reference circuit by MP2 is KI _PTAT1 , where K is the ratio of the width to length ratio of MP2 and MP6. According to the previous analysis, the first-order reference circuit generates another PTAT current as:

${I I}_{PTAT PTAT 22} = = {I I}_{R R 33} = = \frac{{V V}_{BEQN BEQN 22} - - {V V}_{BEQN BEQN 11}}{{R R}_{33}} = = \frac{Δ Δ {V V}_{BE BE}}{{R R}_{33}} = = \frac{{V V}_{T T} ln ln 88}{{R R}_{33}} - - - - - - ((23 twenty three))$

则通过MP2的电流为2I_PTAT2，当两股PATA电流在MP2上产生的电流不相等时，需要设计均流电路，以使得基准源能够产生一个稳定的工作点。因此MP1即实现均流，使得在MP2上镜像得到的KI_PTAT1与一阶基准电路产生的2I_PTAT2相等。当KI_PTAT1>2I_PTAT2，则多余的电流会流入到MP1中。Then the current passing through MP2 is 2I _PTAT2 . When the currents generated by the two PATA currents on MP2 are not equal, a current equalizing circuit needs to be designed so that the reference source can generate a stable operating point. Therefore, MP1 implements current sharing, so that KI _PTAT1 mirrored on MP2 is equal to 2I _PTAT2 generated by the first-order reference circuit. When KI _PTAT1 >2I _PTAT2 , the excess current will flow into MP1.

6.启动过程说明：6. Description of the startup process:

首先是通过MP0管注入一股电流到QN8和QN9的基极，偏置电路启动，使MP8和MP9所在支路及MP10和QN12所在支路导通，并基准的其它部分提供偏置电压。First, a current is injected into the bases of QN8 and QN9 through the MP0 tube, and the bias circuit is started, so that the branches where MP8 and MP9 are located and the branches where MP10 and QN12 are located are turned on, and other parts of the reference provide bias voltage.

偏置电路启动之后，MP4管导通，使得这一路导通，QN6集电极电压为2V_BE，由于此时一阶基准电路关断，V_REF为零，所以此时QN4管导通，这样启动电路会给一阶基准电路注入一股电流，使得一阶基准电路摆脱零工作状态。After the bias circuit is started, the MP4 tube is turned on, so that this channel is turned on, and the QN6 collector voltage is 2V _BE . Since the first-order reference circuit is turned off at this time, V _REF is zero, so the QN4 tube is turned on at this time, and it starts up like this The circuit injects a current into the first-order reference circuit, so that the first-order reference circuit gets out of the zero working state.

同时，由于QN6导通，使得MP3所在支路导通，MP5镜像MP3的电流会给误差放大器的节点SS注入一股失调电流，此时电阻RA1的电流大于电阻RA2的电流，这种情况相当于负端电压V1低于正端V2，通过运放的放大，VREF电压会被拉高，从而加快电压基准源的启动时间。其中，引入的失调电压ΔV_BE为：At the same time, because QN6 is turned on, the branch where MP3 is located is turned on, and the current mirrored by MP5 to MP3 will inject an offset current into the node SS of the error amplifier. At this time, the current of the resistor RA1 is greater than the current of the resistor RA2. This situation is equivalent to The negative terminal voltage V1 is lower than the positive terminal V2, through the amplification of the op amp, the VREF voltage will be pulled up, thereby speeding up the start-up time of the voltage reference source. Among them, the introduced offset voltage ΔV _BE is:

$Δ Δ {V V}_{BE BE} = = {V V}_{BEQAP BEQAP 11} - - {V V}_{BEQAP BEQAP 22} = = {V V}_{T T} ln ln ((\frac{{I I}_{CQAP CQAP 11}}{{I I}_{CQAP CQAP 22}})) = = {V V}_{T T} ln ln ((\frac{{I I}_{PTAT PTAT 11} + + {K K}_{22} {I I}_{PTAT PTAT 11}}{{I I}_{PTAT PTAT 11}})) = = {V V}_{T T} ln ln ((11 + + {K K}_{22})) - - - - - - ((24 twenty four))$

其中K₂为注入通过MP5注入到SS的I_PTAT1电流倍数。输入失调电压通过误差放大器电路进行放大后输出到QN1和QN2的基极，加速电压基准源的启动。where _K2 is the multiplier of the _IPTAT1 current injected into SS through MP5. The input offset voltage is amplified by the error amplifier circuit and then output to the bases of QN1 and QN2 to accelerate the startup of the voltage reference source.

当VREF稳定后，由于QN4管的基极电压不变，而发射极电压上升到VREF，使得QN4关断，启动电路停止工作，MP5关断，不会再有电流注入到误差放大器电路中，误差放大器电路正常工作，启动过程完成。When VREF is stable, since the base voltage of QN4 tube remains unchanged, and the emitter voltage rises to VREF, QN4 is turned off, the startup circuit stops working, MP5 is turned off, and no more current will be injected into the error amplifier circuit. The amplifier circuit works normally and the start-up process is completed.

图6为电压基准源输出电压在电源电压分别为3.0V、4.5V、5.5V时的温度特性曲线，其中横坐标为温度，纵坐标为基准输出电压；图7为电压基准源输出电压启动时间的曲线，其中横坐标为时间，纵坐标为电压基准源的输出电压；图8为电压基准源的电源电压抑制特性，横坐标为频率，纵坐标为PSRR的值，可以看到在该电压基准源在低于10K范围内PSRR为87dB，在10K～100K都大于60dB；图9为电压基准源输出电压随电源电压的变化情况，其中横坐标为电源电压，纵坐标为电压基准源输出电压。Figure 6 is the temperature characteristic curve of the output voltage of the voltage reference source when the power supply voltage is 3.0V, 4.5V, and 5.5V respectively, where the abscissa is the temperature, and the ordinate is the reference output voltage; Figure 7 is the start-up time of the voltage reference source output voltage The curve, where the abscissa is time, and the ordinate is the output voltage of the voltage reference source; Figure 8 is the power supply voltage suppression characteristics of the voltage reference source, the abscissa is the frequency, and the ordinate is the value of PSRR, it can be seen that in this voltage reference The PSRR of the source is 87dB in the range below 10K, and it is greater than 60dB in the range of 10K to 100K; Figure 9 shows the variation of the output voltage of the voltage reference source with the power supply voltage, where the abscissa is the power supply voltage, and the ordinate is the output voltage of the voltage reference source.

在输入电压3.6～5.5V，温度范围为-40℃～125℃下，用Hspice进行仿真。结果表明，在温度范围为-40℃～125℃该带隙电压基准源达到了1.74ppm/℃的温度系数，低频时电源电压抑制比为87dB，启动时间仅为8us，线性调整率为0.032mV/V。Under the input voltage 3.6 ~ 5.5V, the temperature range is -40 ℃ ~ 125 ℃, use Hspice to simulate. The results show that the bandgap voltage reference source has a temperature coefficient of 1.74ppm/℃ in the temperature range of -40℃～125℃, the power supply voltage rejection ratio is 87dB at low frequency, the start-up time is only 8us, and the linear adjustment rate is 0.032mV /V.

本发明的带隙电压基准源主要有以下两个特点：The bandgap voltage reference source of the present invention mainly has the following two characteristics:

1.利用双极型器件的集电极电流和亚阈值区的MOS管漏电流的温度特性对传统的一阶带隙基准进行曲率补偿来减小温度系数，具体为在整个温度范围内，通过在基准输出电压曲线上产生多个零温系数的点来代替单个极值点。1. Use the temperature characteristics of the collector current of the bipolar device and the leakage current of the MOS tube in the subthreshold region to perform curvature compensation on the traditional first-order bandgap reference to reduce the temperature coefficient. Specifically, in the entire temperature range, through the Multiple points of zero temperature coefficient are generated on the reference output voltage curve instead of a single extreme point.

2.误差放大器电路的设计，不仅起到稳定工作点作用，同时可以减小电压基准源的启动时间。2. The design of the error amplifier circuit not only stabilizes the operating point, but also reduces the start-up time of the voltage reference source.

Claims

1. A bandgap voltage reference source, comprising: bias circuit, start-up circuit and first-order reference circuit, is characterized in that, also comprises, temperature compensation circuit and error amplifier circuit, wherein, described bias circuit is described The bandgap voltage reference source provides a bias voltage, the start-up circuit is used to make the first-order reference circuit work normally, the first-order reference circuit generates a reference voltage with a low temperature coefficient, and the temperature compensation circuit is used for a The first-order reference circuit is used for temperature compensation, and the error amplifier circuit is used to stabilize the operating point of the first-order reference circuit;

The first-order reference circuit includes a first NPN transistor, a second NPN transistor, a first PMOS transistor, a second PMOS transistor, a first resistor, a second resistor, a third resistor, and a fourth resistor;

The temperature compensation circuit includes a third NPN transistor, a first NMOS transistor, a fifth resistor, a sixth resistor, and a seventh resistor;

The startup circuit includes a fourth NPN transistor, a fifth NPN transistor, a sixth NPN transistor, a third PMOS transistor, a fourth PMOS transistor, an eighth resistor, a ninth resistor, and a tenth resistor;

The specific connection relationship is as follows:

The base of the first NPN transistor is connected to the base of the second NPN transistor and the emitter of the fourth NPN transistor of the startup circuit, and simultaneously serves as a reference output voltage, and the collectors of the first NPN transistor and the second NPN transistor are respectively connected to The first resistor is connected to one end of the second resistor, and the collectors of the first NPN transistor and the second NPN transistor are respectively connected to the negative input terminal and the positive input terminal of the error amplifier circuit, and the other end of the first resistor and the second resistor It is connected to the drain of the second PMOS transistor, the source of the second PMOS transistor is connected to the external power supply, the gate is connected to the gate of the fourth PMOS transistor of the startup circuit, and the source of the first PMOS transistor is connected to the second PMOS transistor. The drain of the tube is connected, the gate is connected between the eighth resistor and the ninth resistor of the startup circuit, the drain is connected to the ground, the emitter of the first NPN tube is connected to one end of the third resistor, and the third resistor The other end of the ground through the fourth resistor;

The fifth resistor, the sixth resistor and the seventh resistor are connected in sequence between the bases of the first NPN transistor and the second NPN transistor in the first-order reference circuit and the ground, and the collector of the third NPN transistor is connected to the ground in the first-order reference circuit. The collector of the second NPN transistor is connected, the base of the third NPN transistor is connected to the end that is commonly connected to the sixth resistor and the seventh resistor; the drain of the first NMOS transistor is connected to the collector of the third NPN transistor QN6, and the gate The electrode is connected to the end of the common connection between the fifth resistor and the sixth resistor, the emitter of the third NPN transistor is connected to the source of the first NMOS transistor, and is connected to the third resistor and the fourth resistor in the first-order reference circuit. The ends that are commonly connected are connected;

The base of the fifth NPN transistor is short-circuited to the collector and connected to the emitter of the sixth NPN transistor, the emitter of the fifth NPN transistor is connected to the ground, the base of the sixth NPN transistor is short-circuited to the collector, and respectively Connected to the base of the fourth NPN transistor and the drain of the fourth PMOS transistor, the gate of the fourth PMOS transistor is connected to an output terminal of the bias circuit, and connected to the gate of the second PMOS transistor of the first-order reference circuit The eighth resistor, the ninth resistor and the tenth resistor are sequentially connected between the emitter of the fourth NPN transistor and the ground, the collector of the fourth NPN transistor is connected to the drain of the third PMOS transistor, and the third PMOS transistor The gate of the PMOS transistor is short-circuited to the drain, and the sources of the third PMOS transistor and the fourth PMOS transistor are connected to an external power supply.

2. The bandgap voltage reference source according to claim 1, wherein the error amplifier circuit comprises: NPN transistors QAN1, QAN2, QAN3, QAN4, QAN5, and QAN6, PNP transistors QAP1 and QAP2, and PMOS transistor MAP1 , MAP2, MAP3, MAP4, MAP5, MAP6, MAP7 and MP5, NMOS tubes MAN1, MAN2, MAN3 and MAN4, resistors RAP1, RAP2, RAP3 and RAP4, capacitor C0, where the sources of MAP1, MAP3, MAP5 and MAP7 are connected to The power supply is connected and the gate is connected; the drains of MAP1, MAP3 and MAP5 are respectively connected with the sources of MAP2, MAP4 and MAP6, the gates of MAP2, MAP4 and MAP6 are connected, and the drain of MP7 is connected with the drain of MAN4, and serve as The output terminal of the error amplifier circuit, the source of MAN4 is connected to the ground, the gate is connected to the drain of MAN3, the sources of MAN1, MAN2 and MAN3 are connected to the ground, and the gate is connected; the bases of QAN1 and QAN2 are the input terminals of the error amplifier circuit , the collector is connected to the power supply, the emitter of QAN1 is connected to the base of QAP1 and the drain of MAN1, the emitter of QAN2 is connected to the base of QAP2 and the drain of MAN2, the emitters of QAP1 and QAP2 are connected, and connected to The drain of MAP2 is connected, the collector of QAP1 is connected to the emitter of QAN3 and the drain of MP5, the source of MP5 is connected to the external power supply; the collector of QAP2 is connected to the emitter of QAN4, the bases of QAN3 and QAN4, QAN5 The emitters of QAN3 and QAN4 are connected to the drains of MAP4 and MAP6 respectively, the base of QAN5 is connected to the emitter of QAN3, the collector is connected to the power supply, and the resistors RAP1, RAP2, and RAP3 are respectively connected to QAN3 and QAN4 Between the emitter of QAN5 and the ground, the base and emitter of QAN6 are connected to the collector of QAN4 and the drain of MAN3, and the resistor RA4 and capacitor C0 are connected in sequence between the base of QAN6 and the drain of MAN4.

3. The bandgap voltage reference source according to claim 2, wherein the gate of the PMOS transistor MP5 in the error amplifier circuit is connected to the gate of the third PMOS transistor of the start-up circuit.