CN102369604B - Vertical structure light emitting diode structure and manufacturing method thereof - Google Patents

Abstract

The invention provides a method for manufacturing a compound semiconductor vertical structure LED. Providing a first growth substrate capable of supporting epitaxial growth of a compound semiconductor thereon; forming one or more compound semiconductor material epitaxial layers such as GaN or InGaN on a first growth substrate; forming a plurality of trenches within a compound semiconductor material; depositing a passivation material in the one or more trenches; depositing a hard material at least partially within the trench and selectively on the compound semiconductor, the hard material having a hardness greater than a hardness of the compound semiconductor material; depositing a high thermal conductive metal material on the compound semiconductor material, and then planarizing the metal material; and adhering a new main substrate to the metal layer, and removing the first growth substrate. And then cut to make individual LED elements.

Description

Vertical structure light emitting diode structure and manufacturing method thereof

【CROSS-REFERENCE TO RELATED APPLICATIONS】

This application is US Patent Application 61/445,516 (Filing Date: February 22, 2011), US Patent Application 12/912,727 (Filing Date: October 26, 2010), US Patent Application 11/891,466 (Filing Date: 2007 August 10, 2009), U.S. Patent Application No. 12/058,059 (filed March 22, 2008), U.S. Patent No. 7,846,753, and continuation-in-part of U.S. Patent Application No. 12/415,467 (filed March 31, 2009) case, which is cited and incorporated into this disclosure.

【Technical field】

The present invention relates to the fabrication of light-emitting diodes (LEDs), and more particularly to the fabrication of vertically structured LEDs and LED devices fabricated therefrom.

【Background technique】

Vertically structured light-emitting diodes (LEDs) comprising GaN-based materials are becoming increasingly popular as light sources. Typically, layers of epitaxially grown material containing GaN are deposited on non-GaN substrates, such as sapphire (Al ₂ O ₃ ), thanks to the low cost of high-quality sapphire substrates. However, high-power GaN-based LEDs generate considerable heat during use; this heat needs to be dissipated efficiently to enable the application of large-size LED light sources and extend the life of the LEDs.

Although the sapphire substrate allows high-quality epitaxial layers to be grown on it, the sapphire substrate is neither electrically nor thermally conductive and must be replaced by a good thermal conductor before it can be used in the final LED component package.

There are many ways to replace sapphire with a thermally conductive substrate. One such method is laser lift-off, which uses an excimer laser to decompose the interfacial region of GaN and then removes the sapphire growth substrate. Laser lift-off methods for removing sapphire substrates as described above are described in US Pat. Nos. 6,455,340, 7,001,824 and 7,015,117. However, the existing laser lift-off method for fabricating GaN light-emitting diodes is not suitable for traditional semiconductor processes because it uses expensive laser equipment, and laser lift-off can also cause damage to the remaining semiconductor layer, such as cracks .

Another method is to bond a new master substrate to the surface of the epitaxial material layer, and then use chemical mechanical polishing to remove the sapphire growth substrate. With chemical mechanical polishing (CMP), significant cost savings can be achieved. Also, polishing is a gentler method that causes less damage than laser lift-off techniques. However, before a new master substrate is bonded, the surface of the epitaxial material layer will be uneven due to various processes. When bonding a new substrate to an uneven surface, there will be bond voids, resulting in insufficient bonding and/or stress in the final component. Therefore, there is a need for improved techniques for bonding new host substrates to epitaxial layers in LED device fabrication.

【Content of invention】

The present invention provides a method of fabricating a compound semiconductor LED element, such as a GaN-based LED element. Some of the methods used by the present invention for use within various process steps are described in US Published Patent Applications 2009-0218590, 2008-0197367, 2011-0037051 and US Patent 7,846,753, which are hereby incorporated by reference into this disclosure. In these applications and patents, sapphire is used as a material for a host substrate on which compound semiconductor layers are formed.

In these common applicant's patents and applications, a growth substrate such as sapphire has grown thereon a compound semiconductor epitaxial layer comprising GaN, such as InGaN. The thickness of a typical epitaxial layer is 3 to 10 microns, and the growth substrate is about 430 microns.

Following the patterning process, the epitaxial layer is partially or completely removed in some areas to form trenches. Next, dielectric and hard materials are deposited and patterned. Diamond or diamond-like carbon is a typical example of a hard material. The hard material acts as a polishing stop during removal of the growth substrate. Typical thicknesses for hard materials are 1 to 5 microns. Due to the presence of hard materials, the wafer surface is uneven with a step height greater than 1 micron.

Therefore, in order to bond a new host substrate to the uneven epitaxial layer, the present invention provides for depositing a metal layer on the epitaxial layer, followed by planarization of the deposited metal layer. A new host substrate is then bonded to the planarized metal layer, and the first growth substrate is removed. Then cut to form individual LED elements.

【Description of drawings】

1A-1G show a method of fabricating a vertical structure LED according to one aspect of the present invention.

2A-2G show another method of fabricating a vertical structure LED according to one aspect of the present invention.

Figure 2G' shows another vertical structure LED of the present invention.

【Detailed ways】

According to the invention, a metal layer is deposited on epitaxial semiconductor layers, especially those comprising GaN or compound semiconductor materials, which are planarized before bonding a new host substrate to produce vertically structured LEDs. As used herein, "on" means that one layer is on top of another layer, means that it is in direct contact with that layer in one or more places, or it can be separated from the next layer, and the intermediate interval is optional middle layer of material. Figure 1 shows a portion of a monolithic wafer used to fabricate multiple LED chips that will eventually be used in LED components and integrated into lighting fixtures or lighting components. For convenience of description, only a few LED chips are described. In FIG. 1A, there is a first substrate 110 that can support epitaxial growth. Typical substrate materials include sapphire, silicon, aluminum nitride (AlN), silicon carbide (SiC), gallium arsenide (GaAs), and gallium phosphide (GaP), and of course any material capable of supporting the next layer of compound semiconductor material Any epitaxially grown material can be used as the substrate 110 . An epitaxial layer 120 of a compound semiconductor such as gallium nitride (GaN) or indium gallium nitride (InGaN) is formed on the substrate 110 . Although InGaN is described as a typical material, other compound semiconductors such as InGaP, AlInGaN, AlInGaP, AlGaAs, GaAsP or InGaAsP may also be used without limitation, depending on the overall desired LED color. The notation "InGaN" in the drawings is therefore merely used to indicate the compound semiconductor layer. Although not shown in the figure, various active layer structures can be included in layer 120, such as multiple quantum well (MQW) structures, n-doped and p-doped materials, which can be described in the previously cited patent application the same or different. Note that Figure 1A only shows a portion of the wafer that will eventually be singulated into individual LED chips. A typical wafer consists of multiple chips formed on a large support substrate wafer so that multiple chips (which will eventually be fabricated into final components) can be produced simultaneously.

Next is described how to start to fabricate the material layers of the vertical structure LED, trenches 130 are formed in the multilayer structure 120 (already formed in FIG. 1A ). A dry etch such as plasma etch, particularly inductively coupled plasma etch, is selected for forming trench 130 .

A passivation material layer 140 forms inside the trench 130 . The passivation material layer covers at least the walls and the bottom of the trench. Alternative passivation materials include dielectrics such as silicon oxides, silicon nitrides, and the like. A hard material 150 is formed on the passivation material and patterned to expose the epitaxial semiconductor layer, the hard material 150 acts as a polishing stop during subsequent removal of the growth substrate. The hardness of the hard material is greater than that of the epitaxial semiconductor layer. Usually the thickness of the hard material 150 is 1~5um.

In the embodiment of FIG. 1, a portion of the hard material covers at least a portion of the epitaxial semiconductor layer 120, forming a "shoulder" of hard material over this area. As a result, as shown in FIG. 1A , the entire surface is uneven due to the existence of the "shoulders" of this hard material film, with step heights typically greater than 1 micron. Hard materials include diamond, diamond-like carbon, carbides such as SiC, nitrides such as boron nitride, but are not limited to these materials. A detailed description of the above process steps can be found in the previously cited patent applications.

As shown in FIG. 1A , a metal layer 160 is selectively deposited on the semiconductor structure 120 . The metal layer acts as an electrical connection, eg, p-electrode, and can be used for optical reflection of light generated by the semiconductor. Typical metals include nickel, silver, titanium, aluminum, platinum, and alloys thereof, although any metal or other conductive material that can serve as an electrical connection and optical reflector can be used for layer 160, which is compatible with the selected epitaxial semiconductor material 120. compatible.

Covering the entire surface of the structure is a deposited metal layer 170 . The usual metal deposition thickness is 10-100 microns. Because the substrate structure is not flat prior to metal deposition, the deposited metal surface 175 is also not flat, such as surface 175 in FIG. 1A . Preferably, the thermal conductivity of the deposited metal is higher than 130 W/m-K in order to effectively dissipate heat from the light emitting semiconductor layer structure 120 .

In preparation for metal layer 170 to be bonded to a new host substrate, metal surface 175 needs to be planarized to form a new, planar metal layer surface 177, as shown in FIG. 1B. The planarization process can be a mechanical, chemical, chemical mechanical, thermal reflow planarization method. Typically the final metal thickness is 1 to 80 microns. Metal thickness greater than 80 microns is not optimal for using laser cutting technology to singulate LED chips. However, thicker metal layers can be selected if other cutting techniques such as mechanical cutting are used.

In FIG. 1C a new master substrate 200 is bonded to the new surface 177 of the metal layer 170 by a thin adhesive layer 180 . The new host substrate is usually a non-metallic material with high thermal conductivity (above 130 W/m K), such as SiC, AlN, silicon or other semiconducting materials; however, depending on the end application, a metal backing can also be chosen end. The new master substrate preferably has sufficient mechanical strength to adequately support the layer of semiconductor material during subsequent processing, and can be easily separated by laser or mechanical cutting. The initial thickness of the new master substrate is typically greater than 100 microns; however, the initial thickness depends on the overall size of the original selected. Adhesive layer 180 may be a metal such as metal solder or any other suitable permanent adhesive material with good conductivity. Because the metal surface 177 is flat, there are no wafer cracks or bond voids on the bonded host substrate.

As shown in FIG. 1D, the new master substrate 200 is optionally thinned down by any conventional mechanical, chemical, or chemical-mechanical thinning methods, however, depending on the initial Thickness and final desired thickness, also may not require thinning. A typical final thickness of an individual chip is 50-500 microns. Then, the growth substrate 110 is removed by a suitable method such as polishing or chemical mechanical polishing. At this point, the light emitting semiconductor layer structure 120 has been successfully converted from the original growth substrate 110 into the new master substrate 200 .

In FIG. 1E , the orientation of the structure has been reversed (“flip-chip”), with the new master substrate 200 at the bottom and the light emitting semiconductor layer structure 120 at the top. To form individual chips, dicing is typically used to separate each LED. As shown in Figure IE, laser cutting was used to separate, although any other method could be used to separate the device. Advantageously, laser cutting produces narrower kerf widths (as small as 10 microns) compared to other cutting methods. When laser cutting is used, the laser cutting depth is approximately up to the new master substrate 200, but does not need to be cut completely. As shown in FIG. 1F , a cleaving tool 190 (breaker element) is used under the new master substrate 200 to separate the LED chips by mechanical cleaving.

An isolated chip is shown in Figure 1G. The semiconductor layer structure 120 includes an InGaN epitaxial layer (3-10 microns). Optionally, a "shoulder" portion of the hard material 150 remains after chip singulation, surrounding the semiconductor layer structure 120 . Layer 170 is a high thermal conductivity metal layer (1-80 microns, thermal conductivity higher than 130W/m·K), and element 200 is a new main substrate (50-150 microns).

Figures 2A-2G illustrate another aspect of the invention in which the hard material layer 150' is deposited only in the trench 130. The hard material may partially or completely fill the trench 130 . Because the stiff material 150' is not at all coplanar with the semiconductor material 120, there is still an uneven surface, and subsequent deposition of the metal layer 170 and planarization process is still required.

In FIG. 2G', the hard material 150' has been removed by any conventional method or by selection of the location of the separation so that the hard material 150' is also removed during device separation. In this way, passivation material 140 forms a peripheral edge around semiconductor material 120 .

After being separated into individual components, vertical structure LEDs are packaged and then integrated into LED lighting equipment. Encapsulation may include the use of additional various phosphors or other compounds to change the color of the emitted LED light.

Although the above invention has been described in various embodiments, it is not limited to these embodiments. Various changes and modifications will be apparent to those skilled in the art. Such changes and modifications should be considered as included within the scope of the appended claims.

Claims (19)

1. method of making a plurality of compound semiconductor light emitting diode with vertical structure chips, the compound semiconductor epitaxial layer that this light-emitting diode chip for backlight unit comprises has one or more layers nitrilo compound semi-conducting material, and comprise new main substrate binding to described compound semiconductor light emitting diode with vertical structure, this method comprises:

First growth substrates is provided, can supports the compound semiconductor epitaxial growth on it;

Form one or more layers compound semiconductor materials epitaxial loayer in first growth substrates;

Form one or more grooves at least a portion compound semiconductor materials;

Deposit a passivating material in one or more grooves;

Deposit a stiff materials at least in part in one or more grooves, the hardness of described stiff materials is greater than the hardness of described compound semiconductor materials;

Deposit a high-thermal conductive metal material on described compound semiconductor materials;

The metal material of the described deposition of planarization is to form a smooth metal level;

To described metal level, described new main substrate is high heat conduction by the bonding new main substrate of one deck adhesive layer;

Remove first growth substrates.

2. the method for a plurality of compound semiconductor light emitting diode with vertical structure of making as claimed in claim 1 chip, wherein said stiff materials is deposited at least a portion compound semiconductor materials extraly, to form a stiff materials shoulder on described compound semiconductor materials.

3. the method for a plurality of compound semiconductor light emitting diode with vertical structure of making as claimed in claim 1 chip, also comprise: optionally depositing metal layers is at least a portion compound semiconductor materials, described metal material forms electrode, optical reflector, or the both is.

4. the method for a plurality of compound semiconductor light emitting diode with vertical structure of making as claimed in claim 1 chip also comprises: deposition one bonding metal between the metal level of planarization and new main substrate, wherein new main substrate is nonmetallic materials.

5. the method for a plurality of compound semiconductor light emitting diode with vertical structure of making as claimed in claim 1 chip, wherein said stiff materials is diamond, diamond-film-like, boron nitride or carborundum.

6. the method for a plurality of compound semiconductor light emitting diode with vertical structure of making as claimed in claim 1 chip, wherein growth substrates is removed by polishing.

7. the method for a plurality of compound semiconductor light emitting diode with vertical structure of making as claimed in claim 6 chip, wherein growth substrates is removed by chemico-mechanical polishing.

8. the method for a plurality of compound semiconductor light emitting diode with vertical structure of making as claimed in claim 1 chip comprises that also element divisions is to form independent light-emitting diode.

9. the method for a plurality of compound semiconductor light emitting diode with vertical structure of making as claimed in claim 8 chip, wherein element divisions is laser cutting.

10. the method for a plurality of compound semiconductor light emitting diode with vertical structure of making as claimed in claim 1 chip, wherein at least one stratification compound semiconductor epitaxial layers comprises GaN or InGaN.

11. a method of making light-emitting component, this light-emitting component is integrated with the compound semiconductor light emitting diode with vertical structure, comprising: encapsulation is by the described light-emitting diode chip for backlight unit of claim 8.

12. the structure of a compound semiconductor light emitting diode with vertical structure, the compound semiconductor epitaxial layer that this structure comprises have one or more layers nitrilo compound semi-conducting material, and are bonded on the new main substrate, comprising:

One or more layers compound semiconductor epitaxial layer, it forms the light emitting diode with vertical structure of a part;

One or more grooves, it is formed at least a portion compound semiconductor materials, forms a plurality of chips in compound semiconductor materials;

One layer of passivation material, it is deposited in described one or more groove;

One stiff materials, it is deposited in described one or more groove at least in part, and the hardness of described stiff materials is greater than the hardness of described compound semiconductor materials;

The metal level of the planarization of one high heat conduction, it is deposited on the described compound semiconductor materials, and the thermal conductivity of described metal level is higher than 130W/mK, and thickness is 1～80 micron;

One adhesive layer, it is on the metal level of described planarization;

The main substrate of a new high heat conduction, it is bonded in by described adhesive layer on the metal level of described planarization, and its thickness is 50～500 microns.

13. the structure of compound semiconductor light emitting diode with vertical structure as claimed in claim 12, wherein said stiff materials is deposited at least a portion compound semiconductor materials extraly.

14. the structure of compound semiconductor light emitting diode with vertical structure as claimed in claim 12, also comprise the optionally metal level of deposition, it is at least a portion compound semiconductor materials, and described metal material forms electrode, optical reflector, or the both is.

15. the structure of compound semiconductor light emitting diode with vertical structure as claimed in claim 12, wherein said stiff materials are diamond, diamond-film-like, boron nitride or carborundum.

16. the structure of compound semiconductor light emitting diode with vertical structure as claimed in claim 12, wherein at least one stratification compound semiconductor epitaxial layers comprises GaN or the compound compound-material of InGaN.

17. a compound semiconductor light emitting diode with vertical structure, it requires 12 described structures to separate by groove position accessory rights, makes stiff materials be retained on the sidewall of compound semiconductor layer.

18. a compound semiconductor light emitting diode with vertical structure as claimed in claim 17, wherein stiff materials is removed near the compound semiconductor materials.

19. illumination component that comprises compound semiconductor light emitting diode with vertical structure as claimed in claim 17.

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