CN102376871B - Magnetic tunnel junction memory unit and manufacturing method thereof - Google Patents
Magnetic tunnel junction memory unit and manufacturing method thereof Download PDFInfo
- Publication number
- CN102376871B CN102376871B CN2010102632582A CN201010263258A CN102376871B CN 102376871 B CN102376871 B CN 102376871B CN 2010102632582 A CN2010102632582 A CN 2010102632582A CN 201010263258 A CN201010263258 A CN 201010263258A CN 102376871 B CN102376871 B CN 102376871B
- Authority
- CN
- China
- Prior art keywords
- deck
- side wall
- magnetic
- wall construction
- tunnel junction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 238000010276 construction Methods 0.000 claims description 48
- 239000011248 coating agent Substances 0.000 claims description 41
- 238000000576 coating method Methods 0.000 claims description 41
- 150000004767 nitrides Chemical class 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 35
- 238000005530 etching Methods 0.000 claims description 34
- 230000004888 barrier function Effects 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 239000004020 conductor Substances 0.000 claims description 5
- 230000001413 cellular effect Effects 0.000 claims description 2
- 230000007547 defect Effects 0.000 abstract 1
- 239000000428 dust Substances 0.000 description 4
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 240000001439 Opuntia Species 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910000836 magnesium aluminium oxide Inorganic materials 0.000 description 1
- CPLXHLVBOLITMK-UHFFFAOYSA-N magnesium oxide Inorganic materials [Mg]=O CPLXHLVBOLITMK-UHFFFAOYSA-N 0.000 description 1
- 239000000395 magnesium oxide Substances 0.000 description 1
- AXZKOIWUVFPNLO-UHFFFAOYSA-N magnesium;oxygen(2-) Chemical compound [O-2].[Mg+2] AXZKOIWUVFPNLO-UHFFFAOYSA-N 0.000 description 1
- 230000005415 magnetization Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Images
Landscapes
- Semiconductor Memories (AREA)
- Hall/Mr Elements (AREA)
- Mram Or Spin Memory Techniques (AREA)
Abstract
The invention relates to a magnetic tunnel junction memory unit and a manufacturing method thereof. The magnetic tunnel junction memory unit comprises a lower electrode, an upper electrode, a magnetic tunnel junction and a side wall structure, wherein the upper electrode is arranged above the lower electrode; the magnetic tunnel junction is sandwiched between the lower electrode and the upper electrode; and the side wall structure is formed on two sides of the magnetic tunnel junction. According to the magnetic tunnel junction memory unit provided by the invention, on the premise that the line width of the magnetic tunnel junction is not increased, the problem of electric connection formed between the upper and lower electrodes caused by defect of a dielectric layer can be overcome, thereby avoiding failure of the magnetic tunnel junction memory unit.
Description
Technical field
The present invention relates to semiconductor memory, relate in particular to a kind of magnetic channel knot (MTJ) memory cell, the magnetic RAM (MRAM) with this magnetic tunnel junction memory unit and the manufacture method of described magnetic tunnel junction memory unit.
Background technology
Magnetic RAM (Magnetic Random Access Memory, MRAM) be a kind of static random access memory, it has at a high speed reads and write capability, and the high integration of dynamic random access memory, and basically can repeat to write unlimitedly.MRAM comprises magnetic channel knot (Magnetic Tunnel Junction, MTJ) memory cell of transistor and storage data.MRAM is the memory device that a kind of characteristic of utilizing these MTJ unit is write data.
Fig. 1 shows the structural representation of magnetic tunnel junction memory unit of the prior art.Magnetic tunnel junction memory unit 100 comprises bottom electrode 110, magnetic channel knot 120 and top electrode 130.Bottom electrode 110 and top electrode 130 can be tantalum (Ta) electrode or titanium nitride (TiN) electrode.Magnetic channel knot 120 comprises pinning layer 121, tunnel barrier layer 122 and the recording layer 123 sequentially be stacked on bottom electrode 110.Pinning layer 121 and recording layer 123 are made by ferrimagnet.Tunnel barrier layer 122 is usually very thin, and its material is magnesium oxide or aluminium oxide etc.Top electrode 130 is stacked on recording layer 123.
When writing recorded information, pass into electric current in bottom electrode 110 and top electrode 130, and electric current ties 120 by magnetic channel.This electric current produces magnetic field at bottom electrode 110 and 130 of top electrodes, makes the direction of magnetization reversion of the recording layer 123 in magnetic channel knot 120 by means of this magnetic field.According to the magnetized relative configuration of pinning layer 121 and recording layer 123, be parallel or antiparallel is carried out recording binary information.
Fig. 2 shows the schematic diagram that prior art forms the top electrode opening of magnetic tunnel junction memory unit.As shown in Figure 2, form magnetic channel knot 220 on the dielectric layer 240 that comprises bottom electrode 210, wherein magnetic channel knot 220 be positioned at bottom electrode 210 directly over.Form the method for magnetic channel knot 220 for first sequentially forming pinning material layer, tunnel barrier material layer and recording materials layer, then by photoetching process, form magnetic channel knot 220.Then, dielectric layer 250, and in dielectric layer 250, magnetic channel knot 220 directly over etching form the opening 230 that holds top electrode.Finally, at the interior filled conductive material of opening 230, form top electrode.
When MRAM is carried out to write operation, current density must meet certain numerical value could realize data writing.The area of magnetic channel knot is larger, and required write current is also larger, could meet so the required current density of write operation.This will certainly cause increasing the power consumption of MRAM when carrying out write operation.In addition, the area of magnetic channel knot also can reduce the storage density of MRAM greatly, therefore requires the magnetic channel knot to have less live width.As shown in Figure 2, because the live width of magnetic channel knot 220 is less, the dielectric layer that therefore meeting is tied 220 both sides to magnetic channel in the process of etching opening 230 carries out etching.This may make bottom electrode 110 and the top electrode that forms subsequently between because the damaged of dielectric layer is electrically connected to, cause magnetic tunnel junction memory unit to lose efficacy.
Therefore, need a kind of magnetic tunnel junction memory unit and manufacture method thereof, under the prerequisite of the live width that does not increase the magnetic channel knot, overcome because the damaged of dielectric layer causes between upper/lower electrode forming the problem be electrically connected to, thereby avoid magnetic tunnel junction memory unit to lose efficacy.
Summary of the invention
Introduced the concept of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
In order solving when etching forms the opening of top electrode, dielectric layer to be caused to damaged problem, to the invention provides a kind of magnetic tunnel junction memory unit, comprising: bottom electrode; Top electrode, be positioned at the top of described bottom electrode; The magnetic channel knot, be interposed between described bottom electrode and described top electrode; And side wall construction, be formed on described magnetic channel knot both sides.
Preferably, the width sum of the width of described side wall construction and described magnetic channel knot is more than or equal to the width of described top electrode.
Preferably, described side wall construction comprises at least one deck oxide skin(coating) and at least one deck nitride layer, every one deck alternative arrangement in every one deck in wherein said at least one deck oxide skin(coating) and described at least one deck nitride layer, and the innermost layer of described side wall construction is oxide skin(coating).
Preferably, described side wall construction comprises one deck oxide skin(coating) and one deck nitride layer, and the innermost layer of described side wall construction is oxide skin(coating).
Preferably, the silicon nitride that the material of described nitride layer is silicon nitride or carbon dope.
Preferably, between the upper surface do not covered by described magnetic channel knot at described bottom electrode and described magnetic channel knot and described side wall construction, also comprise barrier layer.
The present invention also provides a kind of method of manufacturing magnetic tunnel junction memory unit, comprising: bottom electrode is provided; Form the magnetic channel knot on described bottom electrode; Form side wall construction in described magnetic channel knot both sides; And tie the formation top electrode at described magnetic channel.
Preferably, the width sum of the width of described side wall construction and described magnetic channel knot is more than or equal to the width of described top electrode.
Preferably, the method that forms described side wall construction comprises: at described bottom electrode and described magnetic channel, tie and form at least one deck oxide skin(coating) and at least one deck nitride layer, every one deck alternative arrangement in every one deck in wherein said at least one deck oxide skin(coating) and described at least one deck nitride layer, and innermost layer is oxide skin(coating); And etching described at least one deck oxide skin(coating) and described at least one deck nitride layer, form described side wall construction.
Preferably, the method that forms described side wall construction comprises: at described bottom electrode and described magnetic channel, tie and form successively one deck oxide skin(coating) and one deck nitride layer; And the described oxide skin(coating) of etching and described nitride layer, form described side wall construction.
Preferably, the silicon nitride that the material of described nitride layer is silicon nitride or carbon dope.
Preferably, the method that forms described top electrode comprises: at described bottom electrode and the described magnetic channel that is formed with described side wall construction, tie the formation dielectric layer; Form opening directly over the knot of magnetic channel described in described dielectric layer; Filled conductive material in described opening, form described top electrode.
Preferably, described method also is included in described bottom electrode and described magnetic channel and ties and form barrier layer.
The present invention also provides a kind of magnetic RAM, it is characterized in that, described magnetic RAM comprises described magnetic tunnel junction memory unit.
Magnetic tunnel junction memory unit according to the present invention comprises the side wall construction that is formed on magnetic channel knot both sides, therefore can prevent from, in the opening process of top electrode is held in etching formation, the dielectric layer between upper/lower electrode is carried out to etching.Wherein, the width sum of the width of side wall construction and magnetic channel knot is more than or equal to the width of top electrode, can in etching process, effectively stop the etching of etching gas to dielectric layer.In addition, magnetic tunnel junction memory unit can also comprise barrier layer, to prevent pollution and the damage of subsequent technique to the magnetic channel knot.This barrier layer can also hold as follow-up making the etching stop layer of the opening of top electrode.
The accompanying drawing explanation
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.In the accompanying drawings,
Fig. 1 is the structural representation of magnetic tunnel junction memory unit of the prior art;
Fig. 2 is the schematic diagram that prior art forms the top electrode opening of magnetic tunnel junction memory unit;
Fig. 3 A is the cutaway view according to the magnetic tunnel junction memory unit of one embodiment of the present invention;
Fig. 3 B is the cutaway view of the magnetic tunnel junction memory unit of another execution mode according to the present invention;
Fig. 4 A-4E shows the cutaway view of each step in the making flow process of magnetic tunnel junction memory unit of the implementation method according to the present invention;
Fig. 5 makes the flow chart of magnetic tunnel junction memory unit according to one embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, for technical characterictics more well known in the art, be not described.
In order thoroughly to understand the present invention, detailed structure and step will be proposed in following description, in order to magnetic tunnel junction memory unit of the present invention and manufacture method thereof are described, due to damaged the causing of dielectric layer, between upper/lower electrode, be electrically connected to avoiding.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet, except these are described in detail, the present invention can also have other execution modes.
Fig. 3 A is the cutaway view according to the magnetic tunnel junction memory unit of one embodiment of the present invention.Magnetic tunnel junction memory unit 300 comprises magnetic channel knot 320, side wall construction 380, top electrode 330 and bottom electrode 310.
Tie 320 both sides at magnetic channel and be formed with side wall construction 380, to prevent, in the opening process of top electrode 330 is held in etching formation, the dielectric layer between top electrode 330 and bottom electrode 310 is carried out to etching.
Preferably, the width sum of the width of side wall construction 380 (2d) and magnetic channel knot 320 is more than or equal to the width of top electrode 330, effectively to stop the etching of etching gas to dielectric layer in etching process.
Surround dielectric layer 350 around side wall construction 380, top electrode 330 and bottom electrode 310, insulated from each other with device on every side for making magnetic tunnel junction memory unit 300.Dielectric layer 350 is selected low-k materials usually, to improve, because characteristic size constantly reduces the increase with the metal connecting line depth-width ratio, causes the interconnection capacitance fast rise, and the problems such as crosstalking of causing.
Fig. 3 B is the cutaway view of the magnetic tunnel junction memory unit of another execution mode according to the present invention.Magnetic tunnel junction memory unit 300 also comprises 340， barrier layer 340, barrier layer between bottom electrode 310 is not by the upper surface of magnetic channel knot 320 coverings and magnetic channel knot 320 and side wall construction 380.The effect on barrier layer 340 is, the first, can prevent that dielectric layer 360 is diffused in magnetic channel knot 320 and pollutes magnetic channel knot 320; The second, can avoid the technique of follow-up formation side wall construction to cause damage to magnetic channel knot 320; The 3rd, barrier layer 340 can hold as follow-up making the etching stop layer of the opening of top electrode 330.The material on barrier layer 340 is nitride, and thickness is approximately the 100-500 dust.
The present invention also proposes a kind of method of manufacturing magnetic tunnel junction memory unit, comprising: bottom electrode is provided; Form the magnetic channel knot on bottom electrode; Form side wall construction in magnetic channel knot both sides; And tie the formation top electrode at magnetic channel.Below will specifically describe the manufacture method of the magnetic tunnel junction memory unit shown in Fig. 3 B.Fig. 4 A-4E shows the cutaway view of each step in the making flow process of magnetic tunnel junction memory unit of the implementation method according to the present invention.
As shown in Figure 4 A, provide bottom electrode 410, form magnetic channel knot 420 on bottom electrode 410.Preferably, magnetic channel knot 420 be positioned at bottom electrode 410 directly over.Bottom electrode 410 is surrounded by dielectric layer 450.Preferably, can also form the barrier layer 440 that covers bottom electrode 410 and magnetic channel knot 420, wherein, the material on barrier layer 440 is nitride, and thickness is the 100-500 dust.
In specifically describing be formed with the preferred implementation on barrier layer 440 on bottom electrode 410 and magnetic channel knot 420 below with reference to Fig. 4 B-4C, form the method for side wall construction.In other execution mode of the present invention, when not comprising the step that forms barrier layer 440, the various layer structure that below are formed on barrier layer 440 will be formed directly on bottom electrode 410 and magnetic channel knot 420.In other execution mode of the present invention, the method that forms described various layer structure is identical with method and the step introduced in following preferred implementation with step, therefore repeats no more.
As shown in Figure 4 B, form successively one deck oxide skin(coating) 481 and one deck nitride layer 482 on barrier layer 440.Wherein the thickness of oxide skin(coating) 481 is approximately the 100-300 dust, and the thickness of nitride layer 482 is approximately the 200-500 dust.The material of nitride layer 482 can be the silicon nitride of silicon nitride or carbon dope.
Alternatively, can on barrier layer 440, form at least one deck oxide skin(coating) and at least one deck nitride layer.At least every one deck in one deck oxide skin(coating) and at least every one deck alternative arrangement in one deck nitride layer, and innermost layer is oxide skin(coating).Described innermost layer is 440 nearest one decks from barrier layer.For instance, can on barrier layer 440, form successively oxide skin(coating), nitride layer and oxide skin(coating), or form successively oxide skin(coating), nitride layer, oxide skin(coating) and nitride layer on barrier layer 440, etc.
As shown in Figure 4 C, etching oxide layer 481 and nitride layer 482, tie 420 both sides at magnetic channel and form side wall construction 480.Can adopt dry etching to the etching of oxide skin(coating) 481 and the etching of nitride layer 482.For example, during etching oxide layer 481, main etching gas can be used CF
4.During the nitride layer 482 of etching, main etching gas can be used CO
2or CF
4.
As shown in Figure 4 D, form the opening 470 that holds top electrode on magnetic channel knot 420.Concrete steps are: form dielectric layer 460 on side wall construction 480 and barrier layer 440, and form opening 470 in dielectric layer 460, on magnetic channel knot 420, opening 470 is for holding top electrode.Preferably, opening 470 be positioned at magnetic channel knot 420 directly over.
As shown in Figure 4 E, at the interior filled conductive material of opening 470, form top electrode 430, complete the making of magnetic tunnel junction memory unit.
Fig. 5 makes the flow chart of magnetic tunnel junction memory unit according to one embodiment of the present invention.In step 501, bottom electrode is provided, form the magnetic channel knot on bottom electrode, tie the formation barrier layer at bottom electrode and magnetic channel.In step 502, form one deck oxide skin(coating) and one deck nitride layer on barrier layer.In step 503, etching oxide layer and nitride layer, form side wall construction in magnetic channel knot both sides.In step 504, form dielectric layer on side wall construction and barrier layer, and in dielectric layer, magnetic channel ties and forms the opening hold top electrode.In step 505, filled conductive material in opening, form top electrode, completes the making of magnetic tunnel junction memory unit.
Can be with well known to a person skilled in the art that any means forms above-mentioned various layer structure and other structures.Also it will be appreciated that, when mention certain one deck be positioned at another layer or substrate " on " or during D score, this layer can be located immediately at another layer or substrate " on " or D score, or also intermediate layer can appear therebetween.
In sum, magnetic tunnel junction memory unit according to the present invention comprises the side wall construction that is formed on magnetic channel knot both sides, therefore can prevent from, in the opening process of top electrode is held in etching formation, the dielectric layer between upper/lower electrode is carried out to etching.Wherein, the width sum of the width of side wall construction and magnetic channel knot is more than or equal to the width of top electrode, can in etching process, effectively stop the etching of etching gas to dielectric layer.In addition, magnetic tunnel junction memory unit can also comprise barrier layer, to prevent pollution and the damage of subsequent technique to the magnetic channel knot.This barrier layer can also hold as follow-up making the etching stop layer of the opening of top electrode.
Magnetic tunnel junction memory unit according to the present invention can be used for magnetic RAM.Due to the above magnetic tunnel junction memory unit of having described, and other parts are all known, therefore omit the structure according to magnetic RAM of the present invention is described.Magnetic RAM according to the present invention can be used for for example consumer electronic products, in the various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in radio frequency products.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the purpose for giving an example and illustrating just, but not is intended to the present invention is limited in described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, according to instruction of the present invention, can also make more kinds of variants and modifications, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (12)
1. a magnetic tunnel junction memory unit comprises:
Bottom electrode;
Top electrode, be positioned at the top of described bottom electrode;
The magnetic channel knot, be interposed between described bottom electrode and described top electrode;
Side wall construction, be formed on described magnetic channel knot both sides; And
Barrier layer, be formed on described bottom electrode not by between the upper surface of described magnetic channel knot covering and described magnetic channel knot and described side wall construction.
2. magnetic tunnel junction memory unit as claimed in claim 1, is characterized in that, the width sum of the width of described side wall construction and described magnetic channel knot is more than or equal to the width of described top electrode.
3. magnetic tunnel junction memory unit as claimed in claim 1, it is characterized in that, described side wall construction comprises at least one deck oxide skin(coating) and at least one deck nitride layer, every one deck alternative arrangement in every one deck in wherein said at least one deck oxide skin(coating) and described at least one deck nitride layer, and the innermost layer of described side wall construction is oxide skin(coating).
4. magnetic tunnel junction memory unit as claimed in claim 1, is characterized in that, described side wall construction comprises one deck oxide skin(coating) and one deck nitride layer, and the innermost layer of described side wall construction is oxide skin(coating).
5. magnetic tunnel junction memory unit as described as claim 3 or 4, is characterized in that, the silicon nitride that the material of described nitride layer is silicon nitride or carbon dope.
6. a method of manufacturing magnetic tunnel junction memory unit comprises:
Bottom electrode is provided;
Form the magnetic channel knot on described bottom electrode;
Tie the formation barrier layer at described bottom electrode and described magnetic channel;
Form side wall construction in described magnetic channel knot both sides;
Tie the formation top electrode at described magnetic channel, wherein, the method that forms described top electrode comprises:
Tie the formation dielectric layer at described bottom electrode and the described magnetic channel that is formed with described side wall construction;
Form opening directly over the knot of magnetic channel described in described dielectric layer;
Filled conductive material in described opening, form described top electrode.
7. method as claimed in claim 6, is characterized in that, the width sum of the width of described side wall construction and described magnetic channel knot is more than or equal to the width of described top electrode.
8. method as claimed in claim 6, is characterized in that, the method that forms described side wall construction comprises:
Tie and form at least one deck oxide skin(coating) and at least one deck nitride layer at described bottom electrode and described magnetic channel, every one deck alternative arrangement in every one deck in wherein said at least one deck oxide skin(coating) and described at least one deck nitride layer, and innermost layer is oxide skin(coating); And
Etching described at least one deck oxide skin(coating) and described at least one deck nitride layer, form described side wall construction.
9. method as claimed in claim 6, is characterized in that, the method that forms described side wall construction comprises:
Tie and form successively one deck oxide skin(coating) and one deck nitride layer at described bottom electrode and described magnetic channel; And
The described oxide skin(coating) of etching and described nitride layer, form described side wall construction.
10. method as claimed in claim 8 or 9, is characterized in that the silicon nitride that the material of described nitride layer is silicon nitride or carbon dope.
11. a magnetic RAM is characterized in that described magnetic RAM comprises magnetic tunnel junction memory unit as claimed in claim 1.
12. an electronic equipment that comprises magnetic RAM as claimed in claim 11, wherein said electronic equipment is selected from personal computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102632582A CN102376871B (en) | 2010-08-19 | 2010-08-19 | Magnetic tunnel junction memory unit and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102632582A CN102376871B (en) | 2010-08-19 | 2010-08-19 | Magnetic tunnel junction memory unit and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102376871A CN102376871A (en) | 2012-03-14 |
| CN102376871B true CN102376871B (en) | 2013-12-11 |
Family
ID=45795150
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010102632582A Active CN102376871B (en) | 2010-08-19 | 2010-08-19 | Magnetic tunnel junction memory unit and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102376871B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101515566A (en) * | 2008-02-18 | 2009-08-26 | 台湾积体电路制造股份有限公司 | Method for manufacturing integrated circuit |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100535046B1 (en) * | 2002-12-30 | 2005-12-07 | 주식회사 하이닉스반도체 | A method for manufacturing of a Magnetic random access memory |
| US7611912B2 (en) * | 2004-06-30 | 2009-11-03 | Headway Technologies, Inc. | Underlayer for high performance magnetic tunneling junction MRAM |
| JP2006261592A (en) * | 2005-03-18 | 2006-09-28 | Fujitsu Ltd | Magnetoresistive element and manufacturing method thereof |
| US7688615B2 (en) * | 2007-12-04 | 2010-03-30 | Macronix International Co., Ltd. | Magnetic random access memory, manufacturing method and programming method thereof |
-
2010
- 2010-08-19 CN CN2010102632582A patent/CN102376871B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101515566A (en) * | 2008-02-18 | 2009-08-26 | 台湾积体电路制造股份有限公司 | Method for manufacturing integrated circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102376871A (en) | 2012-03-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11538514B1 (en) | Writing scheme for 1TnC ferroelectric memory bit-cell with plate-lines parallel to a bit-line and with individual switches on the plate-lines of the bit-cell | |
| KR101551272B1 (en) | Mram device and integration techniques compatible with logic integration | |
| KR101382521B1 (en) | Spin torque driven magnetic tunnel junction with non-uniform current path and composite hardmask architecture for forming the same | |
| US8933521B2 (en) | Three-dimensional magnetic circuits including magnetic connectors | |
| WO2020206997A1 (en) | Three-dimensional vertical single transistor ferroelectric memory and manufacturing method thereof | |
| CN111354392A (en) | Magnetic memory array and read-write control method | |
| CN107316808A (en) | A kind of semiconductor devices and preparation method thereof, electronic installation | |
| CN102376871B (en) | Magnetic tunnel junction memory unit and manufacturing method thereof | |
| CN106997857B (en) | A kind of semiconductor devices and its detection structure, electronic device | |
| CN108886022B (en) | Memory element and method for manufacturing memory element | |
| EP4513493A1 (en) | Ferroelectric memory and control apparatus therefor, method for improving durability of ferroelectric memory, and device | |
| US12094511B1 (en) | Write disturb mitigation for column multiplexed non-linear polar material based multi-capacitor bit-cell | |
| US12300297B1 (en) | Memory array with buried or backside word-line | |
| CN220342757U (en) | Capacitor and memory | |
| KR102246246B1 (en) | Variable low resistance area based electronic device and controlling thereof | |
| CN117355139A (en) | memory structure | |
| CN106910679A (en) | A kind of semiconductor devices and preparation method thereof, electronic installation | |
| CN117082866A (en) | Method for improving morphology of grid etching process line in S ADP process | |
| TWI440168B (en) | Flash memory structure | |
| CN113328034A (en) | Storage unit and data writing and reading method thereof, memory and electronic equipment | |
| TW202232724A (en) | Semiconductor apparatus | |
| JP2010251371A (en) | Nonvolatile memory cell and manufacturing method thereof | |
| CN103066077A (en) | HIMOS FLASH memory cell structure and manufacturing method thereof | |
| CN102280451A (en) | Semiconductor device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20130105 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20130105 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |