CN102386080A - Method for forming metal gate - Google Patents
Method for forming metal gate Download PDFInfo
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- CN102386080A CN102386080A CN2010102751844A CN201010275184A CN102386080A CN 102386080 A CN102386080 A CN 102386080A CN 2010102751844 A CN2010102751844 A CN 2010102751844A CN 201010275184 A CN201010275184 A CN 201010275184A CN 102386080 A CN102386080 A CN 102386080A
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Abstract
The invention provides a method for forming a metal gate. The method comprises the following steps: providing a substrate with a formed gate dielectric layer; forming a sacrificial layer on the gate dielectric layer, wherein the sacrificial layer is doped with ions, the concentration of which is distributed in a gradient manner along with the thicknesses of the ions; etching the sacrificial layer to form a gate-replacing electrode layer which is provided with inclined side walls; forming a dielectric layer level to the surface of the gate-replacing electrode layer on the gate dielectric layer; removing the gate-replacing electrode layer to form a groove with the inclined side walls; and adopting filling materials to fill the groove and forming the metal gate. In the method, the gate-replacing electrode layer with the inclined side walls is formed by etching the sacrificial layer with the concentration of the doped ions being distributed in a gradient manner, and the groove with the inclined side walls is formed after the gate-replacing electrode layer is removed, so that the problems that the resistance value of the metal gate is higher than the target resistance value to be formed, and the higher resistance value causes the increase of power consumption are solved, and the reliability of a semiconductor device formed by the metal gate is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of formation method of metal gates.
Background technology
Along with the reduction of technology node, the continuous attenuation of traditional gate dielectric layer, the transistor leakage amount increases thereupon, causes problems such as semiconductor device power wastage.For addressing the above problem, prior art provides a kind of solution that metal gates is substituted polysilicon gate.Wherein, " back grid (gate last) " technology is for forming a main technique of metal gates.
Patent publication No. is that the one Chinese patent application of CN101438389A provides a kind of use " back grid " technology to form the method for metal gates; Comprise: substrate is provided, is formed with the alternative gate structure in the said substrate and is positioned at the interlayer dielectric layer that covers said alternative gate structure in the said substrate; As stopping layer, said interlayer dielectric layer is carried out CMP process with said alternative gate structure; Form groove after removing said alternative gate structure; At last to said trench fill medium and metal, to form gate dielectric layer and metal gate electrode layer.
Find in the practical application that the reliability of the semiconductor device that forms through technique scheme is lower.
Summary of the invention
The problem that the present invention solves provides a kind of formation method of metal gates, to solve the lower problem of reliability of the semiconductor device that adopts prior art formation.
For addressing the above problem, the present invention provides a kind of formation method of metal gates, comprising:
Substrate is provided, in said substrate, is formed with gate dielectric layer;
On said gate dielectric layer, form sacrifice layer, the thickness that said sacrifice layer has with sacrifice layer is the dopant ion that concentration gradient distributes;
The said sacrifice layer of etching forms the alternative gate electrode layer, and said alternative gate electrode layer has sloped sidewall;
On said gate dielectric layer, form dielectric layer, said dielectric layer surface flushes with the alternative gate electrode layer surface;
Remove said alternative gate electrode layer, form groove with sloped sidewall;
Adopt filler that said groove is filled, form metal gates.
Optional, said dopant ion is one or more in phosphorus, boron, arsenic, germanium or the silicon.
Optional, said Gradient distribution is that the concentration of dopant ion increases progressively with the thickness of sacrifice layer or with the thickness-tapered of sacrifice layer.
Optional, said Gradient distribution is linear distribution or nonlinear Distribution.
Optional, said sacrificial layer material is one of polysilicon, amorphous silicon, monocrystalline silicon, polycrystalline germanium, amorphous germanium, monocrystalline germanium, SiGe.
Optional, the etching technics of said sacrifice layer is for passing through the disposable completion of dry etch process.
Optional, the etching gas of said dry etching comprises one or more in chlorine, hydrogen bromide or the sulphur hexafluoride.
Optional, the sidewall of said alternative gate electrode layer and the said gate dielectric layer surface scope of acutangulating are 82 ° to 89 °.
Optional, the etching technics of said sacrifice layer is accomplished through dry etching and wet etching jointly, comprising: the said sacrifice layer of dry etching forms initial alternative gate electrode layer, and said initial alternative gate electrode layer has the sidewall perpendicular to gate dielectric layer; The said initial alternative gate electrode layer of wet etching forms the alternative gate electrode layer with sloped sidewall.
Optional, the solution of said wet etching is one of following solution: the mixed solution of hydrofluoric acid and nitric acid; Hydrofluoric acid solution; Potassium hydroxide solution; Tetramethyl ammonium hydroxide solution; Hydrogen peroxide solution; The mixed solution of hydrogen chloride and hydrogen peroxide solution; The mixed solution of ammoniacal liquor and hydrogen peroxide solution.
Optional, the sidewall of said alternative gate electrode layer and the said gate dielectric layer surface scope of acutangulating are 75 ° to 89 °.
Optional, said gate dielectric layer is one of silica, silicon oxynitride, silicon nitride or combination.
Optional, said gate dielectric layer is high K dielectric layer.
Compared with prior art; Such scheme has the following advantages: the present invention carries out etching through the sacrifice layer that the dopant ion concentration in gradient is distributed; It is little to form the bottom, and the alternative gate electrode layer that opening is big, have sloped sidewall forms the groove with sloped sidewall after removing the alternative gate electrode layer then; Metal gates produces the space after having avoided filler; Improve the quality of metal gates, avoid the resistance value higher and higher resistance value of target resistance values more to be formed of metal gates to cause problems such as power consumption rising, improve the reliability of the semiconductor device that contains said metal gates.
Description of drawings
Fig. 1 is that the metal gates of one embodiment of the invention forms the method flow sketch map.
Fig. 2 to Fig. 8 is the metal gates formation method structural representation of one embodiment of the invention.
Fig. 9 to Figure 10 is the metal gates formation method structural representation of another embodiment of the present invention.
Embodiment
The reliability of the semiconductor device that prior art forms is lower.The inventor finds; The reliability of semiconductor device is low to be because the resistance value of metal gates causes than target resistance values is higher; Further discovering it is because there is the space in the filler inside of said metal gates; The resistance value of metal gates can be improved in said space, makes it higher than target resistance values.
The inventor finds that further the reason that said space forms is following: in the prior art, the lateral vertical of alternative gate structure is in substrate; So the sidewall of removing the groove that said alternative gate structure forms is also perpendicular to said substrate; And the turning at said groove opening place is approximately the right angle, so when groove was filled, it was higher to be positioned near the deposition rate of opening; Low more the closer to bottom deposit speed, the space will appear in metal gates at last.Along with reducing of grid length, the size of groove also reduces thereupon, will more become difficult to trench fill, possibly form the space further.
For addressing the above problem, the present invention provides a kind of formation method of metal gates, and is as shown in Figure 1, comprising:
Step S1 provides substrate, is formed with gate dielectric layer in the said substrate;
Step S2 forms sacrifice layer on said gate dielectric layer, said sacrifice layer is doped with ion, and the ion concentration that said sacrifice layer mixes is with the thickness distribution gradient of sacrifice layer;
Step S3, the said sacrifice layer of etching forms the alternative gate electrode layer, and said alternative gate electrode layer has angled side walls;
Step S4 forms dielectric layer on said gate dielectric layer, said dielectric layer surface flushes with the alternative gate electrode layer surface;
Step S5 removes said alternative gate electrode layer, forms the groove with sloped sidewall;
Step S6 adopts filler that said groove is filled, and forms metal gates.
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, below in conjunction with accompanying drawing specific embodiment of the present invention done detailed explanation.
Fig. 2 to Fig. 8 is the metal gates formation method structural representation of one embodiment of the invention.
As shown in Figure 2, substrate 110 is provided, be formed with gate dielectric layer 120 in the said substrate 110.Also be formed with isolation structure 100 in the said substrate 110, be used to isolate the active area of follow-up formation.
Said substrate 110 can be selected from silicon (SOI) on silicon base, the insulating barrier, or can also be other material, for example III-V compounds of group such as GaAs.Said gate dielectric layer 120 is one of silica, silicon oxynitride, silicon nitride or combination.
Continuation forms sacrifice layer 130 with reference to figure 2 on said gate dielectric layer 120.The material of said sacrifice layer 130 is one of polysilicon, amorphous silicon, monocrystalline silicon, polycrystalline germanium, amorphous germanium, monocrystalline germanium, SiGe.
Said sacrifice layer 130 is doped with ion; Said dopant ion is corresponding as follows with the material of sacrifice layer 130: if the material of said sacrifice layer 130 is one of polysilicon, amorphous silicon, monocrystalline silicon, then said dopant ion can in phosphorus, boron, arsenic, the germanium one or more; If the material of said sacrifice layer 130 is one of polycrystalline germanium, amorphous germanium, monocrystalline germanium, then said dopant ion can in phosphorus, boron, arsenic, the silicon one or more; If the material of said sacrifice layer 130 is a SiGe, then said dopant ion can be in phosphorus, boron, the arsenic one or more.
Further, the ion doping concentration in the said sacrifice layer 130 is with the thickness distribution gradient of sacrifice layer 130, and to be ion concentration increase progressively or with the thickness-tapered of sacrifice layer 130 with the thickness of sacrifice layer 130 said Gradient distribution.Said Gradient distribution can also be linear distribution or nonlinear Distribution.
As an embodiment, said sacrifice layer 130 with concentration increasing or decreasing can be distinguished acquisition in the following manner:
1, has concentration through chemical vapour deposition technique formation and increase progressively sacrifice layer 130; Specifically comprise: in the time of deposition of sacrificial layer 130; Adopt impurity gas that sacrifice layer 130 is carried out ion doping; And along with the deposit thickness of said sacrifice layer 130 increases, increase the flow or the concentration of impurity gas gradually, form the sacrifice layer 130 that ion concentration increases progressively with the thickness of sacrifice layer 130.The top dopant ion concentration of said sacrifice layer 130 is maximum, and bottom dopant ion concentration is minimum.
The sacrifice polysilicon layer that increases progressively with the sacrifice polysilicon layer thickness with formation boron ion concentration is an example, when adopting existing technology to form the sacrifice polysilicon layer, adopts boron trifluoride (BF
3) the sacrifice polysilicon layer is mixed, along with the increase of polysilicon deposition thickness, increase boron trifluoride (BF
3) flow, form the sacrifice polysilicon layer that the boron ion concentration increases progressively with the sacrifice polysilicon layer thickness.
2, form through chemical vapour deposition technique and have the concentration sacrifice layer 130 that successively decreases; Specifically comprise: in the time of deposition of sacrificial layer 130; Adopt impurity gas that sacrifice layer 130 is carried out ion doping; And along with the deposit thickness of said sacrifice layer 130 increases, reduce the flow or the concentration of impurity gas gradually, form the sacrifice layer 130 of ion concentration with the thickness-tapered of sacrifice layer 130.The top dopant ion concentration of said sacrifice layer 130 is minimum, and bottom dopant ion concentration is maximum.
The sacrifice polysilicon layer that successively decreases with the sacrifice polysilicon layer thickness with the formation phosphate ion concentration is an example, when adopting existing technology to form the sacrifice polysilicon layer, adopts phosphine (PH
3) the sacrifice polysilicon layer is mixed, along with the increase of polysilicon deposition thickness, reduce phosphine (PH
3) flow, form the sacrifice polysilicon layer that phosphate ion concentration successively decreases with the sacrifice polysilicon layer thickness.
As shown in Figure 3, the hard mask layer 140 of formation patterning on said sacrifice layer 130, the pattern of said hard mask layer 140 is corresponding with the alternative gate electrode layer position of follow-up formation.
As shown in Figure 4, be mask with said hard mask layer 140, said sacrifice layer 130 is carried out etching, form alternative gate electrode layer 150.Along with the carrying out of etching, the sidewall of alternative gate electrode layer 150 will shrink gradually, finally obtain the alternative gate electrode layer 150 that a little top width of bottom width is big, have sloped sidewall.Through a large amount of creative work of inventor, find that the sidewall of said alternative gate electrode layer 150 is 82 ° to 89 ° with the acute angle scope that said gate dielectric layer 120 surfaces become, follow-up filling effect is more excellent.
Particularly, said etching gas comprises one or more in chlorine, hydrogen bromide or the sulphur hexafluoride.Wherein, distribute for having different ion concentration gradients, the selection of etching gas is different, specifically comprises:
1, the sacrifice layer 130 that successively decreases to the bottom from the top for ion concentration, the etching gas of selection has lower lateral etching rate to the higher sacrifice layer 130 of ion concentration, has higher lateral etching rate for the low more sacrifice layer 130 of ion concentration.Etching gas through having lateral etching rate difference obtains the alternative gate metal level 150 of top width greater than bottom width to the etching of sacrifice layer 130.
As an embodiment; With the dopant ion is phosphonium ion; The ion concentration of said sacrifice layer 130 is decremented to example, then can select bromize hydrogen gas that said sacrifice layer 130 is carried out etching, along with the etching process; Said etching gas lateral etching rate rate increases, and forms the alternative gate electrode layer 150 of top width greater than bottom width at last.The flow of said bromize hydrogen gas is 50sccm to 250sccm, and said etch period is 10 seconds to 100 seconds; The chamber pressure of said etching is 5 millitorr to 50 millitorrs; Said etching power is 500 watts to 1000 watts.
2, the sacrifice layer 130 that increases progressively to the bottom from the top for ion concentration, the etching gas of selection has lower lateral etching rate to the lower sacrifice layer 130 of ion concentration, has higher lateral etching rate for the high more sacrifice layer 130 of ion concentration.Through said etching, obtain the alternative gate metal level 150 of top width greater than bottom width with etching gas of lateral etching rate difference to sacrifice layer 130.
As shown in Figure 5, remove hard mask layer 140; Be mask then, in said substrate 110, form shallow ion doped region 161 with said alternative gate electrode layer 150; Then, on said alternative gate electrode layer 150 substrate on two sides 110, form side wall 170, and be mask, formation source/drain region 162 in said substrate 110 with said side wall 170.In other embodiments, also can directly carry out source/leakage ion and inject formation source/drain region alternative gate electrode layer 150 substrate on two sides 110; The formation in said source/drain region also can form technology with reference to existing source/drain region, does not here just give an example one by one.
As shown in Figure 6, metallization medium layer 180 on said gate dielectric layer 120, said dielectric layer 180 covers said alternative gate electrode layer 150; Follow with said alternative gate electrode layer 150 for stopping layer, to said dielectric layer 180 planarizations.
As shown in Figure 7, remove said alternative gate electrode layer 150, form groove 151.Because said alternative gate electrode layer 150 has angled side walls, also has angled side walls so remove the groove 151 of alternative gate electrode layer 150 back formation.In the present embodiment, the top width of said groove 151 is greater than bottom width, and is preferred, and its sidewall and the said gate dielectric layer 120 surface scopes of acutangulating are 82 ° to 89 °.
The removal method of said alternative gate electrode layer 150 can be dry etching or wet etching: if dry etching, can adopt comprise chloro, fluorine-based gas ions is carried out etching; If wet etching can adopt Ammonia to carry out etching and remove, perhaps also can adopt the mixed solution of nitric acid and hydrofluoric acid to carry out the etching removal.
As shown in Figure 8, adopt filler that said groove 151 is filled, form metal gate electrode layer 190.Said gate dielectric layer 120 constitutes metal gate structure with metal gate electrode layer 190.
Wherein, the material of said metal gate electrode layer 190 can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi.
In the present embodiment; Said gate dielectric layer 120 is the gate dielectric layer of metal gate structure; As other embodiment, can also adopt the gate dielectric layer of high K medium as metal gates, specifically comprise: before adopting filler that said groove 151 is filled; Remove said gate dielectric layer 120, expose the surface of substrate 110; Groove 151 to exposing substrate 110 surfaces is filled high K medium and metal successively, to form high-K gate dielectric layer and metal gates.
Said high K medium can be that hafnium oxide, hafnium silicon oxide, lanthana, lanthana aluminium, zirconia, zirconium silicon oxide, tantalum oxide, titanium oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, yittrium oxide, aluminium oxide, lead oxide scandium tantalum or lead niobate zinc etc. are a kind of.Said metal gate electrode layer material can be one or more of Al, Cu, Ag, Au, Pt, Ni, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, WSi.In the present embodiment; The formation method of said groove 151 is for forming through a step dry etching, and its processing step is simple, saves the technology cost; But a step dry etching usually faces the not high problem of etching precision; The difficult control of etching process, the present invention also provides a kind of formation method of metal gates, with further raising etching groove precision.
Fig. 9 to Figure 10 is the metal gates formation method structural representation of another embodiment of the present invention.
As shown in Figure 1, execution in step S1～S4, the specific embodiment of said step can be with reference to aforementioned, simultaneously with reference to figure 2～3.Form structure as shown in Figure 3; Comprise: substrate 110; Be positioned at the gate dielectric layer 120 and sacrifice layer 130 of said substrate 110, and be positioned at the hard mask layer 140 of patterning on the said sacrifice layer, the pattern of said hard mask layer 140 is corresponding with the alternative gate electrode layer position of follow-up formation.Also be formed with isolation structure 100 in the said substrate 110, be used to isolate the active area of follow-up formation.
As shown in Figure 9, be mask with said hard mask layer 140, said sacrifice layer 130 is carried out etching, form initial alternative gate electrode layer 210.The sidewall of said initial alternative gate electrode layer 210 is perpendicular to said gate dielectric layer 120.
Said etching technics can be existing etching technics, and particularly, the etching gas of selection can be one or more in chlorine, hydrogen bromide or the sulphur hexafluoride.Said etching gas is insensitive to the ion concentration gradient of sacrifice layer 130, and etching forms sidewall perpendicular to said gate dielectric layer 120.
Shown in figure 10, said initial alternative gate electrode layer 210 is revised, form alternative gate electrode layer 250.The said wet etching that is modified to.Said alternative gate electrode layer 250 has sloped sidewall, and the little top width of its bottom width is big.Wherein, the sidewall of said alternative gate electrode layer 250 and the said gate dielectric layer 120 surface scopes of acutangulating are 75 ° to 89 °.
Also need to prove; Adopt first etching to form the alternative gate electrode layer of vertical sidewall in the present embodiment; Adopt wet-etching technology to form the alternative gate electrode layer with sloped sidewall again, it is accurate to have etching, the high advantage of alternative gate electrode layer precision with sloped sidewall of formation.And compare with the sidewall that a step dry etching forms, the acute angle scope that the sidewall that wet etching forms behind the first dry etching of said employing is become with gate dielectric layer is bigger.
The solution of said wet etching is one of following solution: the mixed solution of hydrofluoric acid and nitric acid; Hydrofluoric acid solution; Potassium hydroxide solution; Tetramethyl ammonium hydroxide solution; Hydrogen peroxide solution; The mixed solution of hydrogen chloride and hydrogen peroxide solution; The mixed solution of ammoniacal liquor and hydrogen peroxide solution.Wherein, distribute for having different ion concentration gradients, the selection of said etching solution is different, specifically comprises:
1, the sacrifice layer 130 that successively decreases to the bottom from the top for ion concentration, the etching solution of selection has lower lateral etching rate to the higher sacrifice layer 130 of ion concentration, has higher lateral etching rate for the lower etching sacrificial layer 130 of ion concentration.Etching solution through having lateral etching rate difference obtains the alternative gate metal level 150 of top width greater than bottom width to the etching of sacrifice layer 130.
As an embodiment; With the dopant ion is phosphonium ion; The ion concentration of said sacrifice layer 130 is decremented to example from the top to the bottom, then can select the mixed solution of hydrofluoric acid and nitric acid that said sacrifice layer 130 is carried out etching, along with the etching process; The mixed solution of hydrofluoric acid and nitric acid has lateral etching rate difference, forms the alternative gate electrode layer 150 of top width greater than bottom width at last.Mixing ratio in the mixed solution of said hydrofluoric acid and nitric acid is 5: 1, and said etch period is 10 seconds to 100 seconds.
2, the sacrifice layer 130 that increases progressively to the bottom from the top for ion concentration, the etching solution of selection has lower lateral etching rate to the lower sacrifice layer 130 of ion concentration, has higher lateral etching rate for the higher sacrifice layer 130 of ion concentration.Through said etching, obtain the alternative gate metal level 150 of top width greater than bottom width with etching solution of lateral etching rate difference to sacrifice layer 130.
Formation has after the alternative gate electrode layer 250 of sloped sidewall; Also be included in metallization medium layer on the said gate dielectric layer, remove alternative gate electrode layer formation groove, adopt the filler filling groove to form steps such as metal gate electrode layer; Said step can just not be described in detail with reference to aforementioned here.
The present invention carries out etching through the sacrifice layer that the dopant ion concentration in gradient is distributed; Utilize etching gas or etching solution the sacrifice layer of ion concentration distribution gradient to be had the difference of the lateral etching rate relevant simultaneously with ion concentration; It is little to form the bottom, and the alternative gate electrode layer that opening is big, have sloped sidewall forms the groove with sloped sidewall after removing the alternative gate electrode layer then; Metal gates produces the space after having avoided filler, improves the quality of metal gates.Further, the alternative gate electrode layer that the present invention adopts etching technics once to form to have sloped sidewall, it is simple to have technology, and the advantage that processing step is practiced thrift is enhanced productivity; The present invention adopts first etching to form the alternative gate electrode layer of vertical sidewall, adopts wet-etching technology to form the alternative gate electrode layer with sloped sidewall again, and it is accurate to have etching, the high advantage of alternative gate electrode layer precision with sloped sidewall of formation.
Set forth detail in the following description so that make much of the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization under the situation of intension of the present invention.Therefore the present invention does not receive the restriction of following disclosed practical implementation.
Claims (13)
1. the formation method of a metal gates is characterized in that, comprising:
Substrate is provided, is formed with gate dielectric layer in the said substrate;
On said gate dielectric layer, form sacrifice layer, the thickness that said sacrifice layer has with sacrifice layer is the dopant ion that concentration gradient distributes;
The said sacrifice layer of etching forms the alternative gate electrode layer, and said alternative gate electrode layer has sloped sidewall;
On said gate dielectric layer, form dielectric layer, said dielectric layer surface flushes with the alternative gate electrode layer surface;
Remove said alternative gate electrode layer, form groove with sloped sidewall;
Adopt filler that said groove is filled, form metal gates.
2. according to the formation method of the said metal gates of claim 1, it is characterized in that said dopant ion is one or more in phosphorus, boron, arsenic, germanium or the silicon.
3. according to the formation method of the said metal gates of claim 1, it is characterized in that said Gradient distribution is that the concentration of dopant ion increases progressively with the thickness of sacrifice layer or with the thickness-tapered of sacrifice layer.
4. according to the formation method of the said metal gates of claim 3, it is characterized in that said Gradient distribution is linear distribution or nonlinear Distribution.
5. according to the formation method of the said metal gates of claim 1, it is characterized in that said sacrificial layer material is one of polysilicon, amorphous silicon, monocrystalline silicon, polycrystalline germanium, amorphous germanium, monocrystalline germanium, SiGe.
6. according to the formation method of the said metal gates of claim 1, it is characterized in that the etching technics of said sacrifice layer is for passing through the disposable completion of dry etch process.
7. according to the formation method of the said metal gates of claim 6, it is characterized in that the etching gas of said dry etching comprises one or more in chlorine, hydrogen bromide or the sulphur hexafluoride.
8. according to the formation method of the said metal gates of claim 7, it is characterized in that the sidewall of said alternative gate electrode layer and the said gate dielectric layer surface scope of acutangulating are 82 ° to 89 °.
9. according to the formation method of the said metal gates of claim 1; It is characterized in that; The etching technics of said sacrifice layer is accomplished through dry etching and wet etching jointly; Comprise: the said sacrifice layer of dry etching forms initial alternative gate electrode layer, and said initial alternative gate electrode layer has the sidewall perpendicular to gate dielectric layer; The said initial alternative gate electrode layer of wet etching forms the alternative gate electrode layer with sloped sidewall.
10. according to the formation method of the said metal gates of claim 9, it is characterized in that the solution of said wet etching is one of following solution: the mixed solution of hydrofluoric acid and nitric acid; Hydrofluoric acid solution; Potassium hydroxide solution; Tetramethyl ammonium hydroxide solution; Hydrogen peroxide solution; The mixed solution of hydrogen chloride and hydrogen peroxide solution; The mixed solution of ammoniacal liquor and hydrogen peroxide solution.
11. the formation method according to the said metal gates of claim 10 is characterized in that, the sidewall of said alternative gate electrode layer and the said gate dielectric layer surface scope of acutangulating are 75 ° to 89 °.
12. the formation method according to the said metal gates of claim 1 is characterized in that, said gate dielectric layer is one of silica, silicon oxynitride, silicon nitride or combination.
13. the formation method according to the said metal gates of claim 1 is characterized in that, said gate dielectric layer is high K dielectric layer.
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| CN103864004A (en) * | 2012-12-07 | 2014-06-18 | 精工爱普生株式会社 | Method for producing oscillator |
| US8835237B2 (en) | 2012-11-07 | 2014-09-16 | International Business Machines Corporation | Robust replacement gate integration |
| CN104658895A (en) * | 2013-11-15 | 2015-05-27 | 中国科学院微电子研究所 | Method for forming sacrificial gate body with improved section and method for manufacturing semiconductor device |
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| CN103367133A (en) * | 2012-03-29 | 2013-10-23 | 中芯国际集成电路制造(上海)有限公司 | High-dielectric-constant metal gate production method |
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| CN103515197A (en) * | 2012-06-26 | 2014-01-15 | 中芯国际集成电路制造(上海)有限公司 | Self-aligned multi-patterning mask layer and formation method thereof |
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| CN103864004A (en) * | 2012-12-07 | 2014-06-18 | 精工爱普生株式会社 | Method for producing oscillator |
| CN103864004B (en) * | 2012-12-07 | 2017-04-12 | 精工爱普生株式会社 | Method for producing oscillator |
| CN104658895A (en) * | 2013-11-15 | 2015-05-27 | 中国科学院微电子研究所 | Method for forming sacrificial gate body with improved section and method for manufacturing semiconductor device |
| CN104658895B (en) * | 2013-11-15 | 2017-10-17 | 中国科学院微电子研究所 | Method for forming sacrificial gate body with improved section and method for manufacturing semiconductor device |
| CN110148596A (en) * | 2018-02-12 | 2019-08-20 | 联华电子股份有限公司 | Bit line gate structure of dynamic random access memory and forming method thereof |
| CN110148596B (en) * | 2018-02-12 | 2020-11-10 | 联华电子股份有限公司 | Bit line gate structure of dynamic random access memory and method of forming the same |
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