CN102394633B - Low power consumption asynchronous comparison gate for low density parity code (LDPC) decoder - Google Patents

Abstract

The invention provides a low power consumption asynchronous comparison gate for a low density parity code (LDPC) decoder, which comprises an asynchronous comparator, an asynchronous gate and a delay circuit, wherein the asynchronous comparator is used for receiving two input signals to be operated according to a work control signal, for outputting a completion signal and for comparing a result signal; the asynchronous gate is used for receiving a first input signal and a second input signal as well as a selection signal and a pre-charging signal; the asynchronous gate operates the first input signal and the second input signal according to the selection signal and the pre-charging signal to produce a first output result and a second output result; and the delay circuit is used for delaying and inputting the matched completion signal of the asynchronous comparator to the asynchronous gate to be used as the pre-charging signal of the asynchronous gate. The asynchronous comparison gate is free from producing a transitional signal and burrs and has the advantages of stable data and low power consumption.

Description

A Low Power Asynchronous Compare Strobe for LDPC Decoder

technical field

The invention mainly relates to the field of electronic technology, in particular to the structure and circuit realization of a low-power consumption asynchronous comparison gate used in an LDPC decoder.

Background technique

After integrated circuit (IC) design enters deep submicron process technology, power consumption has gradually become a factor that people consider and pay attention to. Especially portable electronic devices that rely on battery power, such as mobile phones, notebook computers, etc., are in urgent need of low power consumption design. Therefore, low-power design has become an important direction of integrated circuit design, which runs through the entire integrated circuit design process from system design, logic design to physical design and process implementation. LDPC codes are widely used in mobile communication standards due to their excellent performance. LDPC codes have a large amount of calculations, and the comparison gate operation is the main operation, accounting for more than 80% of the calculations. Therefore, the comparison strobe consumes most of the power consumption of the entire decoder, and its low power consumption design is of great significance to reduce the power consumption of the LDPC decoder.

The synchronous comparison strobe is directly connected by the synchronous comparator and the synchronous strobe. Its calculation characteristics are: the data generated by the synchronous comparator through the operation is not synchronized with the data input to the synchronous strobe, which will generate Transition signals and glitches are passed to the next stage of operation, thus increasing unnecessary power consumption. In response to this problem, it is urgent to design a low-power comparison strobe, so that the data generated by the comparator and the input of the strobe are synchronously operated without generating transition signals and glitches, so as to solve the shortcomings of synchronous design, and Reduce power consumption.

Contents of the invention

The purpose of the present invention is to overcome the above-mentioned deficiency that prior art exists, provide a kind of low power consumption asynchronous comparison strobe used for LDPC decoder, replace clock signal by using unified work control signal, make data stable, will not A transition signal or a glitch signal is generated, so as to achieve the purpose of reducing power consumption.

In order to achieve the above object, the present invention provides the following technical solutions:

A low-power asynchronous compare strobe for LDPC decoders comprising:

An asynchronous comparator is used to receive two input signals, perform operations according to the work control signal, and output a completion signal and a comparison result signal, and the two input data are respectively the first input signal and the second input signal;

An asynchronous gate for receiving the first input signal and the second input signal, a selection signal and a precharge signal, wherein the selection signal is a comparison result signal generated by the asynchronous comparator, and the precharge signal is generated by the asynchronous comparator The completion signal is obtained after passing through the delay circuit; the asynchronous gate operates on the first input signal and the second input signal according to the selection signal and the pre-charge signal, and generates the first output result and the second output result;

The delay circuit is used for inputting the matched delay of the completion signal of the asynchronous comparator to the asynchronous strobe as a precharge signal of the asynchronous strobe.

The above-mentioned low-power asynchronous comparison strobe used for LDPC decoders, wherein the asynchronous comparator is composed of a completion signal detection unit and at least one two-bit asynchronous comparison unit; after more than two asynchronous comparison units are cascaded Completing the signal detection unit to form a multi-bit asynchronous comparator, the asynchronous comparator generates a completion signal and two comparison result signals by the completion signal detection unit, and the two comparison result signals are respectively output signals that are greater than or equal to the result and The result is an output signal that is less than .

The above-mentioned low-power asynchronous comparison gate for LDPC decoder, wherein the asynchronous gate is formed by cascading asynchronous 2-to-2 gate units; the comparison result signal generated by the asynchronous comparator is used as the selection signal of the asynchronous gate ; The completion signal generated by the asynchronous comparator is used as the precharge signal of the asynchronous gate after passing through the delay circuit; finally, the first output signal and the second output signal are obtained through operation. Wherein the first output signal is the larger signal among the input signals, and the second output signal is the smaller signal.

In the above-mentioned low-power asynchronous comparison strobe used for LDPC decoders, the delay circuit is composed of a basic inverter chain, and the completion signal generated by the asynchronous comparator is connected to the asynchronous strobe through the delay circuit , as a precharge signal for the asynchronous gate.

Compared with the prior art, the present invention has the following advantages and technical effects: the asynchronous comparison gate of the present invention utilizes the characteristics of the asynchronous circuit structure to stabilize data through a unified signal. At the same time, since the completion signal generated by the comparator is input to the strobe through the matching delay circuit as the precharge signal of the strobe, the asynchronous comparison strobe composed in this way will not generate transition signals and glitches. In addition, the asynchronous comparator and the asynchronous gate have advantages in power consumption compared with the synchronous comparator and the synchronous gate. Therefore, the present invention reduces power consumption compared to synchronous compare gates.

Description of drawings

Fig. 1 is the structural diagram of the asynchronous comparison selector of low power consumption;

Fig. 2 is a structural diagram of an asynchronous comparator;

Fig. 3 is a structural diagram of two asynchronous comparison units;

Fig. 4 is the structural diagram of the completion signal detection unit of asynchronous comparator;

Fig. 5 is a structural diagram of an asynchronous 2-to-2 gating unit.

Detailed ways

In order to make it easier for those skilled in the art to implement the present invention, the implementation of the present invention will be further described below in conjunction with the drawings and specific embodiments, but the implementation and protection scope of the present invention are not limited thereto.

The structure of the low-power asynchronous comparison selector used in LDPC is shown in Figure 1, which consists of an asynchronous comparator 1, an asynchronous gating device 2 and a set of delay circuits 3 composed of basic delay units. The first input signal and the second input signal are connected to the asynchronous comparator 1 and the asynchronous gate 2 respectively, and the working control signal is connected to the asynchronous comparator 1 . After the operation of the asynchronous comparator 1, a completion signal and a comparison result signal are obtained. The comparison result signal is directly connected to the selection signal input terminal of the asynchronous strobe 2 as the selection signal of the asynchronous strobe 2, and the completion signal is connected to the asynchronous strobe through a group of delay circuits 3 composed of basic delay units. The precharge signal terminal of the gate 2 is used as the precharge signal of the asynchronous gate 2. The operation or clearing of the asynchronous gate 2 is determined by the precharge signal, and the selection of the first input signal and the second input signal is determined by the selection signal. After the operation of the asynchronous gate 2, the first output signal and the second output signal are finally output. Wherein, the first output signal is the larger signal of the first input signal and the second input signal, and the second output signal is the larger signal of the first input signal and the second input signal.

FIG. 2 is a structural diagram of an asynchronous comparator, which is composed of at least one two-bit asynchronous comparison unit and a completion signal detection unit. More than two asynchronous comparison units are cascaded together with the completion signal detection unit to form a multi-bit asynchronous comparator. The precharge signal is connected to each two-bit asynchronous comparison unit and the completion signal detection unit, and the input signal is only connected to the two-bit asynchronous comparison unit. The equal output signal of each asynchronous comparison unit except the lowest bit is connected to the asynchronous comparison unit of the next bit, and the equal output signal of the lowest asynchronous comparator unit is directly connected to the completion signal detection unit. And all two asynchronous comparison units are greater than the output signal (comprising greater than the output signal [N-1], greater than the output signal [N-2], ..., greater than the output signal [K], ..., greater than the output signal [0] ]) and less than the output signal (including less than the output signal [N-1], less than the output signal [N-2], ..., less than the output signal [K], ..., less than the output signal [0]) are connected to the completion on the signal detection unit. The first input signal and the second input signal are used as input signals, directly input to the two-bit asynchronous comparison unit, and the operation starts from the high bit. If the high bits of the two are equal, the equal output signal of this bit is valid, and it is input to the next bit. Compare in an asynchronous compare unit. If the high bits of the two are not equal, the equal output signal is 0, and all the low-order asynchronous comparison units behind this bit will not perform operations. The completion signal detection unit generates a completion signal, a greater than or equal output signal, and a less than output signal through calculation according to all the output signals greater than the output signal, less than the output signal, and the lowest bit. This circuit structure can guarantee the following characteristics. For a multi-bit input signal, if the comparison result of the first input signal and the second input signal can be obtained at the high bit, then the entire asynchronous comparator can immediately obtain the corresponding comparison result and completion signal. .

和

输出信号有三个，分别是大于输出信号、相等输出信号和小于输出信号。输出端均由一对PMOS管并联，加上一个弱反馈负载反相器构成，其中一个PMOS管的栅极作为预充电信号的输入端，另外一个PMOS管的栅极连接到弱反馈负载反相器，形成反馈回路，并作为三种输出信号的输出端。该结构的下拉电路的构成规则与一般的CMOS组合逻辑电路设计相同，NMOS管串联实现逻辑“与”功能，NMOS管并联实现逻辑“或”功能。其中，对于输出端为大于输出信号的支路，输入信号分别是预充电信号、相等输入信号、A₁A₀和

实现以下逻辑表达式：大于输出信号＝预充电信号

对于输出端为相等输出信号的支路，输入信号分别是预充电信号、相等输入信号、A₁A₀、B₁B₀、

和

实现以下逻辑表达式：相等输出信号＝预充电信号g相等输入信号

对于小于输出信号，输入信号分别是预充电信号、相等输入信号、

和B₁B₀，实现以下逻辑表达式：在下拉电路中，相等输入信号连接到位于最接近输出端的NMOS管的栅极，并且由

组成的NMOS管和预充电信号作为栅极的NMOS管是三段支路共用的。整个的两位异步比较单元实现的功能如下：当预充电信号或者相等输入信号有一个为低电平，该电路不运算；当预充电信号和相等输入信号均为高电平时，电路进行工作。若A₁A₀大于B₁B₀，则大于输出信号为高电平，相等输出信号和小于输出信号均为低电平；若A₁A₀小于B₁B₀，则小于输出信号为高电平，大于输出信号和相等输出信号均为低电平；若A₁A₀等于B₁B₀，则相等输出信号为高电平，大于输出信号和小于输出信号均为低电平。The structure of two asynchronous comparison units is shown in Figure 3. This structure adopts a dynamic logic circuit, and the input signals are precharge signal, equal input signal, A ₁ A ₀ , B ₁ B ₀ , and the inverted

and

There are three output signals, which are greater than the output signal, equal to the output signal, and less than the output signal. The output terminals are composed of a pair of PMOS transistors connected in parallel, plus a weak feedback load inverter. The gate of one of the PMOS transistors is used as the input terminal of the pre-charge signal, and the gate of the other PMOS transistor is connected to the weak feedback load inverter. device, forming a feedback loop, and as the output of the three output signals. The composition rule of the pull-down circuit of this structure is the same as that of the general CMOS combinational logic circuit design, the NMOS transistors are connected in series to realize the logical "AND" function, and the NMOS transistors are connected in parallel to realize the logical "OR" function. Among them, for the branch whose output terminal is greater than the output signal, the input signals are precharge signal, equal input signal, A ₁ A ₀ and

Realize the following logical expression: greater than output signal = precharge signal

For branches whose outputs are equal output signals, the input signals are precharge signal, equal input signal, A ₁ A ₀ , B ₁ B ₀ ,

and

Realize the following logical expression: equal output signal = precharge signal g equal input signal

For less than the output signal, the input signals are the precharge signal, equal input signal,

and B ₁ B ₀ , realize the following logical expression: In a pull-down circuit, the equal input signal is connected to the gate of the NMOS transistor located closest to the output, and is determined by

The composed NMOS transistor and the NMOS transistor used as the gate for the precharge signal are shared by the three branches. The functions realized by the entire two-bit asynchronous comparison unit are as follows: when one of the precharge signal or the equal input signal is low level, the circuit does not operate; when the precharge signal and the equal input signal are both high level, the circuit operates. If A ₁ A ₀ is greater than B ₁ B ₀ , the greater than output signal is high level, and the equal output signal and less than output signal are both low level; if A ₁ A ₀ is less than B ₁ B ₀ , the less than output signal is high Level, the greater than output signal and the equal output signal are both low level; if A ₁ A ₀ is equal to B ₁ B ₀ , the equal output signal is high level, and the greater than output signal and less than output signal are both low level.

The structure of the completed signal detection unit is shown in Figure 4. The structure consists of two parts of dynamic logic circuits and an AND gate. The output signals of the two parts of the dynamic logic circuit are respectively greater than or equal to the output signal and less than the output signal, both of which are composed of a pair of PMOS transistors connected in parallel, plus a weak feedback load inverter, and the gate of one of the PMOS transistors is used as a precharge The input terminal of the signal, and the gate of the other PMOS transistor are connected to the weak feedback load inverter to form a feedback loop and serve as the output terminal. For greater than or equal output signals, the pull-down circuit is N+1 NMOS transistors connected in parallel, connected in series with an NMOS transistor whose gate is a precharge signal, and the gates of the N NMOS transistors are respectively N greater than the output signal (including Greater than the output signal [N-1], greater than the output signal [N-2], ..., greater than the output signal [0]), the gate of the other NMOS transistor is an equal output signal. For less than the output signal, the pull-down circuit is N NMOS transistors connected in parallel, connected in series with an NMOS transistor whose grid is a precharge signal, and the gates of the N NMOS transistors are respectively N less than the output signal (including less than the output signal [ N-1], less than output signal [N-2], ..., less than output signal [0]). The outputs of these two parts of the dynamic logic circuit are respectively connected to the AND gate, and finally a completion signal is generated.

Fig. 5 is a structural diagram of an asynchronous 2-to-2 gating unit. The structure adopts a dynamic logic circuit, and the input signals are precharge signal, selection signal, inversion signal of selection signal, A and B respectively. The output signals are the first output signal and the second output signal. As mentioned earlier, the output terminals are composed of a pair of PMOS transistors connected in parallel and a weak feedback load inverter. The gate of one of the PMOS transistors is used as the input terminal of the pre-charge signal, and the gate of the other PMOS transistor is connected to the The weak feedback load inverter forms a feedback loop and serves as the output terminal of the output signal. Wherein, for the branch whose output terminal is the first output signal, its pull-down circuit realizes the following logic expression:

The first output signal=precharge signal g[Ag selection signal+Bg selection signal negates signal)]; For the branch circuit that the output terminal is the second output signal, its pull-down circuit realizes following logical expression: the first output signal=precharge Charging signal g [Ag selection signal negation signal + Bg selection signal)]. In the pull-down circuit, a common precharge signal is used as the NMOS transistor of the gate. The functions realized by the entire asynchronous 2-to-2 gating unit are as follows: when the pre-charge signal is low, the circuit does not operate; when the pre-charge signal is high, if the selection signal is high, the first output signal output is A , the output of the second output signal is B; if the selection signal is low, the output of the first output signal is B, and the output of the second output signal is A.

The present invention uses a unified work control signal to replace the clock signal in the synchronous circuit, so that the data is stable, so that in the synchronous comparison strobe, the data of the comparator and the strobe are not synchronized, and then a transition signal is generated and glitch phenomenon, thereby reducing power consumption.

Claims (4)

1. a low power consumption asynchronous comparison selector for LDPC decoder, is characterized in that comprising: An asynchronous comparator is used to receive two input signals, perform operations according to the work control signal, and output a completion signal and a comparison result signal, and the two input data are respectively the first input signal and the second input signal; An asynchronous gate for receiving the first input signal and the second input signal, a selection signal and a precharge signal, wherein the selection signal is a comparison result signal generated by the asynchronous comparator, and the precharge signal is generated by the asynchronous comparator The completion signal is obtained after passing through the delay circuit; the asynchronous gate operates on the first input signal and the second input signal according to the selection signal and the pre-charge signal, and generates the first output result and the second output result; The delay circuit is used for inputting the matched delay of the completion signal of the asynchronous comparator to the asynchronous strobe as a precharge signal of the asynchronous strobe. 2. the low power consumption asynchronous comparison strobe used for LDPC decoder according to claim 1, is characterized in that, wherein asynchronous comparator is made of a complete signal detection unit and at least one asynchronous comparison unit of two bits; two More than two asynchronous comparison units are cascaded to form a multi-bit asynchronous comparator with the completion signal detection unit, and the asynchronous comparator generates a completion signal and two comparison result signals by the completion signal detection unit, and the two comparison result signals are the output signals where the result is greater than or equal and the output signal where the result is less than, respectively. 3. the low power consumption asynchronous comparison strobe for LDPC decoder according to claim 1, is characterized in that, wherein asynchronous strobe adopts asynchronous 2 to select 2 strobe unit cascading to form; Asynchronous comparator produces The comparison result signal is used as the selection signal of the asynchronous strobe; the completion signal generated by the asynchronous comparator is used as the pre-charge signal of the asynchronous strobe after passing through the delay circuit; finally, the first output signal and the second output signal are obtained through operation . 4. the low power consumption asynchronous comparison strobe used for LDPC decoder according to claim 1, is characterized in that, delay circuit adopts basic inverter chain to form, the completion signal that asynchronous comparator produces is through time delay circuit, connected to the asynchronous gate, as a pre-charge signal for the asynchronous gate.

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