CN102402082B - Liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

The present invention provides a method for manufacturing a liquid crystal display device, wherein a contact hole for electrically connecting a pixel electrode to one of a source electrode and a drain electrode of a transistor and a contact hole for processing a semiconductor layer are simultaneously formed. This method helps reduce the number of optical imaging steps. The transistor includes an oxide semiconductor layer having a channel formation region formed therein.

Description

Liquid crystal display device and manufacturing method thereof

technical field

The present invention relates to a method for manufacturing thin film transistors and liquid crystal display devices.

Background technique

In recent years, there has been a strong need to reduce the cost, thickness, and weight of liquid crystal display devices.

As one method of achieving cost reduction of the liquid crystal display device, simplification of the manufacturing process of the liquid crystal display device can be given.

Driving methods of liquid crystal display devices are broadly classified into passive matrix methods and active matrix methods. In recent years, active matrix liquid crystal display devices excellent in image quality and high-speed response have become mainstream.

In an active matrix liquid crystal display device, each pixel is provided with a switching element. Thin film transistors are mainly used as switching elements. As such thin film transistors, there are given a top gate transistor in which a channel formation region is provided below a gate electrode and a bottom gate transistor in which a channel formation region is provided above a gate electrode. These thin film transistors are typically fabricated using at least five layers of photomasks.

Reducing the number of photomasks as much as possible is an important factor in manufacturing liquid crystal display devices at a lower cost. In order to reduce the number of photomasks, complex techniques such as backside exposure (eg, see Patent Document 1), resist reflow, or a lift-off method requiring special equipment are used in many cases. Use of such complicated technology may cause various problems such as a decrease in yield of liquid crystal display devices and deterioration of electrical characteristics of thin film transistors.

Furthermore, as a method of achieving reduction in thickness and weight of a liquid crystal display device, reduction in thickness of a substrate interposing a liquid crystal material by mechanical polishing, chemical polishing, or the like is given.

A glass substrate is mainly used as a substrate sandwiching a liquid crystal material, and thus there is a limit to reducing the thickness of such a substrate by mechanical polishing, chemical polishing, or the like. In addition, there is a problem that as the thickness of such a substrate decreases, the strength of the substrate also decreases, and the liquid crystal display device is more likely to be damaged by external impact. Therefore, it is desirable to manufacture a liquid crystal display device using a remarkably strong support such as a resin film and a metal film as a substrate sandwiching a liquid crystal material.

[references]

[Patent Document 1] Japanese Laid-Open Patent Application No. H05-203987

Contents of the invention

The present invention is made in view of the above technical background. Therefore, it is an object of one embodiment of the present invention to reduce the number of photomasks compared to conventional cases without requiring complex techniques or special devices. Another object of an embodiment of the present invention is to provide a method of manufacturing a liquid crystal display device that is thin, lightweight, and not easily broken.

That is to say, one embodiment of the present invention is a method of manufacturing a liquid crystal display device, which includes the following steps: forming a separation layer on a substrate; forming a first conductive layer on the separation layer; forming a second conductive layer on the first conductive layer a resist mask; using the first resist mask to partially remove the first conductive layer to form a gate electrode; forming a first insulating layer as a gate insulating layer on the gate electrode; forming a semiconductor layer on the first insulating layer layer; forming a second conductive layer on the semiconductor layer; forming a second resist mask on the second conductive layer; partially removing the second conductive layer using the second resist mask to form a source electrode and a drain electrode, Thus, a transistor including a gate electrode, a source electrode, and a drain electrode is manufactured; a second insulating layer serving as a protective insulating layer is formed so that the second insulating layer covers the source electrode, the drain electrode, and the semiconductor layer; and a second insulating layer is formed on the second insulating layer. Three resist masks; use the third resist mask to selectively remove the part of the second insulating layer overlapping with the drain electrode to form the first opening, and at the same time use the third resist mask to remove the portion not connected to the source electrode A part of the second insulating layer, a part of the semiconductor layer and a part of the first insulating layer overlapped by the electrode or the drain electrode to form the second opening; and a third conductive layer is formed so that the third conductive layer covers the first opening, the second opening and the second opening. forming a fourth resist mask on the third conductive layer; and partially removing the third conductive layer using the fourth resist mask to form a pixel electrode.

According to an embodiment of the present invention, the step of forming the first opening serving as the contact hole and the step of etching the semiconductor layer are performed simultaneously, whereby a thin film transistor can be manufactured using a smaller number of photomasks than conventionally used, And layers including thin film transistors may be separated from the substrate.

In a method of manufacturing a liquid crystal display device, according to one embodiment of the present invention, a base layer is formed on a substrate and is in contact with a separation layer.

According to the embodiments of the present invention, diffusion of impurity elements from the substrate can be suppressed. Therefore, changes in the characteristics of the thin film transistor due to the diffusion of impurity elements into the semiconductor layer can be suppressed.

In a method of manufacturing a liquid crystal display device, according to one embodiment of the present invention, a side surface of a semiconductor layer (a side surface of an end portion of the semiconductor layer) is covered with a pixel electrode.

According to the embodiments of the present invention, entry of impurities from the outside can be suppressed. Therefore, changes in the characteristics of the thin film transistor due to entry of impurities from the outside can be suppressed.

In a method of manufacturing a liquid crystal display device, according to one embodiment of the present invention, the semiconductor layer includes an oxide semiconductor.

According to the embodiments of the present invention, a highly reliable liquid crystal display device with low power consumption can be realized by using an oxide semiconductor as a semiconductor layer.

In a method for manufacturing a liquid crystal display device, according to one embodiment of the present invention, heat treatment is performed on an oxide semiconductor.

According to the embodiments of the present invention, the concentration of impurities such as moisture and hydrogen used as electron donors (donors) of the semiconductor layer can be sufficiently reduced. Therefore, off-state current of the transistor can be reduced.

For an oxide semiconductor (purified oxide semiconductor) in which impurities such as moisture and hydrogen used as an electron donor (donor) are reduced (purified oxide semiconductor), the hydrogen concentration measured by secondary ion mass spectrometry (SIMS) is 5×10 ¹⁹ /cm ³ or less, preferably 5×10 ¹⁸ /cm ³ or less, more preferably 5×10 ¹⁷ /cm ³ or less, still more preferably 1×10 ¹⁶ /cm ³ or less . In addition, the band gap of the oxide semiconductor is 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more.

SIMS analysis of hydrogen concentration in an oxide semiconductor is described here. Due to the principle of SIMS analysis, it is known that it is difficult to obtain accurate data near the sample surface or near the interface between laminated films formed of different materials. Therefore, when the hydrogen concentration of the film is analyzed by SIMS, the average value in a region where the value does not change extremely and is substantially constant is used as the hydrogen concentration. Furthermore, in the case where the thickness of the film is small, due to the influence of hydrogen in the films adjacent to each other, a region where a constant value can be obtained cannot be found in some cases. In this case, the maximum or minimum value of the hydrogen concentration is used as the hydrogen concentration in the film. Also, in the case where there is no maximum peak or minimum valley, the value of the inflection point is used as the hydrogen concentration.

In a method for manufacturing a liquid crystal display device, according to an embodiment of the present invention, a first conductive layer and a second conductive layer are respectively formed using a copper-containing material.

According to an embodiment of the present invention, forming a gate electrode, a source electrode, a drain electrode, or a wiring connected to these electrodes using a copper-containing material allows reducing wiring resistance so that signal delay can be prevented.

In the method of manufacturing a liquid crystal display device, according to an embodiment of the present invention, the upper limit of the process temperature after the formation of the first conductive layer and the second conductive layer is lower than or equal to 450°C.

According to an embodiment of the present invention, when a copper-containing material is used to form a gate electrode, a source electrode, a drain electrode, or a wiring connected to these electrodes, the electrodes and the wiring will not be deformed, and components in the electrodes and the wiring will not be deformed due to thermal factors. elution does not occur. Therefore, a highly reliable liquid crystal display device can be manufactured.

In a method for manufacturing a liquid crystal display device, according to an embodiment of the present invention, a first conductive layer and a second conductive layer are respectively formed using a material containing aluminum.

According to an embodiment of the present invention, forming a gate electrode, a source electrode, a drain electrode, or a wiring connected to these electrodes using a material containing aluminum allows reduction of wiring resistance so that signal delay can be prevented.

In the method for manufacturing a liquid crystal display device, according to an embodiment of the present invention, the upper limit of the process temperature after the formation of the first conductive layer and the second conductive layer is lower than or equal to 380°C.

According to an embodiment of the present invention, when an aluminum-containing material is used to form a gate electrode, a source electrode, a drain electrode, or a wiring connected to these electrodes, the electrodes and the wiring will not be deformed, and components in the electrodes and the wiring will not be deformed due to thermal factors. elution does not occur. Therefore, a highly reliable liquid crystal display device can be manufactured.

According to one embodiment of the present invention, a method for manufacturing a liquid crystal display device includes: a step of forming an element region on a substrate, a separation layer is interposed between the substrate and the element region, the element region includes at least a gate electrode, a first An insulating layer, a semiconductor layer, a source electrode, a drain electrode, a second insulating layer, and a pixel electrode, followed by a step of forming a protective layer so that the protective layer covers the surface of the element region; a step of separating the protective layer and the element region from the substrate; A step of bonding a support member to other surfaces of the element area, the fracture toughness of the first support member being greater than or equal to 1.5 [MPa·m ^1/2 ]; a step of removing the protective layer from the first support member; The fourth conductive layer is formed on the surface of the second support, the fracture toughness of the second support is greater than or equal to 1.5 [MPa·m ^1/2 ]; and the surface of the first support with the element region and the fourth conductive layer are provided A liquid crystal material is provided between the surfaces of the second support.

According to an embodiment of the present invention, the element region provided on the substrate can be transferred to the first support whose fracture toughness is greater than or equal to 1.5 [MPa·m ^1/2 ]. In addition, the second support for sandwiching the liquid crystal material may have a fracture toughness greater than or equal to 1.5 [MPa·m ^1/2 ]. Therefore, a liquid crystal display device that is thin, lightweight, and not easily broken can be manufactured.

A semiconductor device in this specification refers to any device that can function by utilizing semiconductor characteristics. Semiconductor circuits, storage devices, imaging devices, display devices, electro-optic devices, electronic devices, etc. are all semiconductor devices.

When "B is formed on A" or "B is formed over A" is explicitly described in this specification, it does not necessarily mean that B is formed in direct contact with A. This expression includes the case where A and B are not in direct contact with each other, that is, includes the case where another object is interposed between A and B. Here, A and B each correspond to an object (for example, a device, element, circuit, wiring, electrode, terminal, film, layer, or substrate).

Thus, for example, when it is expressly described that layer B is formed on (or over) layer A, it includes the case where layer B is formed in direct contact with layer A, and where another layer (e.g., layer C or layer D) is formed in direct contact with layer A. Both the case where the layer B is formed in direct contact with the layer C or layer D is formed in direct contact. It is to be noted that another layer (such as layer C or layer D) may be a single layer or a multilayer.

In this specification, ordinal numbers such as 'first', 'second' and 'third' are used in order to avoid confusion among components, and these terms do not imply the number of components.

A "transistor" in this specification is a semiconductor element, and can perform amplification of current or voltage, switching operation for controlling conduction or non-conduction, and the like. "Transistor" in this specification includes insulated gate field effect transistors (IGFETs) and thin film transistors (TFTs).

The functions of "source" and "drain" of transistors in this specification are sometimes interchangeable with each other, for example, when using transistors of opposite polarity or when changing the direction of current flow in circuit operation. Therefore, the terms "source" and "drain" may be used to denote a drain and a source, respectively, in this specification.

In this specification, the term "electrode" or "wiring" does not limit the function of the component. For example, "electrode" is sometimes used as part of "wiring" and vice versa. In addition, the term "electrode" or "wiring" may include a case where a plurality of "electrodes" or "wiring" are formed in an integrated manner.

The term "toughness" in this specification means the resistance of a material to fracture. When the material has high toughness, fracture does not easily occur even when a heavy load is applied or a strong impact is made, and fracture does not easily occur when, for example, a crack generated in a part of the substrate is used as a starting point. The toughness grade can be expressed as fracture toughness Kc. It is to be noted that the fracture toughness Kc can be determined by the test method defined in JIS R1607.

According to an embodiment of the present invention, the number of photomasks can be reduced compared to conventional cases without using complex techniques or special devices. In addition, a method of manufacturing a thin, lightweight, and remarkably tough liquid crystal display device can be provided.

Description of drawings

In the attached picture:

1A and 1B are top and cross-sectional views illustrating one embodiment of the present invention;

2A and 2B are top and cross-sectional views illustrating one embodiment of the present invention;

3A and 3B are circuit diagrams illustrating an embodiment of the present invention;

4A-1 and 4B-1 are top views illustrating embodiments of the present invention, and FIGS. 4A-2 and 4B-2 are cross-sectional views illustrating embodiments of the present invention;

5A to 5C are cross-sectional process diagrams illustrating one embodiment of the present invention;

6A to 6C are cross-sectional process diagrams illustrating one embodiment of the present invention;

7A to 7C are cross-sectional views illustrating an embodiment of the present invention;

8A and 8B are top and cross-sectional views illustrating one embodiment of the present invention;

9A to 9C are cross-sectional process diagrams illustrating one embodiment of the present invention;

10A to 10C are cross-sectional process diagrams illustrating one embodiment of the present invention;

11A to 11B are cross-sectional process diagrams illustrating one embodiment of the present invention;

12A to 12F are views each showing an application example of an electronic device; and

13A to 13B are views showing application examples of electronic devices.

detailed description

Various embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the modes and details of the present invention can be changed in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the following embodiments. It is to be noted that, in the structure of the present invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and descriptions thereof will not be repeated.

(Example 1)

In this embodiment, a structural example of a pixel portion included in a liquid crystal display device according to an embodiment of the present invention will be described with reference to FIGS. 1A to 6C.

FIG. 3A shows a structural example of a semiconductor device 100 used in a liquid crystal display device. The semiconductor device 100 includes a pixel region 102 on a substrate 101, a terminal portion 103 including m (m is an integer greater than or equal to 1) terminals 105, and a terminal portion 103 including n (n is an integer greater than or equal to 1) terminals 106. terminal portion 104 . The semiconductor device 100 also includes m wirings 212 electrically connected to the terminal portion 103 and n wirings 216 electrically connected to the terminal portion 104 . The pixel area 102 includes a plurality of pixels 110 arranged in a matrix of m rows (in the vertical direction)×n columns (in the lateral direction). The pixel 110 (i, j) in the i-th row and j-th column (i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to 1 and less than or equal to n) is electrically connected to the wiring 212-i and wiring 216-j. The wiring 212-i is electrically connected to the terminal 105-i, and the wiring 216-j is electrically connected to the terminal 106-j.

The terminal portion 103 and the terminal portion 104 are external input terminals, and are connected to a control circuit provided externally through a flexible printed circuit (FPC) or the like. A signal supplied from a control circuit provided outside is input to the semiconductor device 100 through the terminal portion 103 and the terminal portion 104 . In FIG. 3A, terminal portions 103 are provided on the right outer and left outer sides of the pixel region 102, and signals are input from both portions. The terminal part 104 is provided on the upper outer side and the lower outer side of the pixel area 102, and signals are input from both parts. Signal supply capability is increased by signal input from two parts; therefore, high-speed operation of the semiconductor device 100 can be easily realized. Furthermore, the influence of a signal delay due to an increase in wiring resistance due to an increase in size or definition of the semiconductor device 100 can be reduced. In addition, the semiconductor device 100 may have redundancy so that the reliability of the semiconductor device 100 is increased. It is to be noted that although FIG. 3A shows a structure in which two terminal portions 103 and two terminal portions 104 are provided, a structure in which one terminal portion 103 and one terminal portion 104 are provided may be employed.

FIG. 3B shows a circuit configuration of the pixel 110 . The pixel 110 includes a transistor 111 , a liquid crystal element 112 and a capacitor 113 . The gate electrode of the transistor 111 is electrically connected to the wiring 212-i, and one of the source electrode and the drain electrode of the transistor 111 is electrically connected to the wiring 216-j. The other of the source electrode and the drain electrode of the transistor 111 is electrically connected to one electrode of the liquid crystal element 112 and one electrode of the capacitor 113 . The other electrode of the liquid crystal element 112 and the other electrode of the capacitor 113 are electrically connected to the electrode 114 . The potential of the electrode 114 can be a fixed potential, such as 0V, ground or common potential.

The transistor 111 has a function of determining whether an image signal supplied from the wiring 216 - j is input to the liquid crystal element 112 . When a signal for turning on the transistor 111 is supplied to the wiring 212 - i , an image signal from the wiring 216 - j is supplied to the liquid crystal element 112 through the transistor 111 . The light transmittance of the liquid crystal element 112 is controlled depending on the supplied image signal (potential). The capacitor 113 functions as a storage capacitor (also referred to as a Cs capacitor) that holds the potential supplied to the liquid crystal element 112 . Although the capacitor 113 is not necessarily provided, when the capacitor 113 is provided, a change in potential applied to the liquid crystal element 112 caused by a current (off-state current) flowing between the source electrode and the drain electrode when the transistor 111 is off can be suppressed.

The capacitance of the storage capacitor provided in the liquid crystal display device is set in consideration of leakage current and the like of transistors provided in the pixel portion so that charges can be held for a predetermined period of time. When a transistor having a highly purified oxide semiconductor is used for a semiconductor layer in which a channel region is formed, it is sufficient to provide a storage capacitor having a capacitance less than or equal to 1/3, preferably less than or equal to 1/5, of the liquid crystal capacitance of each pixel .

A single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, an amorphous semiconductor, or the like can be used as the semiconductor for forming the channel of the transistor 111 . Examples of semiconductor materials include silicon, germanium, silicon germanium, silicon carbide, and germanium arsenide.

Alternatively, an oxide semiconductor may be used as a semiconductor for forming a channel of the transistor 111 . The oxide semiconductor may be a single crystal oxide semiconductor or a non-single crystal oxide semiconductor. In the latter case, the non-single-crystal oxide semiconductor may be amorphous, microcrystalline (nanocrystalline), or polycrystalline. In addition, the oxide semiconductor may have an amorphous structure including a portion having crystallinity, or an amorphous structure not including a portion having crystallinity. An amorphous oxide semiconductor can be formed by sputtering using an oxide semiconductor target. A crystalline oxide semiconductor can be formed when a substrate is heated to a temperature higher than or equal to room temperature in sputtering. As the oxide semiconductor, an oxide semiconductor whose crystal axes are aligned as described in Embodiment 2 can be used.

An oxide semiconductor has a wide energy gap of 3.0 eV or more. In a transistor with an oxide semiconductor prepared under appropriate conditions, the off-state current can be lower than or equal to 100zA (1× ^10-19 A) at an operating temperature (such as 25°C), and further lower than or equal to 10zA (1 ×10 ^-20 A), further lower than or equal to 1zA (1×10 ^-21 A).

Therefore, using an oxide semiconductor for the semiconductor layer of the transistor 111 in which the channel is formed allows the current value in the off state (off state current value) to be reduced. Therefore, the holding time of an electrical signal such as an image signal can be increased, and the signal can be held for a longer period of time even without performing additional writing. Therefore, the frequency of the refresh operation can be reduced, which contributes to the reduction of power consumption. In addition, the transistor 111 in which an oxide semiconductor is used for the semiconductor layer can maintain the potential supplied to the liquid crystal element even when no storage capacitor is provided.

A transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed has relatively high field-effect mobility, enabling high-speed operation. Therefore, by using such a transistor in a pixel portion of a liquid crystal display device, high-quality images can be provided. Furthermore, since such a transistor can be provided in each of the driver circuit section and the pixel section provided on one substrate, the number of components of the liquid crystal display device can be reduced.

Next, a structural example of the pixel 110 shown in FIGS. 3A and 3B will be described with reference to FIGS. 1A and 1B . FIG. 1A is a plan view showing the planar structure of the pixel 110 , and FIG. 1B is a cross-sectional view showing the layered structure of the pixel 110 . It is to be noted that dotted lines A1-A2, B1-B2, and C1-C2 in FIG. 1A correspond to sections A1-A2, B1-B2, and C1-C2 in FIG. 1B, respectively.

In the transistor 111 described in this embodiment, the drain electrode 206b is partially surrounded by the U-shaped (C-shaped, inverted C-shaped, or horseshoe-shaped) source electrode 206a. With the source electrode having such a shape, the channel width can be sufficiently secured even when the transistor area is small; therefore, the amount of current flowing during the on-state of the transistor (also referred to as on-state current) can be increased.

When the parasitic capacitance between the gate electrode 202 and the drain electrode 206b electrically connected to the pixel electrode 210 is large, the influence due to feedthrough is easily enhanced; therefore, the potential supplied to the liquid crystal element 112 cannot be accurately maintained, which will cause Display quality has deteriorated. As described in this embodiment, by utilizing the structure in which the drain electrode 206 is partially surrounded by the U-shaped source electrode 206A, the channel width can be sufficiently ensured, and the parasitic capacitance between the drain electrode 206b and the gate electrode 202 can be small; Improve the display quality of liquid crystal display devices.

In section A1 - A2 of FIG. 1B , the layered structure of transistor 111 is shown. Transistor 111 is a bottom gate transistor. In section B1 - B2 of FIG. 1B , the layered structure of capacitor 113 is shown. In the section C1-C2, the layered structure of the wiring intersection portion of the capacitor wiring 203 and the wiring 216 is shown.

In the section A1 - A2 , the separation layer 250 is formed on the substrate 200 , the base layer 201 is formed on the separation layer 250 , and the gate electrode 202 is formed on the base layer 201 . A first insulating layer 204 and a semiconductor layer 205 are formed on the gate electrode 202 . In addition, a source electrode 206 a and a drain electrode 206 b are formed on the semiconductor layer 205 . On the source electrode 206 a and the drain electrode 206 b , a second insulating layer 207 is formed in contact with part of the semiconductor layer 205 . The pixel electrode 210 is formed on the second insulating layer 207 and is electrically connected to the drain electrode 206b through the contact hole 208 formed in the second insulating layer 207 .

Part of the first insulating layer 204 , part of the semiconductor layer 205 and part of the second insulating layer 207 are removed, and the pixel electrode 210 is formed in contact with the first insulating layer 204 , the semiconductor layer 205 and the second insulating layer 207 . In the present embodiment, an oxide semiconductor having a significantly reduced carrier concentration (also referred to as an i-type (intrinsic) or substantially i-type oxide semiconductor) is used for the semiconductor layer 205 . An oxide semiconductor can basically be regarded as an insulator in an off state. Therefore, even if the pixel electrode 210 is in contact with the side surface of the end portion of the semiconductor layer 205, problems such as leakage current do not occur.

In addition, since the side surface of the end portion of the semiconductor layer 205 is covered with the pixel electrode 210, external impurities such as hydrogen, water, compounds having hydroxyl groups, hydrides, alkali metals such as sodium, lithium, and potassium, and Alkaline earth metal) reaches the semiconductor layer 205 and adversely affects the electrical characteristics and reliability of the transistor.

In section B1 - B2 , separation layer 250 is formed on substrate 200 , base layer 201 is formed on separation layer 250 , and capacitor wiring 203 is formed on base layer 201 . A first insulating layer 204 and a semiconductor layer 205 are formed on the capacitor wiring 203 , and a second insulating layer 207 is formed on the semiconductor layer 205 . In addition, a pixel electrode 210 is formed on the second insulating layer 207 .

The capacitor wiring 203 and the pixel electrode 210 overlap each other, and a portion where the first insulating layer 204 , the semiconductor layer 205 , and the second insulating layer 207 are interposed therebetween serves as the capacitor 113 . The first insulating layer 204, the semiconductor layer 205, and the second insulating layer 207 function as dielectric layers. Since the dielectric layer formed between the capacitor wiring 203 and the pixel electrode 210 has a multilayer structure, even when a small hole is formed in one dielectric layer, the small hole is covered with another dielectric layer; therefore, the capacitor 113 works normally. In addition, the relative permittivity of an oxide semiconductor is higher than that of silicon oxide, silicon nitride, or the like generally used as an insulating film; therefore, by using an oxide semiconductor for the semiconductor layer 205, the capacitance of the capacitor 113 can be large.

In section C1 - C2 , separation layer 250 is formed on substrate 200 , base layer 201 is formed on separation layer 250 , and capacitor wiring 203 is formed on base layer 201 . The first insulating layer 204 and the semiconductor layer 205 are formed on the capacitor wiring 203 . The wiring 216 is formed on the semiconductor layer 205 , and the second insulating layer 207 and the pixel electrode 210 are formed on the wiring 216 .

It is to be noted that in FIG. 1B , the layers formed on the separation layer 250 are collectively referred to as an element region 260 hereinafter. The element region 260 includes at least a gate electrode 202 , a first insulating layer 204 , a semiconductor layer 205 , a source electrode 206 a , a drain electrode 206 b , a second insulating layer 207 and a pixel electrode 210 . The element region 206 may further include a base layer 201 and wiring 216 . The element region 260 may further include a wiring 212 , an electrode 221 , an electrode 222 and the like which will be described later.

Next, the structure of a pixel whose capacitor is different from that of the pixel 110 in FIGS. 1A and 1B will be described with reference to FIGS. 2A and 2B . FIG. 2A is a plan view showing the planar structure of the pixel 120 , and FIG. 2B is a cross-sectional view showing the layered structure of the pixel 120 . It is to be noted that dotted lines A1-A2, B1-B2, and C1-C2 in FIG. 2A correspond to sections A1-A2, B1-B2, and C1-C2 in FIG. 2B, respectively.

In section B1 - B2 , separation layer 250 is formed on substrate 200 , base layer 201 is formed on separation layer 250 , and capacitor wiring 203 is formed on base layer 201 . The first insulating layer 204 and the semiconductor layer 205 are formed on the capacitor wiring 203 , and the electrode 217 is formed on the semiconductor layer 205 . In addition, the second insulating layer 207 is formed on the electrode 217 , and the pixel electrode 210 is formed on the second insulating layer 207 . The pixel electrode 210 is electrically connected to the electrode 217 through a contact hole 218 formed in the second insulating layer 207 .

The capacitor wiring 203 and the electrode 217 overlap each other, and a portion where the first insulating layer 204 and the semiconductor layer 205 are interposed therebetween serves as the capacitor 123 . The thickness of the dielectric layer formed between the capacitor wiring 203 and the electrode 217 of the capacitor 123 may be smaller than that of the second insulating layer 207 in the capacitor 113 shown in FIG. 1B . Therefore, the capacitance of the capacitor 123 may be greater than that of the capacitor 113 .

It is to be noted that in FIG. 2B , the layers formed on the separation layer 250 are collectively referred to as an element region 260 hereinafter. The element region 260 includes at least a gate electrode 202 , a first insulating layer 204 , a semiconductor layer 205 , a source electrode 206 a , a drain electrode 206 b , a second insulating layer 207 and a pixel electrode 210 . The element region 206 may further include a base layer 201 and wiring 216 . The element region 260 may further include a wiring 212 , an electrode 221 , an electrode 222 and the like which will be described later.

Next, structural examples of the terminal 105 and the terminal 106 will be described with reference to FIGS. 4A-1 , 4A-2 , 4B-1 and 4B-2 . 4A-1 and 4A-2 are a plan view and a cross-sectional view showing the terminal 105, respectively. The dotted line D1-D2 in FIG. 4A-1 corresponds to the section D1-D2 in FIG. 4A-2. 4B-1 and 4B-2 are a plan view and a cross-sectional view showing the terminal 106, respectively. The dotted line E1-E2 in FIG. 4B-1 corresponds to the section E1-E2 in FIG. 4B-2.

In section D1 - D2 , separation layer 250 is formed on substrate 200 , base layer 201 is formed on separation layer 250 , and wiring 212 is formed on base layer 201 . The first insulating layer 204 , the semiconductor layer 205 and the second insulating layer 207 are formed on the wiring 212 . The electrode 221 is formed on the second insulating layer 207 and is electrically connected to the wiring 212 through the contact hole 219 formed in the first insulating layer 204 , the semiconductor layer 205 and the second insulating layer 207 .

In section E1 - E2 , a separation layer is formed on the substrate 200 , a base layer 201 is formed on the separation layer 250 , a first insulating layer 204 is formed on the base layer 201 , and a semiconductor layer 205 is formed on the first insulating layer 204 . A wiring 216 is formed on the semiconductor layer 205 , and a second insulating layer 207 is formed on the wiring 216 . The electrode 222 is formed on the second insulating layer 207 and is electrically connected to the wiring 216 through the contact hole 220 formed in the second insulating layer 207 .

Next, a method of manufacturing a pixel portion in the liquid crystal display device described using FIGS. 1A and 1B will be described with reference to FIGS. 5A to 5C and FIGS. 6A to 6C. Note that sections A1-A2, B1-B2, and C1-C2 in FIGS. 5A to 5C and FIGS. 6A to 6C are sections taken along broken lines A1-A2, B1-B2, and C1-C2 in FIG. 1A, respectively.

Note that in FIGS. 5A to 5C and FIGS. 6A to 6C , cross sections D1 - D2 showing the layered structure of the terminal 105 and sections E1 - E2 showing the layered structure of the terminal 106 are additionally shown. In sections D1-D2 and E1-E2, D2 and E2 each correspond to an edge of the substrate.

First, a separation layer 250 is formed on the substrate 200 to a thickness of greater than or equal to 50 nm and less than or equal to 1000 nm, preferably greater than or equal to 100 nm and less than or equal to 500 nm, more preferably greater than or equal to 100 nm and less than or equal to 300 nm.

The substrate 200 may be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, or the like. Note that such substrates, which are not thin enough to be clearly bendable, enable accurate formation of elements such as transistors. "Not explicitly bendable" means that the modulus of elasticity of the substrate is higher than or equal to that of glass substrates commonly used in the manufacture of liquid crystal displays. In this embodiment, aluminoborosilicate glass is used as the substrate 200 .

By sputtering method, plasma CVD method, brushing method, printing method, etc., and using any element selected from the following: tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb ), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir) and silicon (Si ), an alloy containing any one of the above-mentioned elements as its main component, and a compound containing any one of the above-mentioned elements as its main component, the separation layer 250 is formed to have a single-layer or layered structure.

When the separation layer 250 has a single-layer structure, it is preferable to form a layer containing tungsten, molybdenum, or a mixture of tungsten and molybdenum. Alternatively, a layer containing oxide or oxynitride of tungsten, a layer of oxide or oxynitride containing molybdenum, or a layer of oxide or oxynitride containing a mixture of tungsten and molybdenum is formed. Note that a mixture of tungsten and molybdenum corresponds to, for example, an alloy of tungsten and molybdenum.

In the case where the separation layer 250 has a layered structure, it is preferable to form a metal layer and a metal oxide layer as a first layer and a second layer, respectively. Generally, it is preferable to form a tungsten layer, a molybdenum layer, or a layer containing a mixture of tungsten and molybdenum as the first layer, and to form an oxide, oxynitride, or oxynitride of tungsten, molybdenum, or a mixture of tungsten and molybdenum as the second layer. second floor. When the metal oxide layer is formed as the second layer, an oxide layer such as silicon oxide that can be used as an insulating layer may be formed on the metal layer as the first layer so that an oxide of the metal is formed on the surface of the metal layer .

It is also possible to use a hydrogen-containing amorphous silicon layer, a layer containing nitrogen, oxygen, hydrogen, etc. (such as a hydrogen-containing amorphous silicon film, a hydrogen-containing alloy film, or an oxygen-containing alloy film), or an organic resin as the separation layer 250.

In this embodiment, a tungsten film with a thickness of 150 nm is used as the separation layer 250 . Note that the tungsten film may be in a state where its surface is oxidized (ie, a state where a tungsten oxide film is formed on the surface of the tungsten film).

The separation layer 250 is a layer mainly for separating the semiconductor device provided on the base layer 201 from the substrate 200 , and further has a function of preventing impurity elements from diffusing from the substrate 200 .

Next, an insulating layer serving as base layer 201 is formed on separation layer 250 to a thickness of greater than or equal to 50 nm and less than or equal to 300 nm, preferably greater than or equal to 100 nm and less than or equal to 200 nm.

The base layer 201 may be formed in a single-layer structure or a layered structure using at least one of the following insulating layers: an aluminum nitride layer, an aluminum oxynitride layer, a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and an oxide layer. silicon nitride layer. Base layer 201 has a function of preventing impurity elements from diffusing from substrate 200 and separation layer 250 . It is to be noted that silicon oxynitride in this specification contains oxygen and nitrogen so that the nitrogen content is higher than the oxygen content. Preferably, silicon oxynitride is estimated to have a composition of 5 at. % to 30 at.%, 20 at.% to 55 at.%, 25 at.% to 35 at.%, and 10 at.% to 30 at.% of oxygen, nitrogen, silicon and hydrogen. The base layer 201 can be appropriately formed by a sputtering method, a CVD method, a coating method, a printing method, or the like. In the case where an oxygen-containing film such as a silicon oxynitride film is formed as base layer 201, the surface of separation layer 250 is oxidized so that a metal oxide thin film is formed on the surface of separation layer 250 in the film formation. Metal oxides are handled as the separation layer 250 .

In this embodiment, a stack of a silicon nitride layer and a silicon oxide layer is used as the base layer 201 . Specifically, a 50 nm thick silicon nitride layer was formed on the separation layer 250, and a 150 nm thick silicon oxide layer was formed on the silicon nitride layer. It is to be noted that the base layer 201 may be doped with phosphorus (P) or boron (B).

When a halogen element such as chlorine or fluorine is contained in the base layer 201, the function of preventing impurity elements from diffusing from the substrate 200 may be further improved. The concentration of halogen elements contained in the base layer 201 is measured by secondary ion mass spectrometry (SIMS), and its peak value is preferably greater than or equal to 1×10 ¹⁵ /cm ³ and less than or equal to 1×10 ²⁰ /cm ³ .

The base layer 201 may be formed using gallium oxide. Alternatively, the base layer 201 may have a layered structure of a gallium oxide layer and the above-mentioned insulating layer. Gallium oxide is a material that is difficult to change; therefore, a change in threshold voltage due to charge accumulation of the insulating layer can be suppressed.

Next, a first conductive layer is formed on the base layer 201 by sputtering, vacuum evaporation or electroplating, with a thickness of greater than or equal to 100 nm and less than or equal to 500 nm, preferably greater than or equal to 200 nm and less than or equal to 300 nm. . Then, a first resist mask is formed on the first conductive layer, and the first conductive layer is partially etched using the first resist mask, thereby forming gate electrode 202 , capacitor wiring 203 and wiring 212 .

The first conductive layer for forming the gate electrode 202, the capacitor wiring 203, and the wiring 212 may be formed to have a single layer or a layered structure in which materials such as molybdenum (Mo), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), copper (Cu), chromium (Cr), neodymium (Nd), or scandium (Sc) metal material, or an alloy including any of these elements as its main component. Alternatively, a conductive metal oxide may be used to form the first conductive layer. As conductive metal oxides, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium oxide-tin oxide (In ₂ O ₃ -SnO ₂ , referred to as ITO), oxide Indium-zinc oxide (In ₂ O ₃ —ZnO), or any of these metal oxides containing silicon oxide. Alternatively, a conductive composition containing a conductive macromolecule (also referred to as a conductive polymer) may be used to form the first conductive layer. As the conductive macromolecule, a so-called π-electron conjugated conductive macromolecule can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, and a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

Since the first conductive layer is used as wiring, it is preferable to use a low-resistance material such as Al or Cu. By using Al or Cu, signal delay is reduced so that higher image quality can be expected. It is to be noted that Al has low thermal resistance, whereby defects due to hillocks, whiskers, or migration are easily generated. In order to prevent Al migration, it is preferable to stack a metal layer having a higher melting point than Al, such as Mo, Ti, or W, on the Al layer, or an alloy layer of Al and a hillock-preventing element such as Nd, Ti, Si, or Cu is preferably used. In the case where an Al-containing material is used as the first conductive layer, the maximum process temperature in the later step is preferably set to 380°C or lower, more preferably set to 350°C or lower.

Also, in the case where Cu is used as the first conductive layer, in order to prevent defects due to the migration and diffusion of Cu elements, it is preferable to stack a metal layer with a higher melting point than Cu, such as Mo, Ti, or W. In the case where a Cu-containing material is used as the first conductive layer, the maximum process temperature in a later step is preferably set to 450° C. or lower.

In this embodiment, as the first conductive layer, a 5 nm thick Ti layer is formed on the base layer 201, and a 250 nm thick Cu layer is formed on the Ti layer. Then, a first resist mask is formed on the first conductive layer, and the first conductive layer is partially etched using the first resist mask, thereby forming a gate electrode 202, a capacitor wiring 203, and a wiring 212 (see FIG. 5A).

It is to be noted that the first resist mask formed on the first conductive layer may be formed by an inkjet method. Forming the first resist mask by the inkjet method does not require a photomask; thus, manufacturing costs can be reduced. The first resist mask is removed after etching. Descriptions about the process of removing the first resist mask are omitted.

It is to be noted that the etching of the first conductive layer may be dry etching, or wet etching, or both dry etching and wet etching. As an etching gas for dry etching, a chlorine-containing gas such as chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ) or carbon tetrachloride (CCl ₄ ) can be used. chlorine-based gas).

For dry etching, a parallel plate reactive ion etching (RIE) method or an inductively coupled plasma (ICP) etching method may be used. The etching conditions are preferably set so that the base layer 201 is not etched as much as possible because the base layer 201 has a function of preventing the diffusion of impurity elements from the substrate 200 .

Then, a first insulating layer 204 serving as a gate insulating layer is formed on the gate electrode 202, the capacitor wiring 203, and the wiring 212 to a thickness of 50 nm or more and 800 nm or less, preferably 100 nm or more and 600 nm or less. . Silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum oxynitride, tantalum oxide, gallium oxide, yttrium oxide, hafnium oxide, hafnium silicate ( HfSixOy (x>0, y>0)), nitrogen-added hafnium silicate, nitrogen-added hafnium aluminate, etc. to form the first insulating layer 204 . A plasma CVD method, a sputtering method, or the like can be used. The first insulating layer 204 is not limited to a single layer, and may be a stack of different layers. For example, the first insulating layer 204 can be formed in the following manner: a silicon nitride layer (SiNy(y>0)) is formed as the gate insulating layer A by a plasma CVD method, and a silicon oxide layer (SiOx(x>0)) is stacked on The gate insulating layer A is used as the gate insulating layer B.

In addition to the sputtering method and the plasma CVD method, the first insulating layer 204 can be formed by, for example, a high-density plasma CVD method using microwaves (eg, a frequency of 2.45 GHz).

In this embodiment, a stack of silicon nitride and silicon oxide is used as the first insulating layer 204 . Specifically, a 50 nm thick silicon nitride layer was formed on the gate electrode 202, and a 100 nm thick silicon oxide layer was formed on the silicon nitride layer.

The first insulating layer 204 also serves as a protective layer. With the structure in which the Cu-containing gate electrode 202 is covered with the silicon nitride-containing insulating layer, Cu can be prevented from diffusing from the gate electrode 202 .

In the case where an oxide semiconductor is used for a semiconductor layer formed in a later step, the first insulating layer 204 can be formed using an insulating material containing a composition similar to the oxide semiconductor. In the case where the first insulating layer 204 is a stack of different layers, the layer in contact with the oxide semiconductor is formed using an insulating material containing a composition similar to the oxide semiconductor. This material is compatible with an oxide semiconductor, and using this material for the first insulating layer 204 allows the state of the interface between the oxide semiconductor and the first insulating layer 204 to be kept good. Here, "a component similar to an oxide semiconductor" means one or more elements selected from constituent elements of an oxide semiconductor. For example, in the case where the oxide semiconductor is formed using an In-Ga-Zn-based oxide semiconductor material, gallium oxide is given as an insulating material containing a composition similar to the oxide semiconductor.

In the case of using a layered structure, the first insulating layer 204 may have a layered structure including a film formed using an insulating material containing a composition similar to an oxide semiconductor, and a film containing a material different from the composition material of the above-mentioned film. .

It is preferable to use a high-purity gas from which impurities such as hydrogen, water, compounds having hydroxyl groups, and hydrides are removed as a sputtering gas when forming the first insulating layer 204 . For example, the purity of the high-purity gas from which impurities are removed and introduced into the sputtering device is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

Next, a semiconductor layer 205 is formed on the first insulating layer 204 .

The oxide semiconductor used preferably contains at least indium (In) or zinc (Zn). In particular, In and Zn are preferably contained. As a stabilizer for reducing changes in electrical characteristics of a transistor including an oxide semiconductor, gallium (Ga) is preferably additionally contained. Tin (Sn) is preferably contained as a stabilizer. Hafnium (Hf) is preferably included as a stabilizer. Aluminum (Al) is preferably contained as a stabilizer.

As another stabilizer, one or more lanthanide elements may be included, such as lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), Gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), and Lutetium (Lu).

As the oxide semiconductor, for example, the following can be used: indium oxide, tin oxide, zinc oxide, two-component metal oxides (such as In-Zn-based oxide, Sn-Zn-based oxide, Al-Zn-based oxide substances, Zn-Mg-based oxides, Sn-Mg-based oxides, In-Mg-based oxides, or In-Ga-based oxides), three-component metal oxides (such as In-Ga-based Zn oxide (also called IGZO), In-Al-Zn-based oxide, In-Sn-Zn-based oxide, Sn-Ga-Zn-based oxide, Al-Ga-Zn-based oxide , Sn-Al-Zn-based oxides, In-Hf-Zn-based oxides, In-La-Zn-based oxides, In-Ce-Zn-based oxides, In-Pr-Zn-based oxides , In-Nd-Zn-based oxides, In-Sm-Zn-based oxides, In-Eu-Zn-based oxides, In-Gd-Zn-based oxides, In-Tb-Zn-based oxides , In-Dy-Zn-based oxides, In-Ho-Zn-based oxides, In-Er-Zn-based oxides, In-Tm-Zn-based oxides, In-Yb-Zn-based oxides , or oxides based on In-Lu-Zn), or four-component metal oxides (such as oxides based on In-Sn-Ga-Zn, oxides based on In-Hf-Ga-Zn, oxides based on In- Al-Ga-Zn oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide, or In-Hf-Al-Zn-based oxide).

Note here that, for example, "In-Ga-Zn-based oxide" means an oxide containing In, Ga, and Zn as main components, and there is no specific limitation on the ratio of In, Ga, and Zn. The In-Ga-Zn-based oxide may contain another metal element other than In, Ga, and Zn.

For example, an atomic ratio of In:Ga:Zn=1:1:1 (=1/3:1/3:1/3) or In:Ga:Zn=2:2:1 (=2/5:1) can be used. 2/5:1/5) based In-Ga-Zn oxide, or any oxide whose composition is close to the above composition. Alternatively, an atomic ratio of In:Sn:Zn=1:1:1 (=1/3:1/3:1/3), In:Sn:Zn=2:1:3 (=1/3: 1/6:1/2), or In-Sn-Zn-based oxides of In:Sn:Zn=2:1:5 (=1/4:1/8:5/8), or components thereof Any oxide close to the above composition.

It is to be noted that one embodiment of the present invention is not limited thereto, and materials with suitable compositions may be used depending on semiconductor characteristics (mobility, threshold, variation, etc.). Furthermore, in order to obtain necessary semiconductor characteristics, it is preferable to appropriately set carrier concentration, impurity concentration, defect density, atomic ratio of metal element and oxygen, interatomic distance, density, and the like.

For example, with In-Sn-Zn based oxides, high mobility can be achieved relatively easily. However, even with In-Ga-Zn-based oxides, mobility can be improved by reducing the bulk defect density.

It is to be noted that, for example, the expression "the composition of an oxide whose atomic ratio is In:Ga:Zn=a:b:c (a+b+c=1) is close to the atomic ratio being In:Ga:Zn=A:B : Composition of an oxide of C(A+B+C=1)" means that a, b and c satisfy the following relationship: (aA) ² +(bB) ² +(cC) ² ≤r ² . For example the variable r could be 0.05. The same expression can be applied to other oxides.

The oxide semiconductor may be a single crystal oxide semiconductor or a non-single crystal oxide semiconductor. In the latter case, the non-single-crystal oxide semiconductor may be amorphous or polycrystalline. In addition, the oxide semiconductor may have an amorphous structure including a portion having crystallinity, or an amorphous structure not having a crystalline region.

In an oxide semiconductor in an amorphous state, a flat surface can be obtained relatively easily, so that interfacial scattering of a transistor can be suppressed, and relatively high mobility can be obtained relatively easily.

In an oxide semiconductor having crystallinity, bulk defects can be further reduced, and when surface flatness is improved, mobility higher than that of an oxide semiconductor layer in an amorphous state can be realized. In order to improve surface flatness, an oxide semiconductor is preferably formed on a flat surface. Specifically, the oxide semiconductor can be formed on a surface having an average surface roughness (Ra) of 1 nm or less, preferably 0.3 nm or less, more preferably 0.1 nm or less.

It is to be noted that Ra in this specification refers to the centerline average roughness obtained by three-dimensionally expanding the centerline average roughness defined by JIS B0601 to be applied to the surface to be measured. Ra can be expressed as "the average value of the absolute values of the deviations from the reference plane to the specified plane", and is defined by the following equation.

[equation 1]

${\mathrm{<span\; class="notranslate">\; R</span>}}_{\mathrm{<span\; class="notranslate">\; a</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}}{{\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}}{<span\; class="notranslate">\; \&Integral;</span>}_{\mathrm{<span\; class="notranslate">\; the\; y</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}^{\mathrm{<span\; class="notranslate">\; the\; y</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}{<span\; class="notranslate">\; \&Integral;</span>}_{\mathrm{<span\; class="notranslate">\; x</span>}\mathrm{<span\; class="notranslate">\; 1</span>}}^{\mathrm{<span\; class="notranslate">\; x</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; f</span>}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; ,</span>\mathrm{<span\; class="notranslate">\; the\; y</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; Z</span>}}_{\mathrm{<span\; class="notranslate">\; 0</span>}}<span\; class="notranslate">\; |</span>\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; x</span>}\mathrm{<span\; class="notranslate">\; d</span>}\mathrm{<span\; class="notranslate">\; the\; y</span>}$

Note that in Equation 1, S0 represents the area of the measurement surface (represented by the coordinates (x ₁ ,y ₁ ), (x ₁ ,y ₂ ), (x ₂ ,y ₁ ) and (x ₂ ,y ₂ ) The rectangular area defined by the four points), and Z0 represents the average height of the measurement surface. Ra can be measured using an atomic force microscope (AFM).

As an example of an oxide semiconductor having crystallinity, there are oxides including c-axis aligned crystals (also called C-axis aligned crystals (CAAC)), when viewed from the direction of the a-b plane, surface, or interface It has a triangular or hexagonal atomic arrangement. In a crystal, metal atoms are arranged in a layered manner, or metal atoms and oxygen atoms are arranged in a layered manner along the c-axis, and the a-axis or b-axis direction changes in the a-b plane (the crystal rotates around the c-axis).

In a broad sense, an oxide including CAAC means a non-single-crystal oxide that includes a crystalline phase having a triangular, hexagonal, regular triangular, or regular hexagonal atomic arrangement when viewed from a direction perpendicular to the a-b plane, and wherein Metal atoms are arranged in a layered manner when viewed from a direction perpendicular to the c-axis direction, or metal atoms and oxygen atoms are arranged in a layered manner.

CAAC is not a single crystal, but this does not mean that CAAC includes only amorphous components. Although CAAC includes crystalline fractions (crystal fractions), the boundary between one crystal fraction and another crystal fraction is unclear in some cases.

Where oxygen is included in CAAC, part of the oxygen may be substituted with nitrogen. The c-axes of the individual crystal portions included in the CAAC can be aligned in one direction (eg, a direction perpendicular to the surface of the substrate on which the CAAC is formed or perpendicular to the surface of the CAAC). Alternatively, the normals to the a-b planes of the respective crystal portions included in the CAAC may be aligned in one direction (eg, perpendicular to the surface of the substrate on which the CAAC is formed or perpendicular to the surface of the CAAC).

CAAC becomes a conductor, a semiconductor, or an insulator depending on its components, etc. CAAC transmits or does not transmit visible light depending on its components etc.

As an example of such a CAAC, there is a crystal formed in a film shape and having a triangular or hexagonal atomic arrangement when viewed from a direction perpendicular to the surface of the film or to the surface of the supporting substrate, in which the metal atoms are arranged in the form of arranged in a layered manner, or the metal atoms and oxygen atoms (or nitrogen atoms) are arranged in a layered manner.

In this embodiment, as the semiconductor layer 205 , an In-Ga-Zn-based oxide semiconductor is formed to a thickness of 30 nm by a sputtering method using an In-Ga-Zn-O-based oxide target.

In order to contain as little hydrogen, hydroxyl, and moisture as possible in the semiconductor layer 205, it is preferable to preheat the substrate 200 in a preheating chamber of a sputtering device for preheating before forming the semiconductor layer 205, thereby eliminating And remove impurities such as hydrogen or moisture adsorbed on the substrate 200 and the first insulating layer 204 . It is to be noted that this preheating treatment may be omitted. In addition, this preheating treatment may be similarly performed on the substrate 200 on which components up to and including the gate electrode 202 , the capacitor wiring 203 , and the wiring 212 are formed before the first insulating layer 204 is formed.

The filling rate of the metal oxide target is higher than or equal to 90% and lower than or equal to 100%, preferably higher than or equal to 95% and lower than or equal to 99.9%. By using a metal oxide target with a high filling rate, an oxide semiconductor layer can be formed with a high density.

It is preferable to use a high-purity gas from which impurities such as hydrogen, water, compounds having hydroxyl groups, and hydrides are removed as a sputtering gas when forming the semiconductor layer 205 . For example, the purity of the high-purity gas from which impurities are removed and introduced into the sputtering device is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

The semiconductor layer 205 is preferably formed by a sputtering method in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are less likely to enter the semiconductor layer. The deposition is performed in an oxygen atmosphere while the substrate is heated at a temperature higher than or equal to 100°C and lower than or equal to 600°C, preferably higher than or equal to 150°C and lower than or equal to 550°C, more preferably higher than or equal to 200°C and lower At or equal to 500°C. It is to be noted that when Al is used as a wiring layer (eg, gate electrode 202) formed by etching the first conductive layer, the substrate temperature is set to be lower than or equal to 380°C, preferably lower than or equal to 350°C. It is to be noted that when Cu is used as the wiring layer formed by etching the first conductive layer, the substrate temperature is set to be lower than or equal to 450°C. The thickness of the semiconductor layer 205 is greater than or equal to 1 nm and less than or equal to 40 nm, preferably greater than or equal to 3 nm and less than or equal to 20 nm. As the substrate heating temperature during deposition becomes higher, the impurity concentration of the obtained semiconductor layer 205 becomes lower. In addition, the arrangement of atoms in the semiconductor layer 205 is ordered, and its density is increased, so that polycrystals or CAACs are easily formed. In addition, since an oxygen atmosphere is used for deposition, unnecessary atoms are not contained in the semiconductor layer 205 unlike the case of using a rare gas atmosphere, so that polycrystals or CAAC are easily formed. Note that a mixed gas atmosphere including oxygen and a rare gas may be used. In this case, the percentage of oxygen is higher than or equal to 30 vol.% (volume percentage), preferably higher than or equal to 50 vol.%, more preferably higher than or equal to 80 vol.%. Note that as the semiconductor layer 205 becomes thinner, the short channel effect of the transistor decreases. However, when the semiconductor layer 205 is too thin, the semiconductor layer 205 is significantly affected by interfacial scattering; thus field effect mobility may decrease.

By heating the substrate during deposition, the concentration of impurities such as hydrogen, moisture, hydride or hydroxyl groups in the semiconductor layer 205 can be reduced. In addition, damage due to sputtering can be reduced. Then, a high-purity gas from which impurities such as hydrogen, water, compounds having hydroxyl groups, and hydrides have been removed is introduced into the deposition chamber, moisture remaining therein is removed from the deposition chamber, and the semiconductor layer 205 is formed using the above-mentioned target.

In order to remove moisture remaining in the deposition chamber, it is preferable to use an interception vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. As the exhaust unit, a turbomolecular pump with a cold trap can be used. In the deposition chamber evacuated with the cryopump, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (preferably, compounds containing carbon atoms), etc. are discharged, whereby the semiconductor formed in the deposition chamber can be reduced impurity concentration in layer 205.

Examples of deposition conditions are as follows: the distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, the direct current power is 0.5 kW, and an oxygen atmosphere is used (the flow rate of oxygen is 100%). It is to be noted that a pulsed DC power supply is preferably used, in which case powdery substances (also referred to as particles or dust) generated in deposition can be reduced and the film thickness can be uniform.

Note that it has been pointed out that oxide semiconductors are insensitive to impurities, and there is no problem when a large amount of metal impurities is contained in the oxide semiconductor film, so cheap soda-lime glass (Kamiya glass) containing a large amount of alkali metals such as sodium can also be used. , Nomura and Hosono, "Carrier Transport Properties and Electronic Structures of Amorphous Oxide Semiconductors: The present status", KOTAIBUTSURI (SOLID STATE PHYSICS) , 2009, Vol. 44, pp. 621-633). However, this consideration is inappropriate. When the concentration of the alkali metal in the oxide semiconductor is measured by secondary ion mass spectrometry, it is preferable that the sodium (Na) content is 5×10 ¹⁶ cm ⁻³ or less, preferably 1×10 ¹⁶ cm ⁻³ or less , more preferably 1×10 ¹⁵ cm ^-3 or less; lithium (Li) content of 5×10 ¹⁵ cm ^-3 or less, preferably 1×10 ¹⁵ cm ^-3 or less; potassium (K) content of 5 ×10 ¹⁵ cm ^-3 or less, preferably 1×10 ¹⁵ cm ^-3 or less.

Alkali metals and alkaline earth metals are unfavorable impurities for oxide semiconductors, and are preferably contained as little as possible. When the insulating film in contact with the oxide semiconductor is an oxide, alkali metals, especially Na ions diffuse from the insulating film to the oxide. In addition, Na cleaves the bond between metal and oxygen, or intercalates between metal-oxygen bonds. As a result, deterioration of transistor characteristics (such as a threshold value shifted to the negative side (causing the transistor to be normally on) or a decrease in mobility) is caused. In addition, this also leads to changes in properties. This problem is particularly noticeable in the case where the hydrogen concentration in the oxide semiconductor is extremely low. Therefore, in the case where the hydrogen concentration in the oxide semiconductor is lower than or equal to 5×10 ¹⁹ cm ⁻³ , especially lower than or equal to 5×10 ¹⁸ cm ⁻³ , it is strongly required to set the alkali metal concentration to the above value.

Even when the semiconductor layer 205 is formed by the method described above, the semiconductor layer 205 contains moisture or hydrogen (including hydroxyl groups) as impurities in some cases. Moisture or hydrogen easily forms a donor level, thereby serving as an impurity in the oxide semiconductor. In order to reduce impurities such as moisture and hydrogen in the semiconductor layer 205 (dehydrate or dehydrogenate the semiconductor layer 205), the semiconductor layer 205 may be subjected to a decompression atmosphere, an inert gas atmosphere such as a nitrogen atmosphere or a rare gas atmosphere, an oxygen atmosphere, or the like. Heat treatment is used for dehydration or dehydrogenation (hereinafter simply referred to as first heat treatment).

By performing the first heat treatment on the semiconductor layer 205, moisture or hydrogen on the surface of the semiconductor layer 205 and within the semiconductor layer 205 can be eliminated. Specifically, the heat treatment may be performed at a temperature higher than or equal to 250°C and lower than or equal to 750°C, preferably higher than or equal to 400°C and lower than the strain point of the substrate. For example, heat treatment may be performed at 500° C. for about 3 minutes to 6 minutes. When the RTA method is used for heat treatment, dehydration or dehydrogenation can be performed in a short time; therefore, treatment can be performed even at a temperature higher than the strain point of the glass substrate. It is to be noted that when Al is used as a wiring layer formed by etching the first conductive layer such as the gate electrode 202, the heat treatment temperature is set to be lower than or equal to 380°C, preferably lower than or equal to 350°C. It is to be noted that when Cu is used as the wiring layer formed by etching the first conductive layer, the heat treatment temperature is set to be lower than or equal to 450°C.

It is to be noted that the heat treatment apparatus is not limited to an electric furnace, and may include a device that heats an object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, a rapid thermal anneal (RTA) device such as a gas rapid thermal anneal (GRTA) device or a lamp rapid thermal anneal (LRTA) device may be used. The LRTA apparatus is for heating an object to be treated by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high-pressure sodium lamp, or a high-pressure mercury lamp device. The GRTA apparatus is an apparatus for performing heat treatment using high-temperature gas. As the gas, a rare gas such as argon or an inert gas that does not react with an object to be treated by heat treatment such as nitrogen is used.

The first heat treatment is performed in a reduced-pressure atmosphere or an inert gas atmosphere such as a nitrogen atmosphere, a helium atmosphere, a neon atmosphere, or an argon atmosphere. It is to be noted that the above atmosphere preferably does not contain moisture, hydrogen, or the like. The purity of nitrogen or a rare gas such as helium, neon or argon introduced into the heat treatment device is set to 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

The semiconductor layer 205 subjected to the first heat treatment may further undergo the second heat treatment. The second heat treatment is performed in an oxidizing atmosphere to supply oxygen to the semiconductor layer 205, whereby oxygen deficiency generated in the semiconductor layer 205 in the first heat treatment can be compensated. Thus, the second heat treatment can be referred to as heat treatment for oxygen supply. The second heat treatment may be performed at a temperature higher than or equal to 200°C and lower than or equal to the strain point of the substrate, preferably higher than or equal to 250°C and lower than or equal to 450°C. The processing time is from 3 minutes to 24 hours. As the processing time increases, the ratio of crystalline to amorphous regions in the semiconductor layer may increase. It is to be noted that heat treatment for more than 24 hours is not preferable because productivity is reduced.

The oxidizing atmosphere is an atmosphere containing an oxidizing gas. Note that the oxidizing gas is oxygen, ozone, nitrous oxide, etc., and it is preferable that the oxidizing gas does not contain water, hydrogen, or the like. For example, the purity of oxygen, ozone or nitrous oxide introduced into the heat treatment device is set to 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (i.e. the impurity concentration is less than 1ppm, preferably less than 0.1ppm). As the oxidizing atmosphere, an oxidizing gas and an inert gas may be mixed for use. In this case, the concentration of the mixture containing oxidizing gas is greater than or equal to 10 ppm. In addition, an inert atmosphere refers to an atmosphere containing an inert gas such as helium, neon, argon, krypton, or xenon as a main component. Specifically, the concentration of reactive gas such as oxidizing gas is less than 10 ppm.

It is to be noted that the second heat treatment can be performed using the same heat treatment apparatus and the same gas as the first heat treatment. It is preferable that the first heat treatment for dehydration or dehydrogenation and the second heat treatment for oxygen supply are performed continuously. When the first heat treatment and the second heat treatment are continuously performed, productivity of semiconductor devices can be increased.

In the semiconductor layer 205 purified by sufficiently reducing the hydrogen concentration, the defect level in the energy gap caused by oxygen deficiency is reduced by sufficiently supplying oxygen, and the semiconductor layer has a concentration of less than 1×10 ¹² /cm ³ , less than 1× A carrier concentration of 10 ¹¹ /cm ³ or less than 1.45×10 ¹⁰ /cm ³ . Therefore, the off-state current (per unit channel width (1 μm)) at room temperature (25° C.) is 100 zA/μm (1 zA (one-seventh power (zepto) ampere) is 1×10- ²¹ A) or lower, or 10zA/μm or lower. The off-state current at 85°C is 100zA/µm (1× ^10-19 A/µm) or less, or 10zA/µm (1× ^10-20 A/µm) or less. A transistor having excellent off-state current characteristics can be obtained using such an oxide semiconductor (also referred to as an i-type (intrinsic) or substantially i-type oxide semiconductor) in which the carrier concentration is significantly reduced.

Electrical characteristics of the transistor 111 such as threshold voltage and on-state current have little temperature dependence. In addition, changes in transistor characteristics due to photodegradation hardly occur.

Therefore, changes in electrical characteristics of a transistor including a highly purified oxide semiconductor whose carrier concentration is significantly reduced are suppressed, and thus the transistor is electrically stable. Therefore, by using an oxide semiconductor having stable electrical characteristics, a highly reliable liquid crystal display device can be provided.

It is to be noted that although the above describes the case where the first heat treatment and the second heat treatment are performed on the semiconductor layer 205 immediately after the semiconductor layer 205 is formed, the heat treatment may be performed at any time after the semiconductor layer 205 is formed.

In addition, after the semiconductor layer 205 is formed, an oxygenation treatment to be described below may first be performed on the semiconductor layer 205, and then a first heat treatment may be performed to eliminate hydrogen, hydroxyl groups, or moisture contained in the oxide semiconductor while allowing the oxide semiconductor crystallize. Crystallization may be performed in an additional heat treatment performed later. Through this crystallization or recrystallization process, the crystallinity of the semiconductor layer 205 can be further increased.

Here, "oxygenation treatment" means that oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions) is added to the bulk semiconductor layer 205 . It is to be noted that the term "bulk" is used to clarify that oxygen is added not only to the surface of the film but also to the interior of the film. In addition, "oxygen doping" includes "oxygen plasma doping" in which oxygen that becomes plasma is added to a bulk. When oxygen addition treatment is performed, the amount of oxygen contained in the semiconductor layer 205 can be made larger than the stoichiometric ratio. In addition, after the second insulating layer 207 is formed in a subsequent step, the second insulating layer 207 may undergo oxygen addition treatment, whereby the amount of oxygen in the second insulating layer 207 may be made greater than the stoichiometric ratio. By performing oxygen addition treatment and subsequent heat treatment on the second insulating layer 207 , oxygen in the second insulating layer 207 may be transferred to the semiconductor layer 205 to effectively compensate for oxygen deficiency in the semiconductor layer 205 .

The oxygenation treatment is preferably performed by an inductively coupled plasma (ICP) method using an oxygen plasma excited by microwaves (eg, at a frequency of 2.45 GHz).

It is to be noted that the oxygen addition treatment may also be called an oxygen supply treatment because it makes the amount of oxygen in the semiconductor layer 205, the second insulating layer 207, etc. larger than the stoichiometric ratio. The excess oxygen mainly exists between the lattices. When the oxygen concentration is set to be greater than or equal to 1×10 ¹⁶ /cm ³ and less than or equal to 2×10 ²⁰ /cm ³ , excess oxygen can be contained in the oxide semiconductor without causing crystal distortion or the like.

Next, a second conductive layer is formed on the semiconductor layer 205, a second resist mask is formed on the second conductive layer, and the second conductive layer is partially etched using the second resist mask, thereby forming the source electrode 206a. , the drain electrode 206b and the wiring 216.

The second conductive layer for forming the source electrode 206a, the drain electrode 206b, and the wiring 216 may be formed to have a single layer or a layered structure in which materials such as molybdenum (Mo), titanium (Ti), tungsten (W), tantalum (Ta), aluminum (Al), copper (Cu), chromium (Cr), neodymium (Nd), or scandium (Sc) metal material, or an alloy including any of these elements as its main component. Alternatively, a conductive metal oxide may be used to form the second conductive layer. As conductive metal oxides, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium oxide-tin oxide (In ₂ O ₃ -SnO ₂ , referred to as ITO), oxide Indium-zinc oxide (In ₂ O ₃ —ZnO), or any of these metal oxide materials containing silicon oxide. Alternatively, a conductive composition containing a conductive macromolecule (also referred to as a conductive polymer) may be used to form the second conductive layer. As the conductive macromolecule, a so-called π-electron conjugated conductive macromolecule can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, and a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

Since the second conductive layer is used as wiring, it is preferable to use a low-resistance material such as Al or Cu. By using Al or Cu, signal delay is reduced so that higher image quality can be expected. It is to be noted that Al has low thermal resistance, whereby defects due to hillocks, whiskers, or migration are easily generated. In order to prevent Al migration, it is preferable to stack a metal material layer with a melting point higher than Al on the Al layer, such as Mo, Ti, or W, or it is preferable to use an alloy layer of Al and an element that prevents hillocks (such as Nd, Ti, Si, or Cu) . In the case where an Al-containing material is used as the second conductive layer, the maximum process temperature in the subsequent step is preferably set to 380°C or lower, more preferably set to 350°C or lower.

Also, in the case where Cu is used as the second conductive layer, in order to prevent defects caused by the migration and diffusion of Cu elements, it is preferable to stack a metal material layer with a melting point higher than Cu, such as Mo, Ti, etc., on the second conductive layer containing Cu. or W. In the case where a Cu-containing metal is used as the second conductive layer, the maximum process temperature in the subsequent step is preferably set to 450° C. or lower.

In this embodiment, as the second conductive layer, a 5 nm thick Ti layer is formed on the semiconductor layer 205, and a 250 nm thick Cu layer is formed on the Ti layer. Then, a second resist mask is formed on the second conductive layer, and the second conductive layer is partially etched using the second resist mask, thereby forming a source electrode 206a, a drain electrode 206b, and a wiring 216 (see FIG. 5C).

It is to be noted that the second resist mask formed on the second conductive layer may be formed by an inkjet method. Forming the second resist mask by the inkjet method does not require a photomask; thus, manufacturing cost can be reduced. The second resist mask is removed after etching. Its description can be omitted.

Then, a second insulating layer 207 is formed on the source electrode 206a, the drain electrode 206b, the wiring 216, and the semiconductor layer 205 (see FIG. 6A). The second insulating layer 207 may be formed using materials and methods similar to the first insulating layer 204 or the base layer 201 . The second insulating layer 207 is preferably formed by sputtering because it is less likely to introduce hydrogen and impurities containing hydrogen. If the second insulating layer 207 contains hydrogen, the hydrogen may enter the semiconductor layer or extract oxygen in the semiconductor layer. Therefore, it is important to form the second insulating layer 207 in a method that does not contain hydrogen and hydrogen-containing impurities.

For the second insulating layer 207, an inorganic insulating material such as silicon oxide, silicon oxynitride, hafnium oxide, aluminum oxide, or gallium oxide may be used. Gallium oxide is a material that is difficult to change; therefore, a change in threshold voltage due to charge accumulation of the insulating layer can be suppressed. It is to be noted that, in the case where an oxide semiconductor is used for the semiconductor layer 205 , a metal oxide layer containing the same type of composition as the oxide semiconductor may be formed as the second insulating layer 207 or stacked on the second insulating layer 207 .

In this embodiment, as the second insulating layer 207, a silicon oxide layer was formed to a thickness of 200 nm by a sputtering method. The substrate temperature during deposition may be higher than or equal to room temperature and lower than or equal to 300°C, and in this embodiment it is 100°C. The silicon oxide layer can be formed by a sputtering method under a rare gas (usually argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas and oxygen. As the target, silicon oxide or silicon can be used. For example, by using silicon as a target, a silicon oxide layer can be formed by sputtering in an oxygen-containing atmosphere.

In order to remove moisture remaining in the deposition chamber when the second insulating layer 207 is formed, it is preferable to use a trap vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. For example, the second insulating layer 207 is formed in a deposition chamber evacuated using a cryopump, whereby the impurity concentration in the second insulating layer 207 can be reduced. Alternatively, as an exhaust unit for removing moisture remaining in the deposition chamber, a turbomolecular pump to which a cold trap is added may be used.

It is preferable to use a high-purity gas from which impurities such as hydrogen, water, hydroxyl group-containing compounds, and hydrides have been removed is used as a sputtering gas when forming the second insulating layer 207 . For example, the purity of the high-purity gas from which impurities such as hydrogen, water, hydroxyl-containing compounds, and hydrides have been removed is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

Then, in a reduced pressure atmosphere, an inert gas atmosphere, an oxygen atmosphere or an ultra-dry air atmosphere (preferably higher than or equal to 200°C and lower than or equal to 600°C, more preferably higher than or equal to 250°C and lower than or equal to equal to 550°C) to perform a third heat treatment. It is to be noted that in the case where Al is used as one or both of the wiring layer formed by etching the first conductive layer and the wiring layer formed by etching the second conductive layer, the heat treatment temperature is set to 380° C. or lower, preferably 350°C or lower. Alternatively, in the case where Cu is used as the wiring layer, the heat treatment temperature is set to 450° C. or lower. For example, the third heat treatment may be performed at 450° C. for 1 hour in a nitrogen atmosphere. In the third heat treatment, part of the semiconductor layer (channel formation region) is heated in a state of being in contact with the second insulating layer 207, so oxygen can be supplied to the semiconductor layer 205 from the second insulating layer 207 containing oxygen, thereby reducing Oxygen deficiency in the semiconductor layer 205 . It is to be noted that in the atmosphere at the time of the third heat treatment, it is preferable to reduce impurities such as water and hydrogen as much as possible in the deposition chamber where the second insulating layer 207 is formed.

Next, a third resist mask is formed on the second insulating layer 207, and the second insulating layer, the semiconductor layer 205, and the first insulating layer 204 are partially etched. At this time, in some pixels where TFTs are not formed, part of the second insulating layer 207 , part of the semiconductor layer 205 and part of the first insulating layer 204 are removed to form a pixel opening 225 . In addition, on the drain electrode 206b, only the second insulating layer 207 is etched, whereby a contact hole 208 is formed. On the wiring 216 in the section E1-E2, only the second insulating layer 207 is etched, thereby forming a contact hole 220 . On the wiring 212 in the section D1-D2, the second insulating layer 207, the semiconductor layer 205, and the first insulating layer 204 are etched, thereby forming a contact hole 219 (see FIG. 6B).

It is to be noted that the second insulating layer 207, the semiconductor layer 205, and the first insulating layer 204 in the pixel opening (part of the pixel in which the thin film transistor is not formed) are not necessarily etched. However, in the case where the liquid crystal display device is used as a transmissive liquid crystal display device, the etching of the second insulating layer 207, the semiconductor layer 205, and the first insulating layer 204 in the pixel opening may improve the transmittance of the pixel. Accordingly, the pixels efficiently emit light from the backlight, and thus it is possible to reduce power consumption or improve display quality due to an increase in luminance.

For etching the second insulating layer 207, the semiconductor layer 205, and the first insulating layer 204, dry etching, or wet etching, or both dry etching and wet etching may be employed. For example, a chlorine-containing gas (chlorine-based gas such as chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ), or carbon tetrachloride (CCl ₄ ) can be used as the Etching gas for dry etching.

For dry etching, a parallel plate reactive ion etching (RIE) method or an inductively coupled plasma (ICP) etching method may be used. The etching conditions are preferably set so that the base layer 201 is not etched as much as possible because the base layer 201 has a function of preventing the diffusion of impurity elements from the substrate 200 .

In general, etching of the semiconductor layer and formation of contact holes in the insulating layer are performed separately through different resist mask forming steps and different etching steps; however, according to the manufacturing process of this embodiment, the etching of the semiconductor layer and the insulating layer are performed separately. The formation of the contact hole in the layer can be performed by a resist mask forming step and an etching step. Therefore, not only a reduction in the number of photomasks but also a reduction in the number of resist mask forming steps and the number of different etching steps can be realized. Due to the reduction in the number of steps, a liquid crystal display device can be manufactured at a lower cost and with a higher productivity.

Furthermore, according to the manufacturing process of this embodiment, a resist mask is not directly formed on the semiconductor layer 205 . In addition, since the channel formation region in the semiconductor layer 205 is protected by the second insulating layer 207, moisture does not adhere to the channel formation region in the semiconductor layer in the separation step of the photoresist, the cleaning step, etc.; thus, Variation in characteristics of the transistor 111 can be reduced and reliability improved. Especially in the case where an oxide semiconductor is used as the semiconductor layer 205, the above-mentioned effect is more remarkable.

Next, a third conductive layer is formed on the second insulating layer 207 by sputtering, vacuum evaporation, etc., a fourth resist mask is formed on the third conductive layer, and the third conductive layer is partially etched, thereby A pixel electrode 210, an electrode 221, and an electrode 222 are formed. It is to be noted that the third conductive layer is preferably formed to a thickness of greater than or equal to 30 nm and less than or equal to 200 nm, more preferably greater than or equal to 50 nm and less than or equal to 100 nm. Through the above steps, element regions 260 are formed on the substrate 200 with the separation layer 250 interposed therebetween (see FIG. 6C ).

For the third conductive layer used as the pixel electrode, it is preferable to use materials such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or indium tin oxide with silicon oxide added to the light-transmitting conductive material. Alternatively, a material composed of 1 to 10 graphene flakes (corresponding to one layer of graphite) may be used. Alternatively, conductive compositions containing conductive macromolecules (also referred to as conductive polymers) may be used to form the third conductive layer. As the conductive macromolecule, a so-called π-electron conjugated conductive macromolecule can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, and a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

In this embodiment, as the third conductive layer, an 80 nm-thick ITO layer was formed, and a fourth resist mask was formed and the third conductive layer was partially etched, thereby forming the pixel electrode 210, the electrode 221, and the electrode 222.

The pixel electrode 210 is electrically connected to the drain electrode 206b through the contact hole 208 . The electrode 221 is electrically connected to the wiring 212 through the contact hole 219 . The electrode 222 is electrically connected to the wiring 216 through the contact hole 220 .

In the contact hole 219 and the contact hole 220, it is important to keep the wiring 212 and the wiring 216 from being exposed and covered with an oxide conductive material such as ITO. Since the wiring 212 and the wiring 216 are metal layers, if the wiring 212 and the wiring 216 are left exposed, the exposed surface is oxidized, and the contact resistance with FPC or the like will increase, thereby causing a decrease in reliability. The exposed surfaces of the wiring 212 and the wiring 216 are covered with an oxide conductive material such as ITO, whereby an increase in contact resistance can be prevented, and thus the reliability of the liquid crystal display device can be improved.

Although not shown in the figure, the transistors provided on the element region 206 are easily broken due to static electricity or the like; therefore, it is preferable to provide a protection circuit. The protection circuit is preferably formed using a non-linear element.

According to the present embodiment, a liquid crystal display device can be manufactured by a smaller number of photolithography processes than conventionally. Therefore, liquid crystal display devices can be manufactured at lower cost and with higher productivity. In addition, the element region 206 required to operate the liquid crystal display device is provided on the substrate 200 with the separation layer 250 interposed therebetween; thus the element region 206 can be separated from the substrate 200 and transferred to another support.

This embodiment can be freely combined with any other embodiments.

(Example 2)

In this embodiment, an example of a process that is partially different from Embodiment 1 is described with reference to FIGS. 7A to 7C . Note that the same reference numerals are used for the same parts as in Embodiment 1, and a detailed description of the parts with the same reference numerals is omitted here. Also, in the present embodiment, only an example of the steps of the transistor section is described with reference to the drawings.

First, as in Embodiment 1, a separation layer 250 is formed on the substrate 200 having an insulating surface, a first conductive layer is formed on the separation layer 250, a first resist mask is formed on the first conductive layer, and then using The first resist mask selectively etches the first conductive layer to form the gate electrode 202 .

An insulating layer serving as a base layer may be formed between the separation layer 250 and the gate electrode 202 . In this embodiment, a base layer 201 is formed. The base layer 201 has a function of preventing impurity elements (such as Na) from diffusing from the substrate 200, and can be formed using a film selected from a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a hafnium oxide film, an aluminum oxide film , gallium oxide film and gallium aluminum oxide film. The structure of the substrate 201 is not limited to a single-layer structure, and may be a layered structure of a plurality of the above-mentioned films.

In this embodiment, the deposition temperature of the semiconductor layer formed later is higher than or equal to 200°C and lower than or equal to 450°C, and the temperature of the heat treatment performed after the formation of the semiconductor layer is higher than or equal to 200°C and lower than or equal to 450°C. Therefore, for the gate electrode 202 , a layered structure in which copper is the lower layer and molybdenum is the upper layer or a layered structure in which copper is the lower layer and tungsten is the upper layer may be employed.

Next, as in Embodiment 1, a first insulating layer 204 is formed on the gate electrode 202 by a CVD method, a sputtering method, or the like. FIG. 7A is a cross-sectional view showing a structure obtained through steps up to and including this step.

Then, on the first insulating layer 204, a first semiconductor layer is formed to a thickness of greater than or equal to 1 nm and less than or equal to 10 nm. In this example, the first semiconductor layer was formed to a thickness of 5 nm in an oxygen atmosphere, an argon atmosphere, or a mixed atmosphere of argon and oxygen under the following conditions: using a target for an oxide semiconductor (for an In-based - a target of an oxide semiconductor of Ga-Zn (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]); the distance between the substrate and the target is 170mm; the substrate temperature is 250°C; the pressure is 0.4Pa; And the direct current (DC) power is 0.5kW.

Afterwards, a first heat treatment is performed, and the substrate is placed in a nitrogen atmosphere or a dry air atmosphere. The temperature of the first heat treatment is set to be higher than or equal to 200°C and lower than or equal to 450°C. In the first heat treatment, heating is performed for greater than or equal to 1 hour and less than or equal to 24 hours. Through the first heat treatment, the first crystalline semiconductor layer 748a is formed (see FIG. 7B ).

Next, a second semiconductor layer is formed on the first crystalline semiconductor layer 748a to a thickness greater than 10 nm. In this embodiment, the second semiconductor layer was formed to a thickness of 25 nm in an oxygen atmosphere, an argon atmosphere, or a mixed atmosphere of an argon atmosphere and an oxygen atmosphere under the following conditions: using a target for an oxide semiconductor (for A target based on an oxide semiconductor of In-Ga-Zn (In2O3:Ga2O3:ZnO=1:1:2 [molar ratio]); the distance between the substrate and the target is 170mm; the substrate temperature is 400°C; the pressure is 0.4 Pa; and a direct current (DC) power of 0.5 kW.

Then, a second heat treatment is performed, and the substrate is placed in a nitrogen atmosphere or a dry air atmosphere. The temperature of the second heat treatment is set to be higher than or equal to 200°C and lower than or equal to 450°C. In the second heat treatment, heating is performed for greater than or equal to 1 hour and less than or equal to 24 hours. Through the second heat treatment, a second crystalline semiconductor layer 748b is formed (see FIG. 7C ).

Subsequent steps are performed according to Example 1. After forming the source electrode 206a, the drain electrode 206b, and the second insulating layer 207, a step of simultaneously forming the first opening and the second opening is performed using a single resist mask. The first opening is formed by etching a portion of the second insulating layer 207 overlapping the drain electrode 206b. By etching part of the second insulating layer 207, part of the first crystalline semiconductor layer 748a, part of the second crystalline semiconductor layer 748b, part of the first insulating layer 204, and part of the second insulating layer 207 that do not overlap the source electrode 206a and the drain electrode 206b to form the second opening. Therefore, the number of steps can be reduced.

After that, the transistor 111 can be obtained through steps similar to those in Embodiment 1. Note that, in the case of employing the present embodiment, the semiconductor layer including the channel formation region of such a transistor has a layered structure of the first crystalline semiconductor layer 748a and the second crystalline semiconductor layer 748b. After the first crystalline semiconductor layer 748a is formed, a first heat treatment is performed so that the first crystalline semiconductor layer 748a includes CAAC. Then, the second crystalline semiconductor layer 748b is formed and subjected to a second heat treatment, whereby a crystal (CAAC) grows in the second crystalline semiconductor layer 748b with the first crystalline semiconductor layer 748a as a seed crystal. Therefore, an oxide semiconductor including CAAC can be efficiently formed.

A transistor having a layered structure of the first crystalline semiconductor layer and the second crystalline semiconductor layer has stable electrical characteristics. When the transistor is irradiated with light and subjected to a bias temperature (BT) test, the amount of change in the threshold voltage of the transistor may be reduced.

This embodiment can be freely combined with any other embodiments.

(Example 3)

In this embodiment, an example of the structure of a thin, lightweight and remarkably tough semiconductor device separated from the substrate 200 with the element region 206 formed in Embodiments 1 and 2 will be described with reference to FIGS. 8A and 8B And it is manufactured by means of being arranged on different supports. Furthermore, an example of a method for manufacturing a semiconductor device will be described with reference to FIGS. 9A to 9C , FIGS. 10A to 10C , and FIGS. 11A and 11B .

To describe the sectional view of the liquid crystal display device in FIG. 8B , the sectional view of the element region 206 described in Embodiment 1 is used for the sectional view of the pixel portion 850 . It is to be noted that the description will be made under the assumption that the driving method of the liquid crystal display device in this embodiment is a vertical alignment (VA) mode, and that the liquid crystal display device is a reflective monochrome device including a liquid crystal material exhibiting a blue phase as a liquid crystal layer. LCD display device.

The VA mode is a method of controlling the alignment of liquid crystal molecules of a liquid crystal display panel in which the liquid crystal molecules are vertically aligned to the panel surface when no voltage is applied. Some examples are given as vertical alignment patterns. For example, a multi-domain vertical alignment (MVA) mode, a patterned vertical alignment (PVA) mode, an advanced super vision (ASV) mode, etc. may be given. Furthermore, it is possible to use a method called domain doubling or multi-domain design, where a pixel is divided into regions (sub-pixels) and the molecules are aligned in different directions in their respective regions. The VA mode is a method of controlling the alignment of liquid crystal molecules of a liquid crystal display panel in which the liquid crystal molecules are vertically aligned to the panel surface when no voltage is applied.

It is to be noted that, for the liquid crystal display device in this embodiment, the VA mode is used; however, the embodiment of the present invention is not limited thereto. For example, modes such as TN (Twisted Nematic) mode, IPS (In-Plane Switching) mode, FFS (Fringe Field Switching) mode, ASM (Axisymmetric Aligned Microcell) mode, OCB (Optically Compensated Birefringence) mode may be used instead , FLC (ferroelectric liquid crystal) mode, or AFLC (antiferroelectric liquid crystal) mode driving method.

<Example of Structure of Liquid Crystal Display Device>

FIG. 8A is a plan view of a panel in which an element region 260 and a liquid crystal material 840 are sealed with a sealant 820 between a first support 800 and a second support 810 . FIG. 8B is a cross-sectional view along the dotted line M-N in FIG. 8A.

The first support 800 has a fracture toughness greater than or equal to 1.5 [MPa·m ^1/2 ], and is provided with the element region 260 with an adhesive 808 for fixing interposed between the first support 800 and the element region 260 . Using a material with a fracture toughness greater than or equal to 1.5 [MPa·m ^1/2 ] as the first support member 800 makes it possible to manufacture a thin, lightweight, and remarkably strong liquid crystal display device.

The fracture toughness of the second support member 810 is greater than or equal to 1.5 [MPa·m ^1/2 ]. The fourth conductive layer 814 is disposed on one surface of the second supporter 810 , and the polarizing filter 860 is disposed on the other surface of the second substrate 810 . Using a material with a fracture toughness greater than or equal to 1.5 [MPa·m ^1/2 ] as the second support member 810 makes it possible to manufacture a thin, lightweight, and remarkably strong liquid crystal display device.

The sealant 820 , the liquid crystal material 840 and the first conductive material 845 are sandwiched between the first support 800 provided with the element region 206 and the second support 810 provided with the fourth conductive layer 814 . It is to be noted that the sealant 820 is provided to surround the pixel portion 850 ; therefore, the liquid crystal material 840 does not leak out of the sealant 820 . The first conductive material 845 is provided to electrically connect the wiring 212 formed in the element region 260 and the fourth conductive layer 814 formed on the second support. Accordingly, the alignment of the liquid crystal material 840 can be changed by applying a voltage between the fourth conductive layer 814 and the pixel electrode 210 .

The input terminal 880 is provided outside the area surrounded by the sealant 820 provided on the first support 800 , and the external wirings 870 a and 870 b are connected to the wiring 216 in the element area 260 through the second conductive material 855 . Each of the external wirings 870 a and 870 b has a function of externally supplying power and signals necessary to operate the liquid crystal display device through the second conductive material 855 .

With the above structure, a liquid crystal display device that is thin, lightweight, and not easily broken can be manufactured.

<Method for Manufacturing Liquid Crystal Display Device>

Next, an example of a method of manufacturing the above-described liquid crystal display device will be described with reference to FIGS. 9A to 9C , FIGS. 10A to 10C , and FIGS. 11A and 11B . Note that, in this embodiment, the manufacturing process of the liquid crystal display device is described by dividing it into the following steps: "the step of providing the element region on the first support", "the step of forming the second support" and "Procedure for sealing the liquid crystal layer".

<Procedure for Setting Component Areas on the First Support>

First, the temporary support base 902 is bonded to the surface of the element region 260 formed on the substrate 200 in Embodiment 1 with the adhesive 900 for separation, the separation layer 250 is interposed between the substrate 200 and the element region 260, and then the element region 260 is removed from the The substrate 200 is separated and transferred to a temporary support base 902 (see FIG. 9A ). It is to be noted that, in this specification, the step of separating the element region 260 along the separation layer 250 and transferring the element region 260 to the temporary support base 902 is referred to as a transfer step.

As the separation adhesive 900, an adhesive that can be removed from the temporary support base 902 and the element region 260 as needed, such as an adhesive that is soluble in water or an organic solvent or an adhesive that can be plasticized by ultraviolet light irradiation, can be used. mixture. By using any one of coating machines such as spin coater, slit coater, gravure coater and roll coater or such as flexo printing machine, offset printing machine, gravure printing machine, screen Either of a printing machine and a printing machine of an inkjet machine, the separation adhesive 900 is preferably formed thin and has a uniform thickness.

As the temporary support base 902, a tape whose surface adhesion can be arbitrarily reduced, such as a UV release tape and a heat release tape, can be used. Alternatively, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, a metal substrate, a plastic substrate, or the like may be used. It is to be noted that, in the case of using a tape whose surface adhesion can be arbitrarily reduced, the separating adhesive 900 is not alone necessary. In the case where a plastic substrate is used as the temporary support base 902, it is preferable to use a plastic substrate whose thermal resistance is high enough to withstand the temperature of a process performed later.

It is to be noted that there is no particular limitation on the method for bonding the temporary support base 902 to the element region 260 . When a flexible material such as a strip is used as the temporary support base 902, for example, an apparatus that can perform bonding with a roller (also called a roller laminator) can be used. Therefore, the element region 206 and the temporary support base 902 can be reliably bonded to each other without air bubbles or the like in between.

In this embodiment, a water-soluble adhesive (hereinafter referred to as water-soluble adhesive) that is cured by ultraviolet light irradiation is used as the separation adhesive 900 and is lightly coated with a spin coating device. on the surface of the element region 260, and a curing process is performed. After that, a UV release tape (a tape whose adhesive force can be weakened by UV irradiation) as a temporary support base is adhered to the release adhesive 900 using a roll laminator.

Any of various methods may be suitably used to separate element region 260 from substrate 200 . For example, the separation layer 250 is made of tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), and silicon (Si) or an alloy containing any of the above elements as its main component or a compound is formed, and in the case where a metal oxide film is formed on the surface of the separation layer 250 (for example, as described in Embodiment 1, after the separation layer 250 is formed, an oxygen-containing film is formed as the base layer 201 case), the metal oxide film is crystallized and embrittled, and a force (a force to separate the temporary support base 902 from the substrate 200 ) is applied so that the element region 260 can be separated along the separation layer 250 .

In addition, when the hydrogen-containing amorphous silicon film is formed as the separation layer 250, the hydrogen-containing amorphous silicon film is removed by laser irradiation or etching, so that the element region 260 can be separated from the substrate 200. When a film containing nitrogen, oxygen, hydrogen, etc. (for example, an amorphous silicon film containing hydrogen, an alloy film containing hydrogen, an alloy film containing oxygen, etc.) is used as the separation layer 250, the separation layer is irradiated with laser light to cause the separation Nitrogen, oxygen, or hydrogen contained in the layer 250 is released as a gas, thereby facilitating separation of the element region 260 from the substrate 200 . In addition, a method of removing the separation layer 250 by etching in which a halogen fluoride gas such as NF3, BrF3, or ClF3 is used may be used.

In the case where an organic resin is used for the separation layer 250, inherent stress in the organic resin can be used for separation.

In addition, the above-mentioned various separation methods may be used in combination to facilitate the separation process. Specifically, after performing laser irradiation on part of the separation layer, etching part of the separation layer with gas, solution, etc., or removing part of the separation layer with mechanical force of a sharp knife, scalpel, etc., separation can be performed with physical force (by a machine, etc.) , so that the separation layer and the element region can be easily separated from each other. In the case where the separation layer 250 is formed to have a layered structure of metal and metal oxide, the layer to be separated can be easily separated from The separation layer is physically separated.

Physically separating the element region 260 achieves separation of a larger area in a shorter time, compared to a method of separating the element region 260 by removing the separation layer with a solution, gas, or the like. In addition, since no solution or gas is used, the safety level is high. Therefore, as a method of separating the element region 260 from the substrate 200 , the method of applying a force to separate is most advantageous in terms of productivity and safety.

In the case of performing separation by physical means, separation may be performed while injecting a liquid such as water. Therefore, adverse effects of static electricity on the element region 260 due to the separation operation (such as damage of semiconductor elements destroyed by static electricity) can be suppressed.

It is to be noted that, in the case where an oxide semiconductor is used for the semiconductor layer 205, even when static electricity is generated, the semiconductor layer 205 can be prevented from being damaged by static electricity. This is because an oxide semiconductor has a higher withstand voltage and a lower possibility of dielectric breakdown than a general semiconductor layer including a silicon material.

In the process of separating the element region 260 along the separation layer 250 , the substrate 200 is fixed so as not to move or bend as much as possible, which can suppress the force locally applied to the element region 260 . Therefore, the element region 260 can be separated without any problem (eg, the element region 260 is not broken). As a method for fixing the substrate 200 , for example, a method of fixing the substrate 200 to a stable base using an adhesive material, a method of fixing the substrate 200 using a vacuum chuck, or the like may be employed. It is preferable to fix the substrate 200 using a vacuum chuck in consideration of the trouble of separating the substrate 200 and the reuse of the substrate 200 . In particular, it is preferable to use a vacuum chuck (also referred to as a porous chuck) having a porous surface because the entire surface of the substrate 200 can be fixed with uniform force.

It is to be noted that before the separation adhesive 900 is provided on the element region 260, it is preferable to perform fluid jet cleaning, ultrasonic cleaning, plasma cleaning, UV cleaning, ozone cleaning, etc. on the element region 260 so as to remove Dust and organic components on the surface.

Next, the first support 800 is bonded to the other surface of the element region 260 with an adhesive 808 for fixing interposed therebetween (see FIG. 9B ).

As the material of the fixing adhesive 808, various curable adhesives can be used, for example, photo-curable adhesives such as UV-curable adhesives, reaction-curable adhesives, heat-curable adhesives, and anaerobic adhesives. adhesive.

By using any one of coating machines such as spin coater, slit coater, gravure coater and roll coater or such as flexo printing machine, offset printing machine, gravure printing machine, screen Either of a printer and an inkjet printer, the fixing adhesive 808 is preferably formed thin and has a uniform thickness.

For the first support 800 , any of various materials having high toughness (specifically, fracture toughness greater than or equal to 1.5 [MPa·m ^1/2 ]) is used. For example, an organic resin substrate, an organic resin film, a metal substrate, a metal thin film, or the like is used. Therefore, it is possible to manufacture a liquid crystal display device that is thin, lightweight, and not easily broken even when an external force is applied such as impact or bending. It should be noted that various materials with high toughness generally have high flexibility and toughness, so that the first support member 800 with high toughness can bend freely. The thickness of the first supporter 800 may be appropriately determined depending on the usage application of the liquid crystal display device. For example, when the liquid crystal display device is set to be bent along a shape such as a curved surface, or rolled up to be carried, the first support member 800 may be thin. When the liquid crystal display device is used under a condition of constant applied load, the first supporter 800 may be thick.

As the organic resin substrate and the organic resin film, for example, substrates and films including at least one resin selected from the following resins as components can be used: polyethylene terephthalate (PET) resin, polyethersulfone (PES) resin , polyethylene naphthalate (PEN) resin, polyvinyl alcohol (PVA) resin, polycarbonate (PC) resin, nylon resin, acrylic resin, polyacrylonitrile resin, polyether ether ketone (PEEK) resin, Polystyrene (PS) resin, polysulfone (PSF) resin, polyetherimide (PEI) resin, polyarylate (PAR) resin, polybutylene terephthalate (PBT) resin, polyimide Amine (PI) resin, polyamide (PA) resin, polyamideimide (PAI) resin, polyisobutylene (PIB) resin, chlorinated polyether (CP) resin, melamine (MF) resin, epoxy (EP) Resin, polyvinylidene chloride (PVdC) resin, polypropylene (PP) resin, polyacetal (POM) resin, fluororesin (polytetrafluoroethylene (PTFE)), phenol (PF) resin, furan (FF) resin , unsaturated polyester resin (fiber reinforced plastic (FRP)), cellulose acetate (CA) resin, urea (UF) resin, xylene (XR) resin, diallyl phthalate (DAP) resin, polyvinyl acetate ( PVAc) resin, polyethylene (PE) resin, and ABS resin.

As the metal substrate or metal thin film, for example, aluminum (Al), titanium (Ti), nickel (Ni), chromium (Cr), molybdenum (Mo), tantalum (Ta), beryllium (Be), zirconium (Zr), Gold (Au), silver (Ag), copper (Cu), zinc (Zn), iron (Fe), lead (Pb), or zinc (Sn), or a substrate including an alloy containing any of the above elements or film.

As in this embodiment, in the case of a reflective liquid crystal display device that displays images using reflection of external light, it is preferable to select the above-mentioned metal substrate or metal thin film having a high visible light reflectance as the first supporting member 800 to be used. Material. In particular, a metal substrate or a metal thin film having a coefficient of thermal expansion of 20 ppm/°C or less is preferable. In the case of a transmissive type and a transflective type liquid crystal display device that uses a backlight as a light source to display images, an organic resin substrate and an organic resin film having a high visible light transmittance are preferably used as the first support member 800, and more preferably, the organic resin film used An organic resin substrate and an organic resin film having a coefficient of thermal expansion less than or equal to 20 ppm/°C and having no retardation (birefringent retardation).

It is to be noted that in the present embodiment, the first support 800 has a single-layer structure; however, a protective layer may be formed on the top or bottom surface of the first support 800 . As the protective layer, an inorganic thin film such as a silicon oxide (SiO2) film, a silicon nitride (SiN) film, a silicon oxynitride (SiON) film, and a silicon oxynitride (SiNO) film, such as an aluminum (Al) film or Metal film of magnesium (Mg) film, or oxide film of any metal. It is especially preferable to use a film having low water vapor permeability, low gas permeability, and low UV transmittance. The protective layer is preferably formed by, for example, sputtering or plasma CVD.

Note that, in the case of a transmissive or transflective liquid crystal display device, an inorganic film, a metal oxide film, or the like having a relatively high visible light transmittance is preferably used. On the other hand, in the case of a reflective liquid crystal display device, it is preferable to use a metal film having a high reflectance of visible light.

Alternatively, as a protective layer, a solvent-resistant resin may be used. The composition of the protective layer may be appropriately selected depending on the kind of chemical solution used for substrate cleaning and the kind of solvent included in the alignment film. The composition of the protective layer can be suitably selected from, for example, polyvinyl chloride (PVC) resin, polyvinyl alcohol (PVA) resin, polyisobutylene (PIB) resin, polymethyl methacrylate (PMMA) resin, cellulose acetate (CA) resin , Urea (UF) resin, xylene (XR) resin, diallyl phthalate (DAP) resin, polyvinyl acetate (PVAc) resin, polyethylene (PE) resin, polyamide (PA) (nylon) resin, Polycarbonate (PC) resin, chlorinated polyether (CP) resin, melamine (MF) resin, epoxy (EP) resin, polyvinylidene chloride (PVdC) resin, polystyrene (PS) resin, polypropylene (PP) resin, polyacetal (POM) resin, fluororesin (polytetrafluoroethylene (PTFE)), phenol (PF) resin, furan (FF) resin, unsaturated polyester resin (fiber reinforced plastic (FRP)) , ABS resin, etc. Using such a resin as a protective layer, it is possible to prevent a change in the quality of the first support caused by a chemical solution used to clean the substrate and a solvent included in the alignment film.

By using any one of coating machines such as spin coater, slit coater, gravure coater and roll coater or such as flexo printing machine, offset printing machine, gravure printing machine, screen Either of a printing machine and a printing machine of an inkjet machine, the protective layer is preferably formed thin and has a uniform thickness.

Although the first support member 800 is bonded to the other surface of the element region 206 with the fixing adhesive 808 interposed therebetween in this embodiment, when a member in which a fiber body is impregnated with an organic resin (so-called prepreg ) is used as the first support member 800, the organic resin impregnated with the fiber body has the function of the fixing adhesive 808; At this time, as the organic resin used for the member, a reaction curable resin, a thermosetting resin, a UV curable resin, or the like that is cured by additional treatment is preferably used.

In this embodiment, a stainless steel film (so-called SUS film, composed of a material containing iron as a matrix with addition of chromium, nickel, etc.) was used as the first support, and the thermosetting adhesive was gently Apply to the surface of the stainless steel film. A stainless steel film coated with a thermosetting adhesive is attached to the other surface of the element region, and a curing process is performed.

It is to be noted that before the fixing adhesive 808 is provided on the first support 800, it is preferable to perform fluid jet cleaning, ultrasonic cleaning, plasma cleaning, UV cleaning, ozone cleaning, etc. Dust and organic components on the surface of the first support 800 .

In addition, heat treatment may be performed on the first supporter 800 . Through the heat treatment, moisture and impurities attached to the first supporter 800 are removed. In addition, moisture and impurities can be removed more effectively by heat treatment in a reduced pressure state. When heat treatment is performed, a substrate whose thermal resistance is high enough to withstand heat treatment is preferably used as the first support 800 .

It is to be noted that, as for the cleaning method and heat treatment, any one of the above cleaning methods and heat treatments may be selected, or two or more of the above cleaning methods and heat treatments may be performed in combination. For example, after fluid jet cleaning is performed to remove dust attached to the first support 800, ozone cleaning is performed to remove organic components, and then heat treatment is finally performed to remove dust attached and adsorbed to the first support 800 when fluid jet cleaning is performed. moisture in. In this way, dust, organic components, and moisture on and in the first support 800 may be effectively removed.

Next, the adhesive 900 for separation and the temporary support base 902 are removed from the element region 206 .

In this embodiment, a water-soluble adhesive and a UV release tape are used as the adhesive 900 for separation and the temporary support base 902, respectively. Therefore, UV irradiation treatment was performed to first remove the temporary support base 902 and then remove the adhesive 900 for separation by washing with water.

Due to the high toughness, the first support 800 has sufficient flexibility to be deformed by applying external stress. Therefore, it is preferable to separate the temporary support base 902 from the element region 260 in a state where the substrate having high rigidity is bonded to the first support member 800 through the adhesive material between the substrate with high rigidity and the first support member 800, thereby Deformation and breakage do not occur when a load is applied to the first support member 800 in the separation operation and later steps. When substrates having high rigidity are thus bonded, manufacturing apparatuses for glass substrates and the like can be used as usual.

Through the above steps, the first support member 800 having the element region 260 on its surface with the fixing adhesive 808 interposed therebetween can be manufactured.

It is to be noted that according to this embodiment, it is not necessary to provide an alignment film in a liquid crystal display device in which a liquid crystal material exhibiting a blue phase is used as a liquid crystal layer; therefore, in FIGS. 8A and 8B, FIGS. 9A to 9C, FIGS. 10A to 10C and The alignment film is not shown in FIGS. 11A and 11B . However, in the case of a liquid crystal display device in which a liquid crystal material that does not exhibit a blue phase is used as a liquid crystal layer, an alignment film (for example, such as polyimide (PI), polyvinyl alcohol (PVA) or polycinnamic acid can be used An insulating organic material of vinyl ester (PVCi) may be formed on the element region 260 (at least on the pixel electrode 210), and rubbing treatment may be performed on the alignment film (for example, using a material with fibers (including rayon, cotton, nylon, etc.). The alignment film is rubbed against a roller or the like with fibers or the like as its main material), so that the alignment film has alignment properties.

In the case where a liquid crystal material exhibiting a blue phase is used as the liquid crystal layer, an alignment film is not necessarily provided, so rubbing treatment is also not necessary. Therefore, electrostatic discharge caused by rubbing treatment can be prevented, and damage to the liquid crystal display device during the manufacturing process can be reduced. Therefore, there is also an advantage that the productivity of liquid crystal display devices can be improved.

<Step of Forming Second Support>

Next, the second support 810 is prepared, and the fourth conductive layer 814 is provided on one surface of the second support 810 (see FIG. 10A ). It is to be noted that in the present embodiment, no color filter is provided because the description of the monochromatic liquid crystal display device is given; however, when a color liquid crystal display device is manufactured, the color filter may be provided between the second supporting member 810 and the second supporting member 810. between the fourth conductive layers 814 .

In the case of setting the color filter, three color filters of R, G and B (R, G and B correspond to red, green and blue respectively) are set in the pixel portion; however, one embodiment of the present invention Not limited to this. For example, color filters R, G, B, and W (W corresponds to white), or one or more of color filters R, G, B, and yellow, cyan, magenta, etc. may be provided. In addition, the size of the display area may vary between individual pigment dots. As a display method in the pixel portion, a progressive scanning method, an interlaced scanning method, or the like can be employed.

In addition, the second support may be appropriately provided with a black matrix (light blocking layer) or an optical member (optical substrate) such as a blocking member or an antireflection member.

In this embodiment, the case where the driving method of the liquid crystal display device is VA mode is described; therefore, the structure of the vertical electric field mode is adopted, wherein the fourth conductive layer 814 is formed on one surface of the second supporting member 810, and the liquid crystal material 840 sandwiched between the pixel electrode 210 and the fourth conductive layer 814 . However, it is not necessary to provide the fourth conductive layer 814 on the second support 810 in the case of the driving method using the horizontal electric field mode.

For the second support 810 , any of various materials having high toughness (specifically, fracture toughness greater than or equal to 1.5 [MPa·m ^1/2 ]) is used. Since the second support needs to have a property of not blocking light propagating to the outside, an organic resin substrate or an organic resin film is used. Therefore, it is possible to manufacture a liquid crystal display device that is thin, lightweight, and not easily broken even when an external force is applied such as impact or bending. It should be noted that various materials with high toughness generally have high flexibility and toughness, so that the second support member 810 with high toughness can bend freely. The thickness of the second supporter 810 may be appropriately determined depending on the usage application of the liquid crystal display device. For example, when the liquid crystal display device is set to be bent along a shape such as a curved surface, or rolled up to be carried, the second support member 810 may be thin. In addition, when the liquid crystal display device is used under a constant applied load condition, the second supporter 810 may be thin.

As the organic resin substrate and the organic resin film, materials similar to those of the first support 800 can be used.

Forming the protective layer on the second support 810 , cleaning the second support 810 , etc. are all similar to the operations of the first support 800 ; therefore, descriptions thereof are omitted here.

Due to the high toughness, the second support 810 has sufficient flexibility to be deformed by applying external stress. Accordingly, a substrate having high rigidity is preferably bonded to the second support 810 with an adhesive material interposed therebetween so as not to be deformed or broken when a load is applied to the second support 810 at a later step. When substrates having high rigidity are thus bonded, manufacturing apparatuses for glass substrates and the like can be used as usual. It is to be noted that since the substrate having high rigidity needs to be separated after the second support member 810 is bonded to the element region 260, a low-viscosity adhesive such as silicone rubber or a material whose adhesion can be weakened by light irradiation or heat treatment (eg UV release tape or thermal release tape) are preferably used as adhesives.

The fourth conductive layer 814 can be formed by a sputtering method, a plasma CVD method, a coating method, a printing method, etc. to have a single-layer structure or a layered structure, which uses a light-transmitting conductive material including, for example, the following as its main component Layer: indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, or added oxide Indium tin oxide of silicon.

In this embodiment, a polyimide film is used as the second support 810, and an ITO film is formed as the fourth conductive layer 814 on the polyimide film by sputtering to a thickness of 200 nm.

Although not shown in FIG. 10A, after forming the fourth conductive layer 814, a spacer material may be provided on the fourth conductive layer 814 as required (to keep the material for setting the distance (so-called gap) of the liquid crystal material 840 between the pixel electrode 210 and the fourth conductive layer 814 .

Note that according to the present embodiment, it is not necessary to provide an alignment film in a liquid crystal display device in which a liquid crystal material exhibiting a blue phase is used as a liquid crystal layer; therefore, the alignment film is not shown in FIG. 10A . However, in the case of a liquid crystal display device using a liquid crystal material that does not exhibit a blue phase as a liquid crystal phase, an alignment film (for example, such as polyimide (PI), polyvinyl alcohol (PVA) or polyvinyl cinnamate may be used An insulating organic material (PVCi)) can be formed on the fourth conductive layer 814, and a rubbing process can be performed on the alignment film (for example, using a material having fibers (including rayon, cotton fibers, nylon fibers, etc. as its main component) rubbing the alignment film with a roller etc.), so that the alignment film has an alignment property.

It is to be noted that although in the present embodiment, the step of forming the fourth conductive layer 814 on the second support 810 follows the step of providing the element region 260 on the first support 800 with the fixing adhesive 808 interposed therebetween. Afterwards, however, there is no restriction on the order of these manufacturing steps. These steps are preferably performed simultaneously to reduce the manufacturing time of the liquid crystal display device.

<Procedure for sealing the liquid crystal layer>

After the first support member 800 with the element region 260 provided on the surface (with the fixing adhesive 808 interposed therebetween) is prepared, a sealant 820 is provided on the periphery of the pixel portion 850 to surround the pixel portion 850, and then the pixel portion Liquid crystal material 840 is disposed on 850 (see FIG. 10B ).

In disposing the sealant 820, any of the following printing machines, such as a flexographic printing machine, an offset printing machine, a gravure printing machine, a screen printing machine, an inkjet machine, and a dispenser, may be used. As the sealant 820, any of various curable adhesives can be used, for example, light-curable adhesives such as UV-curable adhesives, reaction-curable adhesives, heat-curable adhesives, and anaerobic adhesives. adhesive. In view of productivity and influence on various materials used for liquid crystal display devices, it is preferable to use a photocurable adhesive that does not require curing treatment under high temperature conditions and has a short curing time. Additionally, the sealant 820 may include a spacer material.

It is to be noted that although only one row of sealant is provided to surround the pixel portion 850 in FIGS. 8A and 8B and FIGS. 10A to 10C , a plurality of rows of sealant 820 may be provided. By providing a plurality of lines of the sealant 820, the first supporter 800 and the second supporter 810 can be firmly bonded to each other.

As the first conductive material 845, a material including conductive particles and an organic resin is used. Specifically, a material in which conductive particles each having a diameter of several nanometers to several tens of nanometers are dispersed in an organic resin is used. As conductive particles, gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo), titanium (Ti) can be used , one or more metal particles of aluminum (Al) and carbon (C), the surface is provided with insulating particles (such as glass particles or organic resin particles) containing one or more metal films of the above metals, Silver halide particles, etc. As the organic resin contained in the first conductive material 845, one or more of the following can be used: an organic resin used as a binder for metal particles, an organic resin used as a solvent for metal particles, an organic resin used as a dispersant for metal particles An organic resin used as an agent, or an organic resin used as a coating member for metal particles. Organic resins such as epoxy resins or silicone resins can be given as representative examples.

In disposing the first conductive material 845, any one of a printing machine such as a flexo printing machine, an offset printing machine, a gravure printing machine, a screen printing machine, an inkjet machine, and a dispenser may be used.

As the liquid crystal material 840, lyotropic liquid crystals, thermotropic liquid crystals, low-molecular liquid crystals, high-molecular liquid crystals, discotic liquid crystals, ferroelectric liquid crystals, antiferroelectric liquid crystals, and the like can be used. It should be noted that the above-mentioned liquid crystal material will exhibit nematic phase, cholesteric phase, cholesteric blue phase, smectic phase, smectic blue phase, cubic phase, smectic D phase, chiral nematic phase, isotropic phase, etc. . The cholesteric and smectic blue phases are seen in liquid crystal materials having a relatively short helical pitch of 500 nm or less in cholesteric and smectic phases. The alignment of the liquid crystal material has a double-twisted structure, and the liquid crystal material has regularity with a pitch smaller than or equal to the wavelength of light. The blue phase is one of the liquid crystal phases, and when the temperature of the cholesteric liquid crystal is raised, the blue phase is generated just before the cholesteric phase changes to the isotropic phase.

Since the blue phase used in this embodiment appears only in a narrow temperature range, a liquid crystal composition mixed with 5 wt% or more of a chiral material was used for the liquid crystal material to broaden the temperature range. As for the liquid crystal composition including the blue phase liquid crystal and the chiral material, the response speed is as high as 10 μs to 100 μs; the alignment film is not necessary due to the optical isotropy; and the viewing angle dependence is small. Therefore, the quality of displayed images can be improved, and cost reduction can be achieved.

The resistivity of the liquid crystal material is greater than or equal to 1×10 ⁹ Ω·cm, preferably greater than or equal to 1×10 ¹¹ Ω·cm, more preferably greater than or equal to 1×10 ¹² Ω·cm.

Next, the surface of the second support 810 provided with the fourth conductive layer 814 is bonded to the surface of the first support 800 provided with the liquid crystal material 840 , and a curing process is performed on the sealant 820 and the first conductive material 845 .

The first support 800 and the second support 810 are preferably bonded to each other in a processing chamber maintained at reduced pressure in a vacuum bonding device or the like. In this way, bonding can be performed without air bubbles being included in the sealant 820 or the liquid crystal material 840 , and inclusion of atmospheric components in the region surrounded by the sealant 820 can be suppressed.

It is to be noted that after performing bonding, a process of applying pressure to one or both sides of the first support 800 and the second support 810 is preferably performed. Accordingly, the liquid crystal material 840 is uniformly formed in the area surrounded by the sealant 820 .

Depending on the material components of the sealant 820 and the first conductive material 845, the curing process is performed by one or more processes selected from visible light radiation, UV light irradiation, and heat treatment, thereby optimizing the sealant 820 and the first conductive material 845. Cured state of material 845 . In the case where the sealant 820 and the first conductive material 845 are, for example, photocurable materials, depending on the curing conditions of the materials, the wavelength, intensity, and time of the irradiated light are appropriately determined. Note that when using materials with the same curing conditions (such as When both the sealant 820 and the first conductive material 845 are photo-curable materials, and the wavelength and intensity of light used for curing are almost the same), the number of times of curing processing can be reduced, which is preferable. In order to improve the conductivity of the first conductive material 845 and prevent defect conduction, it is preferable to apply pressure while curing the first conductive material 845 .

In this embodiment, a method (dropping method) in which the first support 800 and the second support 810 are bonded to each other after dropping the sealant 820 and the liquid crystal material 840 is employed. Alternatively, after the sealant 820 is dropped, the first support 800 and the second support 810 are bonded to each other, and then the liquid crystal is deposited using the capillary action in the space generated between the first support 800 and the second support 810. A method of injecting the material 840 into the area surrounded by the sealant 820 (injection method).

Next, a second conductive material 855 is disposed on the electrode 222 on the first support 800 (see FIG. 11A ).

As the second conductive material 855, for example, a material including conductive particles and an organic resin is used. Specifically, a material in which conductive particles each having a diameter of several nanometers to several tens of nanometers are dispersed in an organic resin is used. As conductive particles, gold (Au), silver (Ag), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo), titanium (Ti) can be used 1. Metal particles of one or more of aluminum (Al) and carbon (C), insulating particles with metal films of one or more of the above metals, silver halide particles, or solder, etc. are provided on the surface. In addition, as the organic resin contained in the second conductive material 855, one or more of the following can be used: an organic resin used as a binder for metal particles, an organic resin used as a solvent for metal particles, an organic resin used as a solvent for metal particles, An organic resin used as a dispersant, or an organic resin used as a coating member for metal particles. Organic resins such as epoxy resins or silicone resins can be given as representative examples.

In disposing the second conductive material 855, any one of a printing machine such as a flexo printing machine, an offset printing machine, a gravure printing machine, a screen printing machine, an inkjet machine, and a dispenser may be used.

In this embodiment, an epoxy resin mixed with flaky silver particles each having a size of several nanometers to several tens of nanometers is used as the second conductive material 855 .

Next, the external wiring 870a is provided on the second conductive material 855, a connection process is performed to electrically connect the external wiring 870a and the electrode 222, and the polarizing filter 860 is bonded to the second support 810 (see FIG. 11B ).

As the external wiring 870a, for example, a printed wiring board or a flexible printed circuit (FPC) can be used. In the liquid crystal display device of this embodiment, the base substrate and the counter substrate have high toughness, and the liquid crystal display device can have flexibility; therefore, it is preferable that the external wiring 870a also have flexibility.

For the connection process, the second conductive material 855 may be treated under the condition of curing the second conductive material 855 (visible light irradiation, UV light irradiation, or heat treatment). In order to improve the conductivity of the second conductive material 855 and prevent defective conduction between the electrode 222 and the second conductive material 855, it is preferable to apply pressure when the second conductive material 855 undergoes a connection process. It is to be noted that the connection process is generally performed using a thermocompression bonding apparatus in which heat treatment is performed while pressure treatment is performed on the second conductive material 855 and the external wiring 870a.

It should be noted that no light source is provided in this embodiment because a reflective liquid crystal display device is described therein; however, in the case of a transmissive or transflective liquid crystal display device, a backlight, side light, etc. may be provided as the first support The light source on the 800 side.

In addition, it is possible to use a time-division display method (also known as a field-sequential driving method), which uses a plurality of light-emitting diodes (LEDs) as a backlight. By employing the field sequential driving method, color display can be performed without using color filters.

It is to be noted that the polarizing filter 860 is only provided on the second support member 810 in the present embodiment because a reflective liquid crystal display device is described therein; however, in the case of a transmissive or transflective liquid crystal display device, A polarizing filter may also be disposed on the first supporter 800 side. It is to be noted that although in the present embodiment, the polarizing filter 860 is bonded after the electrode 222 and the external wiring 870a are connected to each other, these steps may be performed in reverse order.

The element region 260 required to operate the liquid crystal display device manufactured through the above process is manufactured using a smaller number of photomasks than conventionally. In addition, the element region 260 is formed on the first support 800 whose fracture toughness is greater than or equal to 1.5 [MPa·m ^1/2 ]. In addition, the second support member 810 for holding the liquid crystal material 840 also has a fracture toughness greater than or equal to 1.5 [MPa·m ^1/2 ].

Therefore, the number of photomasks can be reduced without requiring complex techniques or special devices, and a thin, lightweight, and remarkably tough liquid crystal display device can be manufactured.

In addition, using a high-toughness material for the first support member 800 and the second support member 810 enables the manufacture of a liquid crystal display device that can be set to bend along a shape such as a curved surface, or can be rolled up to be carried.

This embodiment can be freely combined with any other embodiments.

(Example 4)

In this embodiment, an example of an application mode of a semiconductor device according to an embodiment of the present invention will be described. A semiconductor device according to an embodiment of the present invention can be made flexible by being separated from a substrate on which the semiconductor device has been formed. A specific example of electronic equipment including a semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS. 12A to 12F . Electronic devices include liquid crystal display devices, television devices (also referred to as TVs, TV receivers, or television receivers), cellular phones, and the like.

FIG. 12A shows a display 1201 that includes a support base 1202 and a display portion 1203 . The display portion 1203 is formed using a flexible substrate, which can realize a lightweight and thin display. In addition, the display part 1203 can be bent and detached from the support base 1202, and the display can be installed along a curved wall. A flexible display is an application mode of a semiconductor device according to an embodiment of the present invention, which can be manufactured by using the semiconductor device described in the above embodiments for the display portion 1203 . Therefore, the flexible display can be set up on both curved parts and flat surfaces; thus, it can be used in various applications.

FIG. 12B shows a rollable display 1211 that includes a display portion 1212 . A thin and large-area display that can be rolled is an application mode of the semiconductor device according to one embodiment of the present invention, which can be manufactured by using the semiconductor device described in the above embodiments for the display portion 1212 . Since the rollable display 1211 is formed using a flexible substrate, the display 1211 may be carried by being bent or rolled along the display portion 1212 . Therefore, even in the case where the rollable display 1211 is large, the display 1211 can be carried in a bag by being bent or rolled.

12C shows a tablet-type computer 1221, which includes a display portion 1222, a keyboard 1223, a touch panel 1224, an external connection port 1225, a power outlet 1226, and the like. A thin or sheet type computer is an application mode of the semiconductor device according to one embodiment of the present invention, which can be manufactured by using the semiconductor device described in the above embodiments for the display portion 1222 . The display portion 1222 is formed using a flexible substrate, which can realize a lightweight and thin computer. Also, when a part of the main body of the tablet computer 1221 is provided with a storage space, the display part 1222 may be wound and stored in the main body. Furthermore, by forming the keyboard 1223 also to be flexible, the keyboard 1223 can be rolled up and stored in the storage space of the tablet computer 1221 in a manner similar to the display portion 1222, which is convenient for carrying around. Store your computer without taking up space by bending it when not in use.

12D shows a display device 1231 having a large-sized display portion of 20 inches to 80 inches, which includes a keyboard 1233 as an operation portion, a display portion 1232, a speaker 1234, and the like. Since the display part 1232 is formed using a flexible substrate, the display device 1231 can be carried by detaching the keyboard 1233 and bending or winding it. In addition, the keyboard 1233 and the display portion 1232 can be connected wirelessly. For example, the display device 1231 can be mounted along a curved wall and can be operated with a wireless keyboard 1233 .

In the example of FIG. 12D , the semiconductor device described in the above embodiments is used for the display portion 1232 . Therefore, a thin and large-area display device can be manufactured, which is an application mode of the semiconductor device according to one embodiment of the present invention.

FIG. 12E shows an electronic book 1241, which includes a display portion 1242, operation keys 1243, and the like. Additionally, a modem may be incorporated in the electronic book 1241 . The display part 1242 is formed using a flexible substrate, and may be bent or rolled. Therefore, electronic books can also be carried without taking up space. Also, the display section 1242 can display moving images and still images such as characters.

In the example of FIG. 12E , the semiconductor device described in the above embodiments is used for the display portion 1242 . Therefore, a thin electronic book can be manufactured, which is an application mode of the semiconductor device according to one embodiment of the present invention.

FIG. 12F shows an IC card 1251, which includes a display portion 1252, connection terminals 1253, and the like. Since the display portion 1252 is formed using a flexible substrate to have a lightweight and thin sheet shape, it can be attached to the card surface. When the IC card can receive data without contact, information obtained from the outside can be displayed on the display part 1252 .

In the example of FIG. 12F , the semiconductor device described in the above embodiments is used for the display portion 1252 . Therefore, a thin IC card can be manufactured, which is an application mode of the semiconductor device according to an embodiment of the present invention.

When the semiconductor device according to one embodiment of the present invention is used for electronic equipment, even in the case where an external force such as bending is applied to the electronic equipment to generate stress thereon, damage to elements such as transistors can be suppressed; therefore, it is possible Improve the yield and reliability of semiconductor devices.

As described above, the application range of the present invention is wide, so that the present invention can be applied to electronic equipment and information display devices in various fields.

(Example 5)

In this embodiment, the liquid crystal display device manufactured according to Embodiment 3 is used as a display device for switching the left-eye image and the right-eye image at high speed, and referring to FIGS. 13A and 13B, it is described that viewing with special glasses for synchronizing the video of the display device can be an activity. Examples of 3D images of images or still images.

FIG. 13A shows an outline view in which a display device 1311 and dedicated glasses 1301 are connected to each other with a cable 1303 . In the special glasses 1301, the shutters provided in the left eye panel 1302a and the right eye panel 1302b are alternately opened and closed, whereby the user can see the image of the display device 1311 as a 3D image.

In addition, FIG. 13B is a block diagram showing main configurations of a display device 1311 and dedicated glasses 1301 .

A display device 1311 shown in FIG. 13B includes a display control circuit 1316 , a display portion 1317 , a timing generator 1313 , a source line driver circuit 1318 , an external operation unit 1322 , and a gate line drive circuit 1319 . A semiconductor device according to one embodiment of the present invention may be used for the display portion 1317 . It is to be noted that the output signal changes according to the operation of the external operation unit 1322 such as a keyboard.

In the timing generator 1313, a start pulse signal and the like are formed, and a signal for synchronizing the left-eye image with the shutter of the left-eye panel 1302a, a signal for synchronizing the right-eye image with the shutter of the right-eye panel 1302b, and the like are formed.

The synchronization signal 1331 a of the image for the left eye is input to the display control circuit 1316 so that the image for the left eye is displayed on the display section 1317 . At the same time, a synchronization signal 1330a for opening the shutter of the left-eye panel 1302a is input to the left-eye panel 1302a. Furthermore, a synchronization signal 1331b of the right-eye image is input to the display control circuit 1316 so that the right-eye image is displayed on the display section 1317 . At the same time, a synchronization signal 1330b for opening the shutter of the right-eye panel 1302b is input to the right-eye panel 1302b.

Since left-eye images and right-eye images are switched at high speed, the display device 1311 preferably adopts a continuous color mixing method (field sequential method) in which color display is performed by time division using light emitting diodes (LEDs).

In addition, since the field sequential method is adopted, it is preferable that the timing generator 1313 inputs the synchronization signals 1330a and 1330b to the light emitting diodes of the backlight part. It is to be noted that the backlight section includes LEDs of R, G, and B colors.

This embodiment can be combined with any other embodiments in this specification as desired.

This application is based on Japanese Patent Application S/N.2010-204930 filed with Japan Patent Office on September 13, 2010, the entire contents of which are hereby incorporated by reference.

Claims (24)

1. A liquid crystal display device, comprising: A pixel on a substrate, the pixel comprising: Thin film transistors, including: first conductive layer; an oxide semiconductor layer on the first conductive layer; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; and an insulating layer on the source and drain electrodes; and Liquid crystal components, including: a third conductive layer electrically connected to one of the source and drain electrodes; and a liquid crystal material on the third conductive layer, and The external input terminal on the substrate, the external input terminal includes a terminal, and the terminal includes: the first conductive layer; the oxide semiconductor layer on the first conductive layer; the insulating layer on the oxide semiconductor layer; and the third conductive layer on the insulating layer, the third conductive layer being electrically connected to the first conductive layer in an opening formed in the oxide semiconductor layer and the insulating layer, Wherein, the third conductive layer is in direct contact with a side surface of the oxide semiconductor layer in the pixel. 2. The liquid crystal display device according to claim 1, wherein The thin film transistor further includes a gate insulating layer disposed between the first conductive layer and the oxide semiconductor layer, and The third conductive layer directly contacts a side surface of the gate insulating layer in the pixel. 3. The liquid crystal display device according to claim 2, wherein In the pixel, the insulating layer is in contact with the oxide semiconductor layer in a first region overlapping the first conductive layer, and Electrical connection of the third conductive layer to one of the source electrode and the drain electrode is performed in a contact hole formed in the insulating layer. 4. The liquid crystal display device as claimed in claim 3, wherein The insulating layer is in contact with the oxide semiconductor layer in a second region not overlapping the first conductive layer. 5. The liquid crystal display device according to claim 1, further comprising a base layer between the thin film transistor and the substrate, Wherein the third conductive layer is in contact with the base layer in the pixel. 6. The liquid crystal display device according to claim 1, wherein The oxide semiconductor layer includes an element selected from gallium and indium. 7. The liquid crystal display device according to claim 1, wherein: The substrate is flexible. 8. An electronic device having the liquid crystal display device according to claim 1. 9. A liquid crystal display device, comprising: A pixel on a substrate, the pixel comprising: Thin film transistors, including: an oxide semiconductor layer; a source electrode and a drain electrode electrically connected to the oxide semiconductor layer; an insulating layer on and in contact with the source and drain electrodes; and a third conductive layer on the insulating layer, the third conductive layer in contact with the top surface of the insulating layer; Liquid crystal components, including: the third conductive layer electrically connected to one of the source electrode and the drain electrode; and a liquid crystal material on the third conductive layer; and Capacitors, including: capacitor wiring; a dielectric layer on the capacitor wiring, the dielectric layer including the oxide semiconductor layer and the insulating layer; and the third conductive layer on the dielectric layer; and a base layer between the thin film transistor and the substrate, wherein the third conductive layer is in direct contact with side surfaces of the oxide semiconductor layer and side surfaces of the insulating layer in the pixel, and Wherein, the third conductive layer is in contact with the base layer in the pixel. 10. The liquid crystal display device according to claim 9, wherein The thin film transistor further includes a gate electrode and a gate insulating layer disposed between the gate electrode and the oxide semiconductor layer, and The third conductive layer directly contacts a side surface of the gate insulating layer in the pixel. 11. The liquid crystal display device according to claim 10, wherein the insulating layer is in contact with the oxide semiconductor layer in a first region overlapping the gate electrode, and Electrical connection of the third conductive layer to one of the source electrode and the drain electrode is performed in a contact hole formed in the insulating layer. 12. The liquid crystal display device according to claim 11, wherein The insulating layer is in contact with the oxide semiconductor layer in a second region not overlapping the gate electrode. 13. The liquid crystal display device according to claim 9, wherein The third conductive layer is in contact with a side surface of the dielectric layer. 14. The liquid crystal display device according to claim 9, wherein The capacitor further includes an electrode between the third conductive layer and the capacitor wiring, and The electrodes are electrically connected to the third conductive layer. 15. The liquid crystal display device according to claim 9, wherein, The oxide semiconductor layer includes an element selected from gallium and indium. 16. The liquid crystal display device according to claim 9, wherein The substrate is flexible. 17. An electronic device having the liquid crystal display device according to claim 9. 18. A method for manufacturing a liquid crystal display device, the method comprising: forming a separation layer on the substrate; forming a gate electrode and a capacitor wiring on the separation layer; forming a gate insulating layer on the gate electrode and the capacitor wiring; forming an oxide semiconductor layer on the gate insulating layer; forming a source electrode and a drain electrode on the oxide semiconductor layer; forming an insulating layer on the source electrode, the drain electrode, and the oxide semiconductor layer such that the insulating layer is in contact with the source electrode and the drain electrode; Simultaneously forming the first contact hole and the second contact hole; forming a third conductive layer on the insulating layer, the first contact hole, and the second contact hole such that the third conductive layer is in contact with a top surface of the insulating layer; and separating the gate electrode, the gate insulating layer, the oxide semiconductor layer, the source electrode, the drain electrode, the insulating layer, and the third conductive layer from the substrate, wherein the first contact hole is formed in the insulating layer to expose a portion of one of the source electrode and the drain electrode, wherein the second contact hole penetrates the gate insulating layer, the oxide semiconductor layer and the insulating layer, and Wherein, a capacitor is formed of the capacitor wiring, the gate insulating layer, the oxide semiconductor layer, the insulating layer and the third conductive layer, wherein the gate insulating layer, the oxide semiconductor layer and The insulating layer serves as a dielectric layer. 19. The method of claim 18, wherein, The third conductive layer is in contact with one of the source electrode and the drain electrode in the first contact hole. 20. The method of claim 18, wherein, The third conductive layer is in contact with a side surface of the oxide semiconductor layer in the second contact hole. 21. The method of claim 18, wherein, The third conductive layer contacts a side surface of the gate insulating layer in the second contact hole. 22. The method of claim 18, further comprising the step of forming a base layer before forming the gate electrode, wherein the formation of the second contact hole is performed such that the base layer is exposed in the second contact hole. 23. The method of claim 22, wherein, The third conductive layer is in contact with the base layer in the second contact hole. 24. The method of claim 18, wherein, The oxide semiconductor layer includes an element selected from gallium and indium.