CN102412811B - Adjustable non-overlapping clock signal generating method and generator - Google Patents
Adjustable non-overlapping clock signal generating method and generator Download PDFInfo
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Abstract
The invention discloses an adjustable non-overlapping clock signal generating method and generator, and the method is characterized in that a square signal generated by an oscillating circuit is respectively output to at least 2 duty-ratio regulating circuits; duty-ratio regulation of the square signal is achieved by each duty-ratio regulating circuit through control signals with different duty ratios, thus output signals with different duty ratios of the at least two circuits are obtained, and the output signals with different duty ratios are non-overlapping clock signals. The adjustable non-overlapping clock signal generator provided by the invention has the characteristics of adjustable duty ratio and wide frequency output range.
Description
Technical field
The present invention relates to a kind of non-overlapping clock generator, be specifically related to a kind of adjustable non-overlapping clock signal generating method and generator.
Background technology
Switching capacity (SC) technology is the focus in cmos vlsi.Switched-capacitor circuit not only is widely used in analog (as filter, switching capacity DC-DC transducer and voltage comparator etc.), also penetrates into mixed signal module (as analog to digital converter, sigma-delta modulator and sampled analog structure).Non-overlapped clock generator is used to the switch that control capacitance discharges and recharges, and is one of nucleus module of switched-capacitor circuit.Traditional non-overlapping clock Generator Design is general to be adopted with/NOR gate and chain of inverters and forms delay unit.Although researcher has in the past proposed different methods for designing to the non-overlapping clock generator, clock circuit module wherein mostly is independent of input generator, can only be therefore all shaping circuit.In these circuit, define the parameter of non-overlapping clock to (clk1, clk2) attribute, such as duty ratio, non-overlapped time interval △ τ [clk1, clk2] and rise/fall time, all depend on the formation of delay cell.In case circuit is integrated, these parameters can not change.In addition, in the concept field of this kind traditional design, due to the restriction of delay cell number, during being only limited to, arrives tandem circuit high-frequency application.Have the researcher to propose to be suitable for the circuit design that low frequency is applied, but required number of transistors reach up to a hundred.Some researchers have recognized oscillator and the integrated importance of clock, propose to use digital controlled oscillator (DCO) structure to realize occurring to from oscillator signal the overall process that non-overlapping clock produces.But, in order to control the right attribute of non-overlapping clock, adopted DCO, level translator and some other digital circuit, make circuit structure become very complicated.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of adjustable non-overlapping clock signal generating method and generator, and it has the advantages that duty ratio is adjustable and the frequency output area is wide.
For addressing the above problem, the present invention is achieved by the following technical solutions:
A kind of adjustable non-overlapping clock signal generating method of the present invention, the square-wave signal that oscillating circuit produces is input to respectively at least 2 road duty ratio adjusting circuits, every 1 road duty ratio adjusting circuit is realized the duty cycle adjustment of square-wave signal under the effect of different duty control signal, obtain thus the output signal that at least 2 tunnels have different duty, these output signals with different duty are the non-overlapping clock signal.Above-mentioned oscillating circuit mainly consists of input control circuit and the end to end delay unit of N level, and wherein every 1 grade of delay unit comprises transmission gate and the vibration inverter of mutual formation series connection, and above-mentioned N is equal to or greater than 3 odd number; The input voltage signal of outside input forms the complementary voltage signal after input control circuit is adjusted, the voltage swing of this complementary voltage signal is voltage poor of the voltage of power supply and input voltage signal.Above-mentioned input voltage signal and complementary voltage signal send into respectively the transmission gate of every 1 grade of delay unit 2 control ends, allow all transmission gates change between conducting and cut-off state, and the square-wave signal that impels delay unit to produce to have the broadband tunable range.
Above-mentioned every 1 road duty ratio adjusting circuit mutually forms input inverter in parallel and controls inverter by 2 and forms; Under the adjusting of the duty cycle control signal from controlling the inverter input, the overturn point that changes input inverter realizes inputting the duty cycle adjustment of square-wave signal from the square-wave signal of input inverter input input.
Above-mentioned clock method also is included in 2 of serial connections on the output of input inverter and mutually forms middle the inverter of series connection and export the steps that inverter improves the duty ratio adjusting circuit signal output waveform.
A kind of adjustable non-overlapping clock signal generator of the present invention, comprise the clock generator body.This clock generator body mainly is comprised of oscillating circuit and 2 road duty ratio adjusting circuits at least; Wherein the duty ratio adjusting circuit more than 2 roads or 2 tunnels is parallel with one another, and the input of every 1 road duty ratio adjusting circuit all is connected with the output of oscillating circuit; On every 1 road duty ratio adjusting circuit, each is with a duty cycle adjustment end, and different duty cycle control signals enters the clock generator body from different duty ratio adjusting circuits; The output of duty ratio adjusting circuit forms the output of clock generator body.In order to obtain the tuning capability of broadband, above-mentioned oscillating circuit mainly consists of input control circuit and the end to end delay unit of N level, wherein every 1 grade of delay unit comprises transmission gate circuit and the vibration inverter of mutual formation series connection, and above-mentioned N is equal to or greater than 3 odd number; The input voltage signal of outside input is divided into 2 tunnels immediately after entering the clock generator body, wherein 1 control end of every 1 grade of delay unit transmission gate is directly accessed on 1 tunnel, and another 1 control end of every 1 grade of delay unit transmission gate is accessed on another road after input control circuit; The output of the vibration inverter of afterbody delay unit is divided into 2 tunnels, 1 tunnel as feedback end be connected to first order delay unit input, another 1 tunnel forms the output of oscillating circuit.
In such scheme, every 1 road duty ratio adjusting circuit mutually forms input inverter in parallel and controls inverter by 2 and forms; Wherein the input of input inverter forms the input of duty ratio adjusting circuit, the input of controlling inverter forms the duty cycle adjustment end of duty ratio adjusting circuit, the output of input inverter and this duty ratio adjusting circuit of formation after the output of controlling inverter is connected.
In order to improve the waveform of output signal, above-mentioned every 1 road duty ratio adjusting circuit also includes 2 the middle inverter and the output inverters that mutually form series connection; Wherein, the input of inverter is connected to input inverter and controls on the output of inverter, and the output of exporting inverter this moment forms the output of this duty ratio adjusting circuit.
In order to obtain complementary signal, on the output of above-mentioned middle inverter, also draw a road complementary signal output.
Constant for the grid voltage sum that guarantees transmission gate, input control circuit described above is for to consist of 2 identical field effect transistor; Wherein the source electrode of the first field effect transistor is connected with the positive pole of power supply, and the drain and gate of the second field effect transistor is connected with the negative pole of power supply; The drain electrode of the first field effect transistor is connected with the source electrode of the second field effect transistor, and the grid of the first field effect transistor forms the input of input control circuit.
Compared with prior art, the present invention has following features:
1) by at the rear of oscillating circuit parallel connection at least 2 road duty ratio adjusting circuits, producing non-overlapped clock signal, allow the present invention can collect the oscillator signal generation and betide one with non-overlapping clock, thereby broken traditional non-overlapping clock circuit structure, made this circuit become a clock generator truly;
2) due to the duty cycle control signal of duty ratio adjusting circuit, can draw the outside of clock generator, this not only can carry out flexible to the time interval of the clock signal of clock generator output, and it is non-overlapped etc. many to non-overlapping clock under the prerequisite of simplifying circuit, to produce complementary, that the high level zone is non-overlapped and/or low level zone;
3) oscillating circuit adopts the voltage controlled oscillator based on transmission gate, because transmission gate can have wide Standard resistance range as adjustable equivalent resistance, be that oscillating circuit can obtain wide frequency ranges, therefore the present invention can have the broadband tuning range of a plurality of orders of magnitude, can be widely used in low frequency field (as processing of biomedical signals) and high frequency field (as wireless sensor network node, surveying and process a certain signal).
The accompanying drawing explanation
Fig. 1 is a kind of theory diagram of adjustable non-overlapping clock signal generator;
Fig. 2 is the circuit diagram of oscillating circuit;
Fig. 3 is the circuit diagram of duty ratio adjusting circuit;
Fig. 4 is the equivalent resistance model of Fig. 3;
Fig. 5 is a kind of simulation result of adjustable non-overlapping clock signal generator;
Fig. 6 is the details enlarged drawing of Fig. 5.
Embodiment
Referring to Fig. 1, a kind of adjustable non-overlapping clock signal generating method of the present invention, comprise that square-wave signal produces step and square-wave signal duty cycle adjustment step, the square-wave signal that its oscillating circuit produces is input to respectively at least 2 road duty ratio adjusting circuits, every 1 road duty ratio adjusting circuit is realized the duty cycle adjustment of square-wave signal under the effect of different duty control signal, obtain thus the output signal that at least 2 tunnels have different duty, these output signals with different duty are the non-overlapping clock signal.
Above-mentioned every 1 road duty ratio adjusting circuit mutually forms input inverter in parallel and controls inverter by 2 and forms; Under the adjusting of the duty cycle control signal from controlling the inverter input, the overturn point that changes input inverter realizes inputting the duty cycle adjustment of square-wave signal from the square-wave signal of input inverter input input.For the waveform that makes final signal better, every 1 road duty ratio adjusting circuit also contains 2 the middle inverter and the output inverters that mutually form series connection, middle inverter and output inverter are serially connected on the overturn point of above-mentioned input inverter, to improve the waveform of duty ratio adjusting circuit output signal.
Above-mentioned oscillating circuit mainly consists of input control circuit and the end to end delay unit of N level, and wherein every 1 grade of delay unit comprises transmission gate and the vibration inverter of mutual formation series connection, and above-mentioned N is equal to or greater than 3 odd number; The input voltage signal of outside input forms the complementary voltage signal after input control circuit is adjusted, the voltage swing of this complementary voltage signal is voltage poor of the voltage of power supply and input voltage signal; Above-mentioned input voltage signal and complementary voltage signal send into respectively the transmission gate of every 1 grade of delay unit 2 control ends, allow all transmission gates change between conducting and cut-off state, and the square-wave signal that impels delay unit to produce to have the broadband tunable range.
This circuit design is to be based upon on adjustable passgate structures voltage controlled oscillator (TG-VCO) basis of duty ratio.Input signal forms two paths of signals by input control circuit, and simultaneously the transmission gate in delay unit is carried out to regulating and controlling.This regulates is mainly for the output signal that makes oscillating circuit, to obtain the tuning range of broadband.After the delay unit that is formed by transmission gate and inverter through the N level, oscillating circuit output square-wave signal.Consider this output signal is carried out to voltage control, can change its duty ratio.Along this thinking, in order to obtain the not overlapping clock signal of two-phase, we propose parallel voltage-controlled design, with two, control voltage and to the output signal of TG-VCO, carry out respectively the adjusting of different duty by duty ratio adjusting circuit, thereby make VCO directly export the not overlapping clock of two-phase, realized that the generation of the generation of oscillator signal and two-phase non-overlapping clock signal is integrated.
A kind of adjustable non-overlapping clock signal generator designed according to said method, as shown in Figure 1, it mainly is comprised of oscillating circuit and 2 road duty ratio adjusting circuits at least; Wherein the duty ratio adjusting circuit more than 2 roads or 2 tunnels is parallel with one another, and the input of every 1 road duty ratio adjusting circuit all is connected with the output of oscillating circuit; On every 1 road duty ratio adjusting circuit, each is with a duty cycle adjustment end, and different duty cycle control signals enters the clock generator body from different duty ratio adjusting circuits; The output of duty ratio adjusting circuit forms the output of clock generator body.
In order to obtain the broadband tuning capability, in the present invention, described oscillating circuit adopts the voltage controlled oscillator (TG-VCO) based on passgate structures.Be that described oscillating circuit mainly consists of input control circuit and the end to end delay unit of N level, wherein every 1 grade of delay unit comprises transmission gate circuit and the vibration inverter of mutual formation series connection.Above-mentioned N is equal to or greater than 3 odd number, as N=3,7,9,11 ..., in the present embodiment, adopt 3 grades of delay units.The input voltage signal of outside input is divided into 2 tunnels immediately after entering the clock generator body, wherein 1 control end of every 1 grade of delay unit transmission gate is directly accessed on 1 tunnel, and another 1 control end of every 1 grade of delay unit transmission gate is accessed on another road after input control circuit; The output of the vibration inverter of afterbody delay unit is divided into 2 tunnels, 1 tunnel as feedback end be connected to first order delay unit input, another 1 tunnel forms the output of oscillating circuit.Because transmission gate consists of a N channel field-effect pipe and the parallel connection of a P-channel field-effect transistor (PEFT) pipe, and be Vdd be used to the voltage sum of the grid of controlling N channel field-effect tube grid and P-channel field-effect transistor (PEFT) pipe.Therefore constant in order to guarantee this grid voltage sum Vdd, in the present invention, available 2 identical field effect transistor form input control circuit.Wherein the source electrode of the first field effect transistor is connected with the positive pole of power supply, and the drain and gate of the second field effect transistor is connected with the negative pole of power supply; The drain electrode of the first field effect transistor is connected with the source electrode of the second field effect transistor, and the grid of the first field effect transistor forms the input of input control circuit.Referring to Fig. 2.
By the input voltage control signal of regulating transmission gate circuit, change transistorized working region, transmission gate is changed between conducting state and cut-off state, transmission gate equivalent resistance, the delay unit that is comprised of inverter and transmission gate change simultaneously, and then allow the frequency of oscillating circuit output signal be able to by voltage control, and the relation between frequency and transmission gate equivalent resistance is shown below:
In following formula, N is delay cell progression, and τ is the time delay of each unit, and Gm is the mutual conductance of inverter, and Rtg is the transmission gate equivalent resistance, and Cg is parasitic capacitance.Because Gm and Cg are device parameters, usually be considered to constant, so frequency of oscillation is affected by Rtg mainly.
Consider the output signal of oscillating circuit is carried out to voltage control, can change its duty ratio.Along this thinking, in order to obtain the not overlapping clock of two-phase, the present invention proposes parallel voltage-controlled design, with two, control voltage and to the output signal of TG-VCO, carry out respectively the adjusting of different duty, thereby make VCO directly export the not overlapping clock of two-phase.Change the duty ratio of oscillating circuit output signal, actually need to change the shared ratio of high level and low level in the signal period.When the PMOS pipe that forms inverter and NMOS pipe were all saturated, its voltage-transfer characteristic curve was approximately vertical line segment, and the perfect Gain in this zone is infinity.Overturn point, also claim turn threshold, is defined as the point that makes inverter input, output voltage equate.When two transistors of inverter all are in zone of saturation, can realize by the overturn point that changes inverter the conversion of high and low level, thereby change the duty ratio of output signal.For the duty ratio adjusting circuit of controlling the TG-VCO output signal as shown in Figure 3, namely every 1 road duty ratio adjusting circuit mutually forms input inverters in parallel and controls inverters by 2 and forms.Wherein input inverter consists of transistor M15 and transistor M16, and the input of this input inverter forms the input of duty ratio adjusting circuit, and the square-wave signal Vin of TG-VCO output inputs thus; Control inverter and consist of transistor M17 and transistor M18, this input of controlling inverter forms the duty cycle adjustment end of duty ratio adjusting circuit, and duty cycle control signal Vduty inputs thus; Input inverter is connected and forms afterwards the overturn point of this duty ratio adjusting circuit with the output of controlling inverter; Better for the waveform that makes final signal, after the overturn point of above-mentioned duty ratio adjusting circuit, also be serially connected with 2 inverters.Be that every 1 road duty ratio adjusting circuit also includes 2 middle inverter and output inverters that mutually form series connection; Wherein, inverter consists of transistor M19 and transistor M20, the input of this centre inverter is connected to input inverter and controls on the output of inverter, the output of middle inverter is the complementary signal output, and complementary output signal Vout ' exports thus; The output inverter consists of transistor M21 and transistor M22, and the input of this output inverter is connected with the output of middle inverter, and the output of output inverter forms the output of this duty ratio adjusting circuit, and output signal Vout exports thus.
Suppose that all pipe works are in saturation region, as shown in Figure 4, node voltage Vb can calculate by following formula the equivalent resistance model of input inverter and control inverter:
R is the conducting resistance (on-resistance) of field effect transistor, and wherein R17 and R18 can regard variable resistor as.Adjusting Vduty controls the resistance of R17 and R18, and the value of Vb also changes thereupon.Therefore, the overturn point of the input inverter that M15 and M16 form can be controlled by Vduty, can regulate the duty ratio of oscillating circuit output signal thus.
In the present embodiment, the input Vin of two duty ratio adjusting circuit Fig. 3 is parallel to the output of oscillating circuit Fig. 2, can realizes the non-overlapping clock generator shown in Fig. 1 theory diagram.Vduty1, Vduty2 are respectively the control voltage of two duty ratio adjusting circuits.By arranging these two, control voltage, draw the output signal of different duty, produce thus non-overlapping clock pair.Because middle inverter and output inverter can be exported anti-phase each other signal, therefore can after middle inverter, set up a complementary signal output, so the signal nclk1 of this complementary signal output output just with the former clock signal that is located at the signal clk1 a pair of anti-phase complementation each other of the signal output part output after the output inverter.According to this scheme, if each road duty cycle circuit can both be exported the clock signal of a pair of anti-phase complementation, so just can draw different non-overlapping clock signals.Take the duty cycle circuit of 2 Fig. 4 in parallel as example, so altogether can export 4 signals is clk1, nclk1, clk2, nclk2, and the waveform of these 4 signals as shown in Figure 5 and Figure 6.Wherein have:
2 groups of complementary non-overlapping clock signals: clk1 and nclk1, clk2 and nclk2.Their characteristics are clk when being high, and nclk is low, and high and low level part is never overlapping.
1 group of high level part non-overlapping clock signal: clk1 and clk2.Their low level partly can be overlapping.
1 group of low level part non-overlapping clock signal: nclk1 and nclk2.Their high level partly can be overlapping.
Visible, how many how many road duty ratio adjusting circuits in parallel, just can export to complementary non-overlapping clock signal, i.e. clk and nclk.
When the output of oscillating circuit only is connected to a road duty ratio adjusting circuit, only export one group of complementary non-overlapping clock signal.
When the output of oscillating circuit 2 road duty ratio adjusting circuit in parallel, exportable 2 groups of complementary signals, 1 group of high level are overlapped signal not, and 1 group of low level is overlapped signal not.
When the output of oscillating circuit 3 road duty ratio adjusting circuit in parallel, exportable 3 groups of complementary signals, 3 groups of high level parts are overlapped signal not, and 3 groups of low level parts are overlapped signal not.For example, by regulating the different signal dutyfactor of 3 road duty ratio adjusting circuits, export 6 signals: the clk1(high level partly accounts for 44%), nclk1(56%), clk2(80%), nclk2(20%), clk3(60%), nclk3(40%).Wherein have:
3 groups of complementary non-overlapped signal pair: clk1 and nclk1, clk2 and nclk2, clk3 and nclk3.
3 groups of high level part is overlapped signal pair: clk1 and nclk2 not, clk1 and nclk3, clk3 and nclk2.
3 groups of low levels part is overlapped signal pair: clk2 and nclk1 not, clk2 and nclk3, clk3 and nclk1.
Therefore, the present invention can obtain many to the non-overlapping clock signal by the parallel multiplex duty ratio adjusting circuit, include complementary non-overlapped signal to, high level part not overlapped signal to low level part overlapped signal pair not.
Claims (8)
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103078611B (en) * | 2012-12-28 | 2016-01-20 | 芯锋宽泰科技（北京）有限公司 | Clock generator and comprise its switched-capacitor circuit |
| JP2015080070A (en) * | 2013-10-16 | 2015-04-23 | セイコーエプソン株式会社 | Oscillation circuit, oscillator, electronic apparatus and movable body |
| CN104639125B (en) * | 2013-11-14 | 2018-04-27 | 展讯通信（上海）有限公司 | Clock signal generating apparatus and electronic equipment |
| KR20170009551A (en) * | 2015-07-17 | 2017-01-25 | 에스케이하이닉스 주식회사 | Sginal generator adjusting duty cycle and semiconductor apparatus using the same |
| CN107124161B (en) * | 2017-03-17 | 2020-04-24 | 东南大学 | Method for realizing M/N duty ratio clock signal based on single-molecule and two-molecule chemical reaction network |
| CN112448700B (en) * | 2021-02-01 | 2021-11-02 | 南京邮电大学 | A 50% Duty Cycle Shaping Circuit for Low Voltage |
| CN117498840B (en) * | 2023-12-29 | 2024-04-16 | 中茵微电子(南京)有限公司 | Parallel coarse-fine adjustment device in single-ended analog duty cycle regulator |
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| US4645947A (en) * | 1985-12-17 | 1987-02-24 | Intel Corporation | Clock driver circuit |
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