CN102427060B - Formation method of dual damascene structure - Google Patents
Formation method of dual damascene structure Download PDFInfo
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- CN102427060B CN102427060B CN201110386916.1A CN201110386916A CN102427060B CN 102427060 B CN102427060 B CN 102427060B CN 201110386916 A CN201110386916 A CN 201110386916A CN 102427060 B CN102427060 B CN 102427060B
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Abstract
The invention provides a formation method of a dual damascene structure. The method comprises the following steps:1) providing a semiconductor substrate whose surface possesses a conducting structure and forming an interlayer dielectric layer on the substrate; 2) successively forming a silicon nitride layer, an amorphous silicon layer, a bottom anti-reflective layer, a first photoresist layer, a low temperature barrier layer and a second photoresist layer on the interlayer dielectric layer; 3) carrying out groove imaging to the second photoresist layer; 4) etching the low temperature barrier layer under the groove by using a wet method; 5) carrying out through hole imaging to the first photoresist layer; 6) taking the amorphous silicon layer and the silicon nitride layer as a hard mask imaging interlayer dielectric layer and forming the groove and the through hole; 7) filling a barrier layer material and a conductive material in the groove and the through hole; 8) performing planarization processing to the barrier layer material and the conductive material so as to form the dual damascene structure. In the invention, the through hole or the groove does not need to be filled. Technology difficulty is reduced. A photoresist surface is smooth and the technology is stable. The method is practical.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly the formation method of a kind of dual-damascene structure (dual damascene structure).
Background technology
Along with the fast development of semiconductor technology, the future development to miniaturization that the size of IC device design also continues.Based on market competition and industry demand, the performance/cost performance improving constantly product is the power of microelectric technique development.
Current semiconductor device CMOS has deep submicron structures, comprises the semiconductor element of enormous quantity in semiconductor integrated circuit IC.In this large scale integrated circuit, the high-performance between element, highdensity connection not only interconnect in single interconnection layer, and will interconnect between multilayer.Therefore, usually provide multilayer interconnect structure, wherein multiple interconnection layer is stacking mutually, and interlayer dielectric is placed in therebetween, for connecting semiconductor element.When particularly utilizing dual damascene (dual-damascene) technique to form multilayer interconnect structure, in interlayer dielectric, form interconnection groove and connecting hole in advance, then fill described interconnection groove and connecting hole with electric conducting material such as copper (Cu).
The main devices of integrated circuit especially in very lagre scale integrated circuit (VLSIC) is metal-oxide semiconductor fieldeffect transistor (metal oxide semiconductor field effect transistor is called for short MOS transistor).Since metal-oxide-semiconductor is invented, its physical dimension is constantly reducing always, and the number of transistors in chip constantly increases, and while the metal connecting line of chip is more and more thinner, level also gets more and more.Therefore increasing company have employed copper wiring and instead of original aluminum manufacturing procedure, and compared with aluminium, the resistance coefficient of copper is less, and fusing point is high, and deelectric transferred ability is strong, is therefore widely adopted.But because copper is difficult to be etched, the lithographic technique traditionally for the formation of aluminum metal wiring is inapplicable for copper.Therefore single mosaic technology and the dual-damascene technics of copper is developed.Because the efficiency of dual-damascene technics is higher, be therefore widely used.
Dual-damascene technics is the method that one can form the stacked on top structure of plain conductor and connector (plug) simultaneously, to be used for connecting different elements and the wire of each interlayer in semiconductor wafer, and utilize the core dielectric material around it (inter-layer dielectrics ILD) and other element isolated.The major technique of dual-damascene technics focuses on the lithographic technique etching the groove of filling conductor metal, in the front end etching technics of dual-damascene technics, current existence two kinds of methods make the groove of dual damascene trench, first method first defines conductor trench on the top of dielectric layer, another photoresist layer is utilized to define interlayer hole opening afterwards, the method due to the density of conductor trench quite high, making the surface irregularity of the photoresist layer for defining interlayer hole opening, having had a strong impact on the resolution of exposure imaging technique.Another kind method defines the interlayer hole opening penetrating dielectric layer completely first in the dielectric layer, then utilizes another photoresist layer to define conductor trench, before coating photoresist layer, first can be coated with one deck reflector, to improve the resolution of exposure imaging technique.
Chinese patent CN201010144234 provides a kind of Double-embedded structure forming method, comprises step: provide semiconductor structure and impression shielding, semiconductor structure comprises interconnection layer, the dielectric layer be positioned on interconnection layer, is positioned at the sacrifice layer on dielectric layer; Sacrifice layer on described semiconductor structure is heated, described sacrifice layer is softened; Utilize described impression to shield and punching press is carried out to the sacrifice layer on described semiconductor structure, make the projection on described semiconductor structure embed in described sacrifice layer; Sacrifice layer on semiconductor structure is cooled, described sacrifice layer is hardened; Described impression shielding is taken out, thus form dual-damascene structure on the sacrifice layer of described semiconductor structure; The semiconductor structure with dual-damascene structure is etched, makes to form dual-damascene structure in the dielectric layer, and the via bottoms in described dual-damascene structure exposes interconnection layer.Thus decrease the damage that substrate is caused, improve device reliability.
Chinese patent CN03121250 provides a kind of method making dual-damascene structure (dual damascene structure).First sequentially form one first dielectric layer, one second dielectric layer, one first curtain layer of hard hood and one second curtain layer of hard hood in semiconductor wafer surface, then form first photoresist layer being used for definition one upper strata channel patterns in this second curtain layer of hard hood surface.Remove subsequently not by this second curtain layer of hard hood that this first photoresist layer covers, until this first curtain layer of hard hood surface, and then form second photoresist layer being used for definition one lower floor contact hole pattern in this semiconductor wafer surface.Then this first curtain layer of hard hood and this second dielectric layer of not covered by this second photoresist layer is removed, until this first dielectric layer surface, then etch not this first curtain layer of hard hood of covering by this second curtain layer of hard hood, and remove not this second dielectric layer to desired depth of covering by this first curtain layer of hard hood, finally remove again this second curtain layer of hard hood and not this first dielectric layer of covering by this first curtain layer of hard hood.
Chinese patent CN200710040380 relates to a kind of manufacture method of dual-damascene structure, comprising: form cover layer, interlevel dielectrics layer and barrier layer on a semiconductor substrate successively; Etching interlevel dielectrics layer and barrier layer form connecting hole; The first bottom anti-reflection layer is formed in connecting hole and on barrier layer; Until the first bottom anti-reflection layer on barrier layer is completely removed; The second bottom anti-reflection layer is formed in connecting hole and on barrier layer; Etch the second bottom anti-reflection layer, form the 3rd bottom anti-reflection layer, described 3rd bottom anti-reflection layer is positioned at connecting hole; Etching barrier layer and interlevel dielectrics layer form groove, and the position of groove is corresponding with the position of connecting hole and be communicated with connecting hole; Remove barrier layer and the 3rd bottom anti-reflection layer, and the cover layer removed in connecting hole is until exposing semiconductor substrate, forms dual-damascene structure.Described method can avoid peeling off phenomenon between cover layer and interlevel dielectrics layer after formation metal wiring structure.
Chinese patent CN200610025649 provides a kind of formation method of dual-damascene structure, comprising: provide a surface to have the Semiconductor substrate of conductive structure, substrate forms inner layer dielectric layer; Described inner layer dielectric layer is formed first photoresist layer with contact hole graph; Described first photoresist layer is formed second photoresist layer with groove opening figure; Etch the described figure of described first photoresist layer and the second photoresist layer, till exposing described conductive structure; Fill metal material and form dual-damascene structure.The formation method of dual-damascene structure of the present invention eliminates the step forming anti-reflecting layer, by two to three etch cleaner process modification in prior art for just to form dual-damascene structure merely through an etch cleaner.The formation method of dual-damascene structure of the present invention can form good dual-damascene structure, and simplifies manufacturing process, reduces production cost.
Described dual-damascene technics, the difference realizing sequential manner according to technique can be divided into two classes: first trench process (Trench First) and first via process (Via First).First trench process comprises: first on the interlayer dielectric layer deposited, etch groove figure, and then etch through hole.Because the photoetching forming through hole carries out after trench formation, now substrate exists groove, substrate surface is rough and uneven in surface, makes the skewness of photoresist.First via process comprises: in interlayer dielectric layer, first etch the through hole through interlayer dielectric layer, then utilize another layer photoetching glue define and form groove.Because the photoetching owing to forming groove carries out after the via is formed, now there is through hole in substrate, will must carry out the photoetching of groove after filling through hole again.Need in original technique to fill through hole or groove, be difficult to carry out perfection and fill, photoresist surface is difficult to smooth.
Summary of the invention
In view of the above problems, the object of the present invention is to provide a kind of formation method of dual-damascene structure, be very suitable for practicality.
The object of the invention to solve the technical problems realizes by the following technical solutions.
The invention provides a kind of formation method of dual-damascene structure, it has following steps:
1) provide a surface to have the Semiconductor substrate of conductive structure, substrate forms interlayer dielectric layer;
2) on described interlayer dielectric layer, silicon nitride layer, amorphous silicon layer, bottom anti-reflection layer, the first photoresist layer, low temperature barrier layer and the second photoresist layer is formed successively;
3) the graphical of groove is carried out to the second described photoresist layer;
4) the low temperature barrier layer under wet etching groove;
5) the graphical of through hole is carried out to the first described photoresist layer;
6) be hard mask pattern interlayer dielectric layer with described amorphous silicon layer and silicon nitride layer, form groove and through hole;
7) in described groove and through hole, barrier material and electric conducting material is filled;
8) planarization is carried out to described barrier material and electric conducting material, form dual-damascene structure.
The object of the invention to solve the technical problems also can be applied to the following technical measures to achieve further:
The first described photoresist layer is negative photoresist or positive photoresist.
The second described photoresist layer is negative photoresist or positive photoresist.
Described low temperature barrier layer is low thermal oxidation silicon, and thickness is 1000 ~ 8000 dusts.
Described low temperature barrier layer forms required maximum temperature not higher than the temperature of curing in photoetching.
Described silicon nitride layer material is silicon nitride or carborundum.
The barrier material of filling in described groove and through hole and electric conducting material are copper (Cu).
Above-mentioned explanation is only the general introduction of technical solution of the present invention, in order to technological means of the present invention can be better understood, and can be implemented according to the content of specification, and can become apparent to allow above and other object of the present invention, feature and advantage, below especially exemplified by preferred embodiment, and coordinate accompanying drawing, be described in detail as follows.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe embodiments of the invention more fully.But, appended accompanying drawing only for illustration of and elaboration, do not form limitation of the scope of the invention.
Fig. 1 illustrates the flow chart of a kind of Double-embedded structure forming method that the present invention relates to.
Fig. 2 to Fig. 8 illustrates the generalized section of Double-embedded structure forming method in the embodiment of the present invention.
In Reference numeral, 1 is silicon substrate, and 2 is interlayer dielectric layer, and 3 is silicon nitride layer, and 4 is amorphous silicon layer, and 5 is bottom anti-reflection layer, and 6 is the first photoresist layer, and 7 is low temperature barrier layer, and 8 is the second photoresist layer, and 9 is metallic copper.
Embodiment
For further setting forth the present invention for the technological means reaching predetermined goal of the invention and take and effect, below in conjunction with accompanying drawing and preferred embodiment, to a kind of method making polysilicon side wall proposed according to the present invention, be described in detail as follows.
Different embodiments of the invention will details are as follows, to implement different technical characteristic of the present invention, will be understood that, the unit of the specific embodiment of the following stated and configuration are in order to simplify the present invention, and it is only example and does not limit the scope of the invention.
Fig. 2 to Fig. 8 illustrates the generalized section of Double-embedded structure forming method in the embodiment of the present invention.As shown in Figure 2, provide a surface to have the Semiconductor substrate of conductive structure, substrate forms interlayer dielectric layer; Described interlayer dielectric layer is formed silicon nitride layer, amorphous silicon layer, bottom anti-reflection layer, the first photoresist layer, low temperature barrier layer and the second photoresist layer successively.Described low temperature barrier layer, its thickness is enough thick, and the maximum temperature needed for formation is not higher than the temperature of curing in photoetching, and exposure time first time cannot penetrate this barrier layer, and it can be low thermal oxidation silicon; Optional amorphous silicon layer is APF(advanced pattern film), optional silicon nitride layer is also carborundum etc.As shown in Figure 3, the graphical of groove is carried out to the second photoresist layer.As shown in Figure 4, the low temperature barrier layer under wet etching groove is adopted.As shown in Figure 5, the graphical of through hole is carried out to the first described photoresist layer.As shown in Fig. 6 (a) He Fig. 6 (b), be hard mask pattern interlayer dielectric layer with described amorphous silicon layer and silicon nitride layer, form groove and through hole, the position of groove is corresponding with the position of through hole, and is connected with through hole.The technique forming groove is prior art.As shown in Figure 7, in described groove and through hole, metallic copper is filled as barrier material and electric conducting material.As shown in Figure 8, planarization is carried out to described barrier material and electric conducting material, form dual-damascene structure.
By illustrating and accompanying drawing, give the exemplary embodiments of the ad hoc structure of embodiment.Although foregoing invention proposes existing preferred embodiment, but these contents are not as limitation.For a person skilled in the art, after reading above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should regard the whole change and correction of containing true intention of the present invention and scope as.In Claims scope, the scope of any and all equivalences and content, all should think and still belong to the intent and scope of the invention.
Claims (8)
1. a formation method for dual-damascene structure, is characterized in that: it has following steps:
1) provide a surface to have the Semiconductor substrate of conductive structure, substrate forms interlayer dielectric layer;
2) on described interlayer dielectric layer, silicon nitride layer, amorphous silicon layer, bottom anti-reflection layer, the first photoresist layer, low temperature barrier layer and the second photoresist layer is formed successively;
3) the graphical of groove is carried out to the second described photoresist layer;
4) the low temperature barrier layer under wet etching groove;
5) the graphical of through hole is carried out to the first described photoresist layer;
6) be hard mask pattern interlayer dielectric layer with described amorphous silicon layer and silicon nitride layer, form groove and through hole;
7) in described groove and through hole, barrier material and electric conducting material is filled;
8) planarization is carried out to described barrier material and electric conducting material, form dual-damascene structure;
Described amorphous silicon layer is APF layer, and plain conductor and connector stacked on top form described dual-damascene structure.
2. the formation method of a kind of dual-damascene structure as claimed in claim 1, is characterized in that: the first described photoresist layer is negative photoresist or positive photoresist.
3. the formation method of a kind of dual-damascene structure as claimed in claim 1, is characterized in that: the second described photoresist layer is negative photoresist or positive photoresist.
4. the formation method of a kind of dual-damascene structure as claimed in claim 1, is characterized in that: described low temperature barrier layer is low thermal oxidation silicon.
5. the formation method of a kind of dual-damascene structure as claimed in claim 1, is characterized in that: described low temperature barrier layer thickness is 1000 ~ 8000 dusts.
6. the formation method of a kind of dual-damascene structure as claimed in claim 1, is characterized in that: described low temperature barrier layer forms required maximum temperature not higher than the temperature of curing in photoetching.
7. the formation method of a kind of dual-damascene structure as claimed in claim 1, is characterized in that: described silicon nitride layer material is silicon nitride or carborundum.
8. the formation method of a kind of dual-damascene structure as claimed in claim 1, is characterized in that: the barrier material of filling in described groove and through hole and electric conducting material are copper (Cu).
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| CN201110386916.1A CN102427060B (en) | 2011-11-29 | 2011-11-29 | Formation method of dual damascene structure |
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| CN102751238A (en) * | 2012-07-27 | 2012-10-24 | 上海华力微电子有限公司 | Through hole preferential copper interconnection production method |
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| US6242344B1 (en) * | 2000-02-07 | 2001-06-05 | Institute Of Microelectronics | Tri-layer resist method for dual damascene process |
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| US6242344B1 (en) * | 2000-02-07 | 2001-06-05 | Institute Of Microelectronics | Tri-layer resist method for dual damascene process |
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