CN102420192B - Manufacturing method of twin-transistor and zero-capacitance dynamic RAM (Random Access Memory) - Google Patents
Manufacturing method of twin-transistor and zero-capacitance dynamic RAM (Random Access Memory) Download PDFInfo
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Abstract
The invention discloses a manufacturing method of a twin-transistor and zero-capacitance dynamic RAM (Random Access Memory), aiming at providing the manufacturing method of the twin-transistor and zero-capacitance dynamic RAM which is manufactured by adopting a silicon of insulator-based gate-last process and has a design for manufacturability. In the process, the characteristics different from the characteristics of greater Overlap between a T1 source/drain electrode and a gate and greater distance Underlap between a T2 source/drain electrode and the gate in a conventional CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process are effectively achieved by self aligning; the manufacturing method is suitable for manufacturing of an integrated circuit in the gate-last process of a high-dielectric-constant oxidation layer metal gate of below 45nm; and by adjusting work functions of the gates of the T1 and the T2, which are close to the source electrode and the drain electrode, or doping types of channel regions at the lower parts of the gates, which are close to the source electrode and the drain electrode through ion implantation, the channel regions in the channel regions of the T1, which are close to the source electrode and the drain electrode, are inverted to be the same types with the source region and the drain region under the condition of no increase of the pressure of the gates and diffusion regions below the gates of the source electrode and the drain electrode of the T2 are inverted into the opposite types of the source region and the drain region under the condition of no increase of the pressure of the gates.
Description
Technical field
The present invention relates generally to technical field of manufacturing semiconductors, or rather, the present invention relates to a kind of preparation method of pair transistor zero capacitance dynamic ram of the rear grid technology based on silicon-on-insulator with manufacturability design.
Background technology
Along with semiconductor integrated circuit enters the more high-order technique epoch, tradition one transistor one capacitor (One Transistor One Capacity, being abbreviated as 1T1C) DRAM of structure makes by electric capacity and transistor, electric capacity is used for storing data and transistor leads to the switch block of system as data, this has aggravated the complexity of manufacturing process undoubtedly, and especially to prepare difficulty be increasing to the capacitor of high density of integration, low electric leakage.Therefore, at present to substituting pair transistor (the Two Transistors of 1T1C structure DRAM, be abbreviated as 2T) even single-transistor structure zero capacitance dynamic ram or without electric capacity dynamic ram (Zero-Capacitor RAM or Capacitorless RAM, being abbreviated as Z-RAM) research is more and more popular, Z-RAM can double the storage density of DRAM, the buffer memory capacity of processor is improved to five times, and without requiring to use special material or more advanced manufacturing process, have a good application prospect.US Patent No. 2010/0329043 A1 discloses a kind of buoyancy aid/grid unit (FBGC:Floating Body/Gate Cell, be abbreviated as FBGC) pair transistor dynamic ram structure, figure mono-is its cellular construction (take NMOS as example), it is based on silicon-on-insulator (Silicon On Insulator, be abbreviated as SOI) dual-MOS structure (can be part depletion <Partial Depletion, PD> or all exhaust <Full Depletion, FD>), in figure, the source of T1 is leaked and is connected together BL1(Bit Line 1, bit line 1), it utilizes the T1 grid that leak in grid and source when OFF state to induce drain leakage (Gate-Induced Drain Leakage, be abbreviated as GIDL) effect discharges to realize to buoyancy aid when its buoyancy aid (Floating Body) is filled to positive charge and T1 ON state " 0 ", " 1 " and storage and conversion, figure bis-is for utilizing the change in voltage characteristic of each node under the various states of this 2T DRAM of UFDG/Spice3 model emulation, and BL2 voltage or electric current are for reading result.In order fast T1 to be discharged and recharged, realize and write the high-speed of process, requiring T1 source to leak with grid has larger overlapping (Overlap), to increase GIDL effect as far as possible.In order to make T1 buoyancy aid electric charge fast driving T2, require to reduce T2 parasitic capacitance as far as possible, require source leakage and the grid of T2 to have larger distance (Underlap) to reduce the parasitic capacitance between T2 grid and source leakage for this reason, this FBGC 2T DRAM structure has certain uniqueness, but it does not solve manufacturability (DFM, Design for Manufacturability) how problem, be different from the T1 source leakage of stand CMOS by the effective realization of autoregistration in technique and grid has larger overlapping and T2 source to leak and grid has larger range performance.
Summary of the invention
Problem for above-mentioned existence, the preparation method who the object of this invention is to provide the pair transistor zero capacitance dynamic ram that a kind of rear grid technology based on silicon-on-insulator with manufacturability design manufactures, in technique, by autoregistration, effectively realizing the T1 source that is different from stand CMOS leaks and has larger overlapping (Overlap) and T2 source to leak with grid and grid has larger distance (Underlap) characteristic, be applicable to, in the integrated circuit preparation of grid technology after the high dielectric constant oxide layer metal gates below 45nm, be achieved through the following technical solutions:
A preparation method for pair transistor zero capacitance dynamic ram, pair transistor is wherein two cascade MOS transistor T1 and the T2 being formed on common substrate, wherein, comprises front standby operation, described front standby operation comprises:
T1 and T2 separately the channel surface between source-drain electrode be formed with respectively thin oxide layer;
Above thin oxide layer, by wet the eat-backing of appended sample grid, be formed with respectively T1 and T2 gate trench separately, and in T1 and T2 gate trench separately, be formed with respectively high dielectric layer and the metal oxide dielectric materials layer above it.
By T1, the T2 opening of gate trench separately, by Implantation, change respectively metal oxide dielectric materials layer that T1, T2 comprise near the work function at the two ends of source electrode and drain electrode, so that the region near source electrode and drain electrode is the doping type identical with source-drain area not adding transoid in grid voltage situation in T1 channel region, the region near source electrode and drain electrode in T2 channel region is the doping type contrary with source-drain area not adding transoid in grid voltage situation.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, when two cascade MOS transistor T1 and T2 are all NMOS structure, described front standby operation comprises:
T1 and T2 separately the channel surface between source-drain electrode be formed with respectively thin oxide layer;
Above thin oxide layer, by wet the eat-backing of appended sample grid, be formed with respectively T1 and T2 gate trench separately, and in T1 and T2 gate trench separately, be formed with respectively high dielectric layer and the metal oxide dielectric materials layer above it;
Carry out photoetching, T1 regional window is opened, T2 regional window is closed, carry out angle inclination, carry out two-way Implantation so that grid reduce work function near source and leak after rotating 180 degree, causing the channel region near source and leakage under grid is N-type not adding transoid in grid voltage situation, the ion that injection ion is little work function;
Carry out photoetching, T2 regional window is opened, T1 regional window is closed, carry out angle inclination, rotate after 180 degree and carry out two-way Implantation so that grid increase work function near source and leak, causing diffusion zone under the grid of source and leakage is P type not adding transoid in grid voltage situation, injects the ion that ion is mainly large work function.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, when two cascade MOS transistor T1 and T2 are all PMOS structure, described front standby operation comprises:
T1 and T2 separately the channel surface between source-drain electrode be formed with respectively thin oxide layer;
Above thin oxide layer, by wet the eat-backing of appended sample grid, be formed with respectively T1 and T2 gate trench separately, and in T1 and T2 gate trench separately, be formed with respectively high dielectric layer and the metal oxide dielectric materials layer above it;
Carry out photoetching, T1 regional window is opened, T2 regional window is closed, carry out angle inclination, rotate after 180 degree and carry out two-way Implantation so that grid increase work function near source and leak, causing the channel region near source and leakage under grid is P type not adding transoid in grid voltage situation, injects the ion that ion is mainly large work function;
Carry out photoetching, T2 regional window is opened, T1 regional window is closed, carry out angle inclination, carry out two-way Implantation so that grid reduce work function near source and leak after rotating 180 degree, causing the channel region near source and leakage under grid is N-type not adding transoid in grid voltage situation, injects the ion that ion is mainly little work function.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, first above thin oxide layer, by wet the eat-backing of appended sample grid, form respectively T1 and T2 gate trench separately, then in T1 and T2 gate trench separately, be formed with respectively high dielectric layer and the metal oxide dielectric materials layer above it.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, high dielectric layer and metal oxide dielectric materials layer first form when prepared by sample grid, do not remove while eat-backing appended sample grid are wet.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, the operation of described twice regulatory work function can be exchanged.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, the ion of described little work function comprises that following column element is a kind of ion of base or the combination of different kinds of ions: Li, Mg, Ca, Sc, Mn, Ga, Rb, Sr, Y, Zr, Nb, In, Cs, Ba, La, Nd, Pr, Pm, Gd, Dy, Ho, Tb, Yb, Tm, Er, Lu, Hf, Ta, Pb, Fr, Ra, Ac, Th.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, the ion of described large work function comprises that following column element is a kind of ion of base or the combination of different kinds of ions: B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po.
A preparation method for pair transistor zero capacitance dynamic ram, pair transistor is wherein two cascade MOS transistor T1 and the T2 being formed on common substrate, wherein, comprises front standby operation, wherein: described front standby operation comprises:
T1 and T2 separately the channel surface between source-drain electrode form thin oxide layer;
Above thin oxide layer, by wet the eat-backing of appended sample grid, form respectively T1 and T2 gate trench separately;
By Implantation, making the channel region near source electrode and drain electrode in the channel region of T1 is the doping type identical with source-drain area not adding transoid in grid voltage situation, and to make the channel region near source electrode and drain electrode in the channel region of T2 be the doping type contrary with source-drain area not adding transoid in grid voltage situation.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, when two cascade MOS transistor T1 and T2 are all NMOS structure, described front standby operation comprises:
T1 and T2 separately the channel surface between source-drain electrode form thin oxide layer;
Above thin oxide layer, by wet the eat-backing of appended sample grid, form respectively T1 and T2 gate trench separately;
Carry out photoetching, T1 regional window is opened, T2 regional window is closed, carry out angle inclination, rotate two-way injection P or As ion after 180 degree, causing the channel region near source and leakage under grid is N-type not adding transoid in grid voltage situation;
Carry out photoetching, T2 regional window is opened, T1 regional window is closed, carry out angle inclination, rotate two-way injection B or BF2 or BF or In ion after 180 degree, causing diffusion zone under the grid of source and leakage is P type not adding transoid in grid voltage situation.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, when two cascade MOS transistor T1 and T2 are all PMOS structure, described front standby operation comprises:
T1 and T2 separately the channel surface between source-drain electrode form thin oxide layer;
Above thin oxide layer, by wet the eat-backing of appended sample grid, form respectively T1 and T2 gate trench separately;
Carry out photoetching, T1 regional window is opened, T2 regional window is closed, carry out angle inclination, rotate two-way injection B or BF2 or BF or In ion after 180 degree, causing the channel region near source and leakage under grid is P type not adding transoid in grid voltage situation;
Carry out photoetching, T2 regional window is opened, T1 regional window is closed, carry out angle inclination, rotate two-way injection P or As ion after 180 degree, causing diffusion zone under the grid of source and leakage is N-type not adding transoid in grid voltage situation.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, the operation of described twice Implantation compensation can be exchanged.
The preparation method of above-mentioned pair transistor zero capacitance dynamic ram, wherein, adopts rapid thermal treatment or transient peak annealing or flash annealing to inject ion to activate.
Those skilled in the art reads the detailed description of following preferred embodiment, and with reference to after accompanying drawing, the advantage of these and other aspects of the present invention undoubtedly will be apparent.
Accompanying drawing explanation
With reference to appended accompanying drawing, to describe more fully embodiments of the invention, yet appended accompanying drawing only, for explanation and elaboration, does not form limitation of the scope of the invention.
Fig. 1 is the NMOS cellular construction of buoyancy aid/grid of the prior art unit pair transistor dynamic ram structure;
Fig. 2 is the change in voltage characteristic of utilizing each node under the various states of this pair transistor dynamic ram of UFDG/Spice3 model emulation in buoyancy aid/grid of the prior art unit pair transistor dynamic ram structure preparation process;
Fig. 3 A ~ Fig. 3 D is respectively that the preparation method of pair transistor zero capacitance dynamic ram of the present invention adopts the work function of NMOS structure to regulate the flowage structure schematic diagram of the embodiment of pattern;
Fig. 4 is that the preparation method of pair transistor zero capacitance dynamic ram of the present invention adopts the work function of NMOS structure to regulate the status architecture schematic diagram after the flow process of the embodiment of pattern completes;
Fig. 5 A ~ Fig. 5 D is respectively that the preparation method of pair transistor zero capacitance dynamic ram of the present invention adopts the work function of PMOS structure to regulate the flowage structure schematic diagram of the embodiment of pattern;
Fig. 6 is that the preparation method of pair transistor zero capacitance dynamic ram of the present invention adopts the work function of PMOS structure to regulate the status architecture schematic diagram after the flow process of the embodiment of pattern completes;
Fig. 7 A ~ Fig. 7 D is respectively the flowage structure schematic diagram of the embodiment of the preparation method of the pair transistor zero capacitance dynamic ram of the present invention Implantation compensation model that adopts NMOS structure;
Fig. 8 is the status architecture schematic diagram after the flow process of the embodiment of the preparation method of the pair transistor zero capacitance dynamic ram of the present invention Implantation compensation model that adopts NMOS structure completes;
Fig. 9 A ~ Fig. 9 D is respectively the flowage structure schematic diagram of the embodiment of the preparation method of the pair transistor zero capacitance dynamic ram of the present invention Implantation compensation model that adopts PMOS structure;
Figure 10 is the status architecture schematic diagram after the flow process of the embodiment of the preparation method of the pair transistor zero capacitance dynamic ram of the present invention Implantation compensation model that adopts PMOS structure completes.
Embodiment
The present invention is the preparation method of grid pair transistor zero capacitance dynamic ram after a kind of silicon-on-insulator with manufacturability design, pair transistor is wherein two cascade MOS transistor T1 and the T2 being formed on common substrate, specifically comprise front standby operation and subsequent handling, wherein, front standby operation comprises:
T1 and T2 separately the channel surface between source-drain electrode be formed with respectively thin oxide layer;
Above thin oxide layer, by wet the eat-backing of appended sample grid, form respectively T1 and T2 gate trench separately, and in T1 and T2 gate trench separately, be formed with respectively high dielectric layer and the metal oxide dielectric materials layer above it.Alternatively, high dielectric layer and metal oxide dielectric materials layer also can first form when prepared by sample grid, do not remove while eat-backing appended sample grid are wet;
By T1, the T2 opening of gate trench separately, by Implantation, change respectively metal oxide dielectric materials layer that T1, T2 comprise near the work function at the two ends of source electrode and drain electrode, so that the region near source electrode and drain electrode is the doping type identical with source-drain area not adding change (being transoid) in grid voltage situation in T1 channel region, the region near source electrode and drain electrode in T2 channel region is the doping type contrary with source-drain area not adding change (being transoid) in grid voltage situation;
Subsequent handling comprises:
At two cascade MOS transistor T1 and difference plated metal barrier layer, T2 surface and metal level, by cmp, form grid afterwards;
Deposit an insulating barrier;
Above grid, source electrode and drain electrode, in insulating barrier, form through hole and contact, and draw wire by back segment interconnection process.
embodiment mono-, when two cascade MOS transistor T1 and T2 are all NMOS structure, specifically comprise the steps:
As shown in Figure 3A, by wet the eat-backing of appended sample grid, form respectively T1 and T2 gate trench separately, the gate dielectric layer of T1 and T2 comprises high dielectric layer 2(HK layer) and the metal oxide dielectric materials layer 3(Cap layer above it), the high dielectric layer 2 belows one deck thin oxide layer 1 of can growing alternatively, the gate dielectric layer of T1 and T2 can form after eat-backing sample grid are wet, also can when prepared by sample grid, form and at sample grid, wets while eat-backing and do not remove;
As shown in Figure 3 B, carry out photoetching, T1 regional window is opened, T2 regional window is closed, carry out angle inclination, carry out two-way Implantation so that grid reduce work function near source and leak after rotating 180 degree, causing the channel region near source and leakage under grid is N-type not adding change (being transoid) in grid voltage situation, the ion that injection ion is little work function, the work function characteristics of the metal oxide dielectric materials layer 3 of the top is corresponding there is variation, and thin oxide layer 1 and high dielectric layer 2 are not affected;
As shown in Figure 3 C, carry out photoetching, T2 regional window is opened, T1 regional window is closed, carry out angle inclination, rotate after 180 degree and carry out two-way Implantation so that grid increase work function near source and leak, cause under the grid of source and leakage diffusion zone to change (being transoid) for P type not adding in grid voltage situation, inject the ion that ion is mainly large work function, the work function characteristics of the metal oxide dielectric materials layer 3 of the top is corresponding there is variation, and thin oxide layer 1 and high dielectric layer 2 are not affected.
The operation of above-mentioned twice regulatory work function can be exchanged, and as shown in Figure 3 D, referring to the double-head arrow indication of below, leak in the source of T1 on one side of having realized has larger overlappingly with grid for schematic diagram after completing work function and regulating, and leak with grid without overlapping in the source of another side T2.
Wherein, the ion of above-mentioned little work function is to take the ion that the elements such as Li, Mg, Ca, Sc, Mn, Ga, Rb, Sr, Y, Zr, Nb, In, Cs, Ba, La, Nd, Pr, Pm, Gd, Dy, Ho, Tb, Yb, Tm, Er, Lu, Hf, Ta, Pb, Fr, Ra, Ac, Th are base, and the ion of above-mentioned large work function is to take the ion that the elements such as B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po are base.
After completing above-mentioned steps, then at two cascade nmos pass transistor T1 and T2 surface deposition metal barrier and metal level, by cmp, form grid 0 afterwards; Deposit an insulating barrier 4; Above grid 0, source electrode and drain electrode, in insulating barrier, form through hole and contact 5, and draw wire by back segment interconnection process, according to the circuit diagram in Fig. 1, connect respectively, guarantee that the tagma of T1 is to be connected with the grid of T2, the status architecture schematic diagram after completing as shown in Figure 4.
embodiment bis-,when two cascade MOS transistor T1 and T2 are all PMOS structure, specifically comprise the steps:
As shown in Figure 5A, by wet the eat-backing of appended sample grid, form respectively T1 and T2 gate trench separately, the gate dielectric layer of T1 and T2 comprises high dielectric layer 2(HK layer) and the metal oxide dielectric materials layer 3(Cap layer above it), the high dielectric layer 2 belows one deck thin oxide layer 1 of can growing alternatively, the gate dielectric layer of T1 and T2 can form after eat-backing sample grid are wet, also can when prepared by sample grid, form and at sample grid, wets while eat-backing and do not remove;
As shown in Figure 5 B, carry out photoetching, T1 regional window is opened, T2 regional window is closed, carry out angle inclination, rotate after 180 degree and carry out two-way Implantation so that grid increase work function near source and leak, causing the channel region near source and leakage under grid is P type not adding change (being transoid) in grid voltage situation, inject the ion that ion is mainly large work function, the work function characteristics of the metal oxide dielectric materials layer 3 of the top is corresponding there is variation, and thin oxide layer 1 and high dielectric layer 2 are not affected;
As shown in Figure 5 C, carry out photoetching, T2 regional window is opened, T1 regional window is closed, carry out angle inclination, carry out two-way Implantation so that grid reduce work function near source and leak after rotating 180 degree, causing the channel region near source and leakage under grid is N-type not adding change (being transoid) in grid voltage situation, inject the ion that ion is mainly little work function, the work function characteristics of the metal oxide dielectric materials layer 3 of the top is corresponding there is variation, and thin oxide layer 1 and high dielectric layer 2 are not affected.
The operation of above-mentioned twice regulatory work function can be exchanged, and as shown in Figure 5 D, referring to the double-head arrow indication of below, leak in the source of T1 on one side of having realized has larger overlappingly with grid for schematic diagram after completing work function and regulating, and leak with grid without overlapping in the source of another side T2.
Wherein, the ion of above-mentioned little work function is to take the ion that the elements such as Li, Mg, Ca, Sc, Mn, Ga, Rb, Sr, Y, Zr, Nb, In, Cs, Ba, La, Nd, Pr, Pm, Gd, Dy, Ho, Tb, Yb, Tm, Er, Lu, Hf, Ta, Pb, Fr, Ra, Ac, Th are base, and the ion of above-mentioned large work function is to take the ion that the elements such as B, C, Al, Ti, Cr, Ni, Ge, As, Se, Rh, Pd, Te, Re, Pt, Au, Hg, Po are base.
After completing above-mentioned steps, then at two cascade PMOS transistor Ts 1 and T2 surface deposition metal barrier and metal level, by cmp, form grid 0 afterwards; Deposit an insulating barrier 4; Above grid 0, source electrode and drain electrode, in insulating barrier, form through hole and contact 5, and draw wire by back segment interconnection process, according to the circuit diagram in Fig. 1, connect respectively, guarantee that the tagma of T1 is to be connected with the grid of T2, the status architecture schematic diagram after completing as shown in Figure 6.
The present invention is the preparation method of grid pair transistor zero capacitance dynamic ram after a kind of silicon-on-insulator with manufacturability design, pair transistor is wherein two cascade MOS transistor T1 and the T2 being formed on common substrate, specifically comprise front standby operation and subsequent handling, wherein, front standby operation comprises: T1 and T2 separately the channel surface between source-drain electrode form thin oxide layer;
Above thin oxide layer, by wet the eat-backing of appended sample grid, form respectively T1 and T2 gate trench separately; By T1, the T2 opening of gate trench separately, by Implantation, make in the channel region of T1 to change (being transoid) for the doping type identical with source-drain area near the channel region of source electrode and drain electrode not adding in grid voltage situation, and make in the channel region of T2 to change (being transoid) for the doping type contrary with source-drain area near the channel region of source electrode and drain electrode not adding in grid voltage situation;
Form the metal oxide dielectric materials layer of high dielectric layer and its top;
Subsequent handling comprises:
At two cascade MOS transistor T1 and T2 surface deposition metal barrier and metal level, by cmp, form grid afterwards;
Deposit an insulating barrier;
Above grid, source electrode and drain electrode, in insulating barrier, form through hole and contact, and draw wire by back segment interconnection process.
embodiment mono-,when two cascade MOS transistor T1 and T2 are all NMOS structure, specifically comprise the steps: as shown in Figure 7 A, by wet the eat-backing of appended sample grid, form respectively T1 and T2 gate trench separately, T1 and T2 separately the channel surface between source-drain electrode only form a thin oxide layer 1;
As shown in Figure 7 B, carry out photoetching, T1 regional window is opened, T2 regional window is closed, carry out angle inclination, rotate two-way injection P or As ion after 180 degree, cause under grid near the channel region of source and leakage and change (being transoid) for N-type not adding in grid voltage situation;
As shown in Fig. 7 C, carry out photoetching, T2 regional window is opened, T1 regional window is closed, carry out angle inclination, rotate two-way injection B or BF after 180 degree
2or BF or In ion, causing diffusion zone under the grid of source and leakage is P type not adding transoid in grid voltage situation.
The operation of above-mentioned twice Implantation compensation can be exchanged, and adopts rapid thermal treatment (RTP) or transient peak annealing (Spike Anneal) or flash annealing (Flash Anneal) to activate injection ion.Complete schematic diagram after Implantation compensated regulation as shown in Fig. 7 D.
After completing above-mentioned steps, then in T1 and T2 gate trench separately, be formed with high dielectric layer 2(HK layer) and the metal oxide dielectric materials layer 3(Cap layer above it); At two cascade nmos pass transistor T1 and T2 surface deposition metal level, by cmp, form grid 0 afterwards; Deposit an insulating barrier 4; Above grid 0, source electrode and drain electrode, in insulating barrier, form through hole and contact 5, and draw wire by back segment interconnection process, according to the circuit diagram in Fig. 1, connect respectively, guarantee that the tagma of T1 is to be connected with the grid of T2, the status architecture schematic diagram after completing as shown in Figure 8.
embodiment bis-,when two cascade MOS transistor T1 and T2 are all PMOS structure, specifically comprise the steps:
As shown in Figure 9 A, by wet the eat-backing of appended sample grid, form respectively T1 and T2 gate trench separately, T1 and T2 separately the channel surface between source-drain electrode only form a thin oxide layer 1;
As shown in Figure 9 B, carry out photoetching, T1 regional window is opened, T2 regional window is closed, carry out angle inclination, rotate two-way injection B or BF after 180 degree
2or BF or In ion, causing the channel region near source and leakage under grid is P type not adding change (being transoid) in grid voltage situation;
As shown in Figure 9 C, carry out photoetching, T2 regional window is opened, T1 regional window is closed, carry out angle inclination, rotate two-way injection P or As ion after 180 degree, cause under the grid of source and leakage diffusion zone to change (being transoid) for N-type not adding in grid voltage situation.
The operation of above-mentioned twice Implantation compensation can be exchanged, and adopts rapid thermal treatment (RTP) or transient peak annealing (Spike Anneal) or flash annealing (Flash Anneal) to activate injection ion.Complete schematic diagram after Implantation compensated regulation as shown in Fig. 9 D.
After completing above-mentioned steps, then in T1 and each comfortable gate trench of T2, be formed with high dielectric layer 2(HK layer) and the metal oxide dielectric materials layer 3(Cap layer above it); At two cascade PMOS transistor Ts 1 and T2 surface deposition metal level, by cmp, form grid 0 afterwards; Deposit an insulating barrier 4; Above grid 0, source electrode and drain electrode, in insulating barrier, form through hole and contact 5, and draw wire by back segment interconnection process, according to the circuit diagram in Fig. 1, connect respectively, guarantee that the tagma of T1 is to be connected with the grid of T2, the status architecture schematic diagram after completing as shown in figure 10.
By explanation and accompanying drawing, provided the exemplary embodiments of the ad hoc structure of embodiment, for example, this case is to set forth with PMOS device and nmos device, based on the present invention's spirit, chip also can be done the conversion of other types.Therefore, although foregoing invention has proposed existing preferred embodiment, yet these contents are not as limitation.
For a person skilled in the art, read after above-mentioned explanation, various changes and modifications undoubtedly will be apparent.Therefore, appending claims should be regarded whole variations and the correction of containing true intention of the present invention and scope as, and within the scope of claims, scope and the content of any and all equivalences, all should think and still belong to the intent and scope of the invention.
Claims (5)
1. a preparation method for pair transistor zero capacitance dynamic ram, pair transistor is wherein two cascade MOS transistor T1 and the T2 being formed on common substrate, it is characterized in that, comprise front standby operation, described front standby operation comprises:
T1 and T2 separately the channel surface between source-drain electrode be formed with respectively thin oxide layer;
Above thin oxide layer, by wet the eat-backing of appended sample grid, be formed with respectively T1 and T2 gate trench separately, and in T1 and T2 gate trench separately, be formed with respectively high dielectric layer and the metal oxide dielectric materials layer above it;
By T1, the T2 opening of gate trench separately, by Implantation, change respectively metal oxide electricity dielectric material layer that T1, T2 comprise near the work function at the two ends of source electrode and drain electrode, so that the region near source electrode and drain electrode is the doping type identical with source-drain area not adding transoid in grid voltage situation in T1 channel region, the region near source electrode and drain electrode in T2 channel region is the doping type contrary with source-drain area not adding transoid in grid voltage situation.
2. the preparation method of pair transistor zero capacitance dynamic ram according to claim 1, it is characterized in that, first above thin oxide layer, by wet the eat-backing of appended sample grid, form respectively T1 and T2 gate trench separately, then in T1 and T2 gate trench separately, be formed with respectively high dielectric layer and the metal oxide dielectric materials layer above it.
3. the preparation method of pair transistor zero capacitance dynamic ram according to claim 1, is characterized in that, high dielectric layer and metal oxide dielectric materials layer first form when prepared by sample grid, does not remove while eat-backing appended sample grid are wet.
4. a preparation method for pair transistor zero capacitance dynamic ram, pair transistor is wherein two cascade MOS transistor T1 and the T2 being formed on common substrate, it is characterized in that, comprises front standby operation, wherein: described front standby operation comprises:
T1 and T2 separately the channel surface between source-drain electrode form thin oxide layer;
Above thin oxide layer, by wet the eat-backing of appended sample grid, form respectively T1 and T2 gate trench separately;
By Implantation, making the channel region near source electrode and drain electrode in the channel region of T1 is the doping type identical with source-drain area not adding transoid in grid voltage situation, and to make the channel region near source electrode and drain electrode in the channel region of T2 be the doping type contrary with source-drain area not adding transoid in grid voltage situation.
5. the preparation method of pair transistor zero capacitance dynamic ram according to claim 4, is characterized in that, adopts rapid thermal treatment or transient peak annealing or flash annealing to inject ion to activate.
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| CN103855008A (en) * | 2012-11-30 | 2014-06-11 | 中国科学院微电子研究所 | N-type MOSFET and manufacturing method thereof |
| CN104103502B (en) * | 2013-04-02 | 2017-02-22 | 中芯国际集成电路制造(上海)有限公司 | Formation method of transistor |
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