CN102436998B - Field emission display panel - Google Patents

Abstract

A field emission display panel. The substrate includes at least a display area and a non-display area. A first conductive layer is disposed in the display area, and the first conductive layer includes a first electrode line and a first electrode electrically connected to the first electrode line. A resistive material layer is located on the first conductive layer in the display area. An insulating layer covers the resistive material layer in the display area and has a first opening and a second opening, wherein the first opening exposes a portion of the resistive material layer above the first electrode, and the second opening exposes a portion of the resistive material layer above the first electrode line. An electron emission element is disposed on the resistive material layer exposed by the first opening. A second conductive layer is disposed on the insulating layer and in the second opening, wherein the second conductive layer includes a second electrode line and a second electrode electrically connected to the second electrode line, and the second electrode has a third opening to expose the electron emission element, and the second electrode line and the first electrode line at least define a first sub-pixel area and a second sub-pixel area.

Description

Field Emission Display Panel

technical field

The present invention relates to a display panel, and in particular to a field emission display panel.

Background technique

Generally speaking, the field emission display panel mainly manufactures the electron emitter (electron emitter) on the cathode in an ultra-high vacuum environment (less than 10-6 Torr), and uses the high aspect ratio (high aspect ratio) of the electron emitter. aspect ratio) to help electrons overcome the work function of the cathode and leave the cathode. In addition, in the field emission display panel, if the phosphor powder is coated on the anode, and the high electric field between the cathode and the anode causes the electrons to be led out from the electron emission end of the cathode, and directly hits the electrons on the anode through the action of the electric field. Phosphor, which emits visible light.

The problem faced by the current field emission display panel is that the brightness uniformity of the display panel is insufficient. In other words, in the traditional field emission display panel, the current of the electron emission terminal in some regions will be significantly different from the current of the electron emission terminal in another part of the region, which will cause the uniformity of the overall luminous brightness of the display panel. poor degree.

Contents of the invention

The invention provides a field emission display panel, which can improve the problem of insufficient uniformity of luminous brightness of the traditional field emission display panel.

The invention provides a field emission display panel, which includes a substrate, a first resistance element, a first conductive pattern, an electron emission element, a second resistance element, a second conductive pattern and a conductive layer. The substrate at least has a display area and a non-display area, and the display area at least includes a first sub-pixel area and a second sub-pixel area. The first resistance element is disposed in the first sub-pixel area and the second sub-pixel area, wherein the resistance value of the first resistance element in the first sub-pixel area is different from the resistance value of the first resistance element in the second sub-pixel area . The first conductive pattern is connected to one end of the first resistance element in the first sub-pixel area and one end of the first resistance element in the second sub-pixel area. The electron emission element is arranged in the first sub-pixel area and the second sub-pixel area, and is connected to the other end of the first resistance element in the first sub-pixel area and the other end of the first resistance element in the second sub-pixel area. The second resistance element is disposed in the first sub-pixel area and the second sub-pixel area, wherein the resistance value of the second resistance element in the first sub-pixel area is different from the resistance value of the second resistance element in the second sub-pixel area . The second conductive pattern is connected to one end of the second resistance element in the first sub-pixel area and one end of the second resistance element in the second sub-pixel area. The conductive layer is connected to the other end of the second resistance element in the first sub-pixel area and the other end of the second resistance element in the second sub-pixel area, wherein the conductive layer surrounds and floats on the electron emission element.

The first resistive element and the second resistive element include a resistive material layer.

The first conductive pattern and the second conductive pattern are composed of the same film layer.

The conductive layer is located on the first resistive element, the second resistive element, the first conductive pattern and the second conductive pattern.

It further includes an insulating layer, which is located under the conductive layer and does not cover the electron emission element.

When the first resistive element and the second resistive element are projected onto the substrate, the first resistive element does not overlap with the second resistive element.

The voltage transmitted by the conductive layer is given to the electron emission element through the second resistance element of the first sub-pixel area, and the voltage transmitted by the conductive layer is given to the second resistance element of the second sub-pixel area. The currents of the electron emission elements are substantially the same.

The present invention further provides a field emission display panel, which includes a substrate, a first conductive layer, a resistive material layer, an insulating layer, an electron emission element, and a second conductive layer. The substrate at least includes a display area and a non-display area. The first conductive layer is disposed in the display area, and the first conductive layer includes first electrode lines and first electrodes electrically connected to the first electrode lines. The resistive material layer is located on the first conductive layer in the display area. The insulating layer covers the resistive material layer in the display area, and the insulating layer has a first opening and a second opening, the first opening exposes a part of the resistive material layer above the first electrode, and the second opening exposes a portion of the resistive material layer above the first electrode. Part of the resistive material layer above the first electrode lines. The electron emission element is disposed on the resistance material layer exposed by the first opening. The second conductive layer is disposed on the insulating layer and in the second opening, wherein the second conductive layer includes a second electrode line and a second electrode electrically connected to the second electrode line, and the second electrode has a third opening to expose The electron emission element, and the second electrode line and the first electrode line at least define a first sub-pixel area and a second sub-pixel area.

The projected area of the second opening in the first sub-pixel region to the substrate is substantially different from the projected area of the second opening in the second sub-pixel region to the substrate.

The second conductive layer contacts the surface of the resistive material layer located in the second opening.

The second opening in the first sub-pixel area is located at the intersection of the first electrode line and the second electrode line.

The second opening in the second sub-pixel area is located at the intersection of the first electrode line and the second electrode line.

There is a gap between the first electrode line and the first electrode, so that the first electrode line is separated from the first electrode.

The projected area of the first opening in the first sub-pixel region to the substrate is substantially different from the projected area of the first opening in the second sub-pixel region to the substrate.

The area of the electron emission element in the first sub-pixel area is substantially different from the area of the electron emission element in the second sub-pixel area.

Based on the above, in the present invention, a first resistor element and a second resistor element are respectively provided in the first sub-pixel area and the second sub-pixel area of the field emission display panel. In particular, the resistance value of the first resistance element in the first sub-pixel area is different from the resistance value of the first resistance element in the second sub-pixel area, and the resistance value of the second resistance element in the first sub-pixel area is different The resistance value of the second resistance element in the second sub-pixel area. The arrangement of the above-mentioned first resistance element and the second resistance element can reduce the difference between the currents generated by the electron emission elements in the first sub-pixel area and the second sub-pixel area of the field emission display panel, thereby improving the field emission display The uniformity of the luminous brightness of the panel.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic top view of a field emission display panel according to an embodiment of the invention.

FIG. 2A is an equivalent circuit diagram of a first sub-pixel region of the field emission display panel of FIG. 1 .

FIG. 2B is a schematic top view of the first sub-pixel region of the field emission display panel of FIG. 1 .

FIG. 2C is a schematic cross-sectional view of FIG. 2B along section lines I-I' and II-II'.

FIG. 2D is a schematic top view of a first sub-pixel region of a field emission display panel according to another embodiment.

FIG. 3A is an equivalent circuit diagram of a second sub-pixel region of the field emission display panel of FIG. 1 .

FIG. 3B is a schematic top view of the second sub-pixel region of the field emission display panel of FIG. 1 .

FIG. 3C is a schematic cross-sectional view along the section lines I-I' and II-II' of FIG. 3B.

FIG. 3D is a schematic top view of the second sub-pixel region of the field emission display panel according to another embodiment.

Explanation of reference signs

100: Substrate A: Display area

B: Non-display area P1: The first sub-pixel area

P2: The second sub-pixel area Ra-1: The first resistance element

Rb-1: Second resistance element Ro-1: Resistance

Va-1, Vb-1, V1, Vg-1, HV1L: Voltage

110-1: Electron emission element 102: The first conductive layer

102a-1, 102a-2: first electrode (first conductive pattern)

102b-1, 102b-2, 102c-1, 102c-2: first electrode line (second conductive pattern)

103: Resistance material layer 104: Insulation layer

106: second conductive layer 106a-1, 106a-2: second electrode

106b-1, 106b-2: second electrode wire Oa-1, Oa-2: first opening

Ob-1, Ob-2: Second opening Oc-1, 0c-2: Third opening

Detailed ways

FIG. 1 is a schematic top view of a field emission display panel according to an embodiment of the invention. Referring to FIG. 1 , the field emission display panel of this embodiment includes a substrate 100 . According to this embodiment, the material of the substrate 100 can be glass, quartz, polymer, or opaque/reflective material (for example: conductive material, metal, wafer, ceramic, or other applicable materials), or other Applicable materials. The substrate 100 at least has a display area A and a non-display area B, and the non-display area B surrounds the display area A. In addition, in the display area A there are a plurality of sub-pixel areas arranged in an array. In FIG. 1 , only the first sub-pixel region P1 and the second sub-pixel region P2 are marked for detailed description. The first sub-pixel area P1 and the second sub-pixel area P2 are respectively located at the edge and the center of the display area A for illustration, but the present invention is not limited thereto. According to other embodiments, both the first sub-pixel region P1 and the second sub-pixel region P2 may be located at the edge of the display area A, or both may be located near the center of the display area A.

The structure in the above-mentioned first sub-pixel region P1 will be described in detail below. FIG. 2A is an equivalent circuit diagram of a first sub-pixel region of the field emission display panel of FIG. 1 . FIG. 2B is a schematic top view of the first sub-pixel region of the field emission display panel of FIG. 1 . FIG. 2C is a schematic cross-sectional view of FIG. 2B along section lines I-I' and II-II'.

Please refer to FIG. 2A, FIG. 2B and FIG. 2C at the same time. In the first sub-pixel area P1, a first conductive layer 102, a resistive material layer 103, an insulating layer 104, an electron emission element 110-1 and a second conductive layer 106 are provided. .

The first conductive layer 102 includes a first electrode line 102b-1 and a first electrode 102a-1 electrically connected to the first electrode line 102b-1. Here, the first electrode 102a-1 of the first conductive layer 102 may be referred to as a first conductive pattern, and the first electrode line 102b-1 of the first conductive layer 102 may be referred to as a second conductive pattern. Therefore, in this embodiment, the first conductive pattern (first electrode 102a-1) and the second conductive pattern (first electrode line) 102b-1 are composed of the same film layer (first conductive layer) 102, but The present invention is not limited thereto. According to other embodiments, the first conductive pattern (first electrode 102a-1) and the second conductive pattern (first electrode line) 102b-1 may also be composed of different film layers. Based on the consideration of conductivity, the first conductive layer 102 is generally made of metal material. However, the present invention is not limited thereto, and according to other embodiments, the first conductive layer 102 may also use other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable materials), or stacked layers of metal materials and other conductive materials.

The resistive material layer 103 is located on the first conductive layer 102 . According to this embodiment, the resistance material layer 103 includes silicon, amorphous silicon, crystalline silicon, silicide, diamond-like carbon (diamond-like carbon, DLC), silicon carbide, amorphous carbon, ceramic materials (for example: cermet (cermet) ), or other materials with the same properties), semiconductor oxides, semiconductor nitrides, metal oxides, metal nitrides, metal oxynitrides, the above materials have porosity, or other applicable resistive materials, or the above materials any two combinations of . The resistive material layer 103 serves as a first resistive element Ra-1 above the first conductive pattern (first electrode 102a-1), and one end of the first resistive element Ra-1 is connected to the first conductive pattern 102a-1. The resistive material layer 103 serves as a second resistive element Rb-1 above the second conductive pattern (first electrode line) 102b-1, and one end of the second resistive element Rb-1 is connected to the second conductive pattern 102b-1. In addition, when the first resistive element Ra- 1 and the second resistive element Rb- 1 are projected onto the substrate 100 , the first resistive element Ra- 1 does not overlap with the second resistive element Rb- 1 .

The insulating layer 104 covers the resistive material layer 103, and the insulating layer 104 has a first opening Oa-1 and a second opening Ob-1. The first opening Oa-1 exposes a portion of the resistive material layer 103 above the first electrode (first conductive pattern) 102a-1, and the second opening Ob-1 exposes a portion of the resistive material layer 103 above the first electrode line (second conductive pattern). pattern) 102b-1 above a portion of the resistive material layer 103.

The electron emission element 110 - 1 is disposed on the resistive material layer 103 exposed by the first opening Oa - 1 of the insulating layer 104 . Therefore, the electron emission element 110-1 is connected to the other end of the first resistance element Ra-1 in the first sub-pixel region P1. The electron emission element 110 - 1 can be a cone made of metal material, a carbon nanotube electron emission end, or an electron emission end in the form of other tip discharges, or a combination of the above two emission ends. The present invention is not limited to the number of electron emission elements 110-1 disposed in the first sub-pixel region P1. In other words, the number of electron emission elements 110-1 disposed in the first sub-pixel region P1 may be more than the number shown in the figure. Furthermore, the present invention is not limited to the region where the electron emission element 110-1 disposed in the first sub-pixel region P1 is only regarded as an electron emission region. In other words, a plurality of electron emission regions may be disposed in the first sub-pixel region P1.

The second conductive layer 106 is disposed on the insulating layer 104 and filled into the second opening Ob-1. According to this embodiment, the second conductive layer 106 is more in contact with the surface of the resistive material layer 103 located in the second opening Ob- 1 . In addition, the second conductive layer 106 surrounds and floats on the electron emission device 110-1. In other words, the second conductive layer 106 surrounds the electron emission element 110-1 and is not connected to the electron emission element 110-1.

According to this embodiment, the second conductive layer 106 includes a second electrode line 106b-1 and a second electrode 106a-1 electrically connected to the second electrode line 106b-1. The second electrode 106a-1 of the second conductive layer 106 has a third opening Oc-1 to expose the electron emission element 110-1, and the second electrode line 106b-1 of the second conductive layer 106 is connected to the first sub-pixel region P1 The other end of the second resistive element Rb-1 in. In addition, the insulating layer 104 is located under the second conductive layer 106 and does not cover the electron emission element 110-1. Moreover, the second conductive layer 106 is located on the first resistive element Ra-1, the second resistive element Rb-1, the first conductive pattern 102a-1 and the second conductive pattern 102b-1. Based on the consideration of conductivity, the second conductive layer 106 is generally made of metal material. However, the present invention is not limited thereto, and according to other embodiments, the second conductive layer 106 may also use other conductive materials. For example: alloys, nitrides of metal materials, oxides of metal materials, oxynitrides of metal materials, or other suitable materials), or stacked layers of metal materials and other conductive materials.

According to this embodiment, the extension direction of the second electrode line 106b-1 is not parallel to the extension direction of the first electrode line 102b-1. Preferably, the extension direction of the second electrode line 106b-1 is parallel to the extension direction of the first electrode line The extending direction of 102b-1 is vertical. Therefore, the second electrode line 106b-1 and the first electrode line 102b-1 define the first sub-pixel region P1. In addition, in this embodiment, the second opening Ob-1 in the first sub-pixel region P1 is located at the intersection of the first electrode line 102b-1 and the second electrode line 106b-1.

In the embodiment of FIG. 2B , the first conductive layer 102 in the first sub-pixel region P1 includes a first electrode line 102b-1 and a first electrode 102a-1. However, the present invention is not limited thereto. According to other embodiments, as shown in FIG. 2D , the first conductive layer 102 in the first sub-pixel region P1 includes the first electrode 102a-1, and the first electrode line is composed of 102b-1 and 102c-1. . There is a gap between the first electrode line 102c-1 and the first electrode 102a-1, so that the first electrode line 102c-1 is separated from the first electrode 102a-1. The second opening Ob-1 exposing the second resistance element Rb-1 is correspondingly disposed at the intersection of the first electrode line 102c-1 and the second electrode line 106b-1. Here, the first electrode line 102c-1 and the first electrode line 102b-1 may be respectively connected to corresponding voltages Va-1, Vb-1, and the voltages Va-1, Vb-1 may be the same or different.

In the first sub-pixel region P1 of this embodiment, as shown in FIG. 2A , when the external circuit gives the first sub-pixel region P1 a voltage V1, it will enter the first sub-pixel region after being consumed by the resistance Ro-1 of the external circuit. The voltage value of P1 is Vg-1, and the voltage Vg-1 and the voltage HV1 will drive the electron emission element 110-1 to generate discharge.

Next, the structure in the second sub-pixel region P2 of the field emission display panel of this embodiment will be described in detail. FIG. 3A is an equivalent circuit diagram of a second sub-pixel region of the field emission display panel of FIG. 1 . FIG. 3B is a schematic top view of the second sub-pixel region of the field emission display panel of FIG. 1 . FIG. 3C is a schematic cross-sectional view along the section lines I-I' and II-II' of FIG. 3B.

Please refer to FIG. 3A, FIG. 3B and FIG. 3C at the same time. In the second sub-pixel region P2, the first conductive layer 102, the resistive material layer 103, the insulating layer 104, the electron emission element 110-2 and the second conductive layer 106 are arranged. .

The first conductive layer 102 includes a first electrode line 102b-2 and a first electrode 102a-2 electrically connected to the first electrode line 102b-2. Here, the first electrode 102a-2 of the first conductive layer 102 may be referred to as a first conductive pattern, and the first electrode line 102b-2 of the first conductive layer 102 may be referred to as a second conductive pattern. Therefore, in this embodiment, the first conductive pattern (first electrode 102 a - 2 ) and the second conductive pattern (first electrode line) 102 b - 2 are composed of the same film layer (first conductive layer) 102 .

Similarly, the resistive material layer 103 of the second sub-pixel region P2 is located on the first conductive layer 102 . The resistive material layer 103 above the first conductive pattern (first electrode 102a-2) serves as a first resistive element Ra-2, and one end of the first resistive element Ra-2 is connected to the first conductive pattern 102a-2. The resistive material layer 103 serves as a second resistive element Rb-2 above the second conductive pattern (first electrode line) 102b-2, and one end of the second resistive element Rb-21 is connected to the second conductive pattern 102b-2. In addition, when the first resistive element Ra- 2 and the second resistive element Rb- 2 are projected onto the substrate 100 , the first resistive element Ra- 2 does not overlap with the second resistive element Rb- 2 .

It is worth mentioning that, in this field emission display panel, the resistance value of the first resistance element Ra-1 in the first sub-pixel area P1 is different from that of the first resistance element Ra-2 in the second sub-pixel area P2. resistance value. Moreover, the resistance value of the second resistance element Rb-1 in the first sub-pixel area P1 is different from the resistance value of the second resistance element Rb-2 in the second sub-pixel area P2.

The insulating layer 104 covers the resistive material layer 103 , and the insulating layer 104 has a first opening Oa- 2 and a second opening Ob- 2 . The first opening Oa-2 exposes a portion of the resistive material layer 103 above the first electrode (first conductive pattern) 102a-2, and the second opening Ob-2 exposes a portion of the resistive material layer 103 above the first electrode line (second conductive pattern). A portion of the resistive material layer 103 above the pattern) 102b-2.

It is worth mentioning that, according to an embodiment, the projected area of the first opening Oa-1 in the first sub-pixel region P1 onto the substrate 100 is substantially different from that of the first opening Oa-2 in the second sub-pixel region P2. projected onto the area of the substrate 100 . However, the present invention is not limited thereto. In other embodiments, the projected area of the first opening Oa-1 in the first sub-pixel region P1 onto the substrate 100 is the same as the area of the first opening Oa-2 in the second sub-pixel region P2. The area projected onto the substrate 100 is equivalent. In addition, according to an embodiment, the projected area of the second opening Ob-1 in the first sub-pixel region P1 onto the substrate 110 is substantially different from the projected area of the second opening Ob-2 in the second sub-pixel region P2 onto the substrate 100. area. However, the present invention is not limited thereto. In other embodiments, the projected area of the second opening Ob-1 in the first sub-pixel region P1 onto the substrate 110 may also be the same as the area of the second opening Ob-1 in the second sub-pixel region P2. 2 projected onto the substrate 100 are equivalent.

The electron emission element 110-2 is disposed on the resistive material layer 103 exposed by the first opening Oa-2 of the insulating layer 104. Referring to FIG. Therefore, the electron emission element 110-2 is connected to the other end of the first resistance element Ra-2 in the second sub-pixel region P2. The electron emission element 110-2 can be a cone made of metal material, a carbon nanotube electron emission end, or an electron emission end in the form of other tip discharges, or a combination of the above two emission ends. The present invention is not limited to the number of electron emission elements 110-2 disposed in the second sub-pixel region P2. In other words, the number of electron emission elements 110-2 disposed in the second sub-pixel region P2 may be more than the number shown in the figure. Furthermore, the present invention is not limited to the region where the electron emission element 110-1 disposed in the first sub-pixel region P1 is only regarded as an electron emission region. In other words, a plurality of electron emission regions may be disposed in the first sub-pixel region P1. In addition, the second conductive layer 106 surrounds and floats on the electron emission device 110-2. In other words, the second conductive layer 106 surrounds the electron emission element 110-2 and is not connected to the electron emission element 110-2.

It is worth mentioning that the area of the electron emission element 110-1 in the first sub-pixel region P1 is substantially different from the area of the electron emission element 110-2 in the second sub-pixel region P2. However, the present invention is not limited thereto. According to other embodiments, the area of the electron emission element 110-1 in the first sub-pixel region P1 is substantially equivalent to the area of the electron emission element 110-2 in the second sub-pixel region P2.

The second conductive layer 106 is disposed on the insulating layer 104 and filled into the second opening Ob- 2 . According to this embodiment, the second conductive layer 106 is more in contact with the surface of the resistive material layer 103 located in the second opening Ob- 2 . The second conductive layer 106 includes a second electrode line 106b-2 and a second electrode 106a-2 electrically connected to the second electrode line 106b-2. The second electrode 106a-2 of the second conductive layer 106 has a third opening Oc-2 to expose the electron emission element 110-2, and the second electrode line 106b-2 of the second conductive layer 106 is connected to the second sub-pixel region P2 The other end of the second resistive element Rb-2 in. In addition, the insulating layer 104 is located under the second conductive layer 106 and does not cover the electron emission element 110-2. Moreover, the second conductive layer 106 is located on the first resistive element Ra- 2 , the second resistive element Rb- 2 , the first conductive pattern 102 a - 2 and the second conductive pattern 102 b - 2 .

According to this embodiment, the extension direction of the second electrode line 106b-2 is not parallel to the extension direction of the first electrode line 102b-2. Preferably, the extension direction of the second electrode line 106b-2 is parallel to the extension direction of the first electrode line The extending direction of 102b-2 is vertical. Therefore, the second electrode line 106b-2 and the first electrode line 102b-2 define the second sub-pixel region P2. In addition, in this embodiment, the second opening Ob- 2 in the second sub-pixel region P2 is located at the intersection of the first electrode line 102 b - 2 and the second electrode line 106 b - 2 .

In the embodiment of FIG. 3B , the first conductive layer 102 in the second sub-pixel region P2 includes a first electrode line 102b-2 and a first electrode 102a-2. However, the present invention is not limited thereto. According to other embodiments, as shown in FIG. 3D , the first conductive layer 102 in the second sub-pixel region P2 includes the first electrode 102a-2, and the first electrode line is composed of 102b-2 and 102c-2. . There is a gap between the first electrode line 102c-2 and the first electrode 102a-2, so that the first electrode line 102c-2 is separated from the first electrode 102a-2. The second opening Ob- 2 exposing the second resistance element Rb- 2 is correspondingly disposed at the intersection of the first electrode line 102 c - 2 and the second electrode line 106 b - 2 . Here, the first electrode line 102c-2 and the first electrode line 102b-2 can be respectively connected to corresponding voltages Va-2, Vb-2, and the voltages Va-2, Vb-2 can be the same or different.

In the second sub-pixel region P2 of this embodiment, as shown in FIG. 3A , when the external circuit gives the second sub-pixel region P2 a voltage V2, it enters the second sub-pixel region after being consumed by the resistance Ro-2 of the external circuit. The voltage value of P2 is Vg-2, and the voltage Vg-2 and the voltage HV2 will drive the electron emission element 110-2 to generate discharge.

As mentioned above, in the field emission display panel of this embodiment, the first sub-pixel area P1 has the first resistance element Ra-1 and the second resistance element Rb-1, and the second sub-pixel area P2 has The first resistance element Ra-2 and the second resistance element Rb-2. In particular, the resistance value of the first resistance element Ra-1 in the first sub-pixel area P1 is different from the resistance value of the first resistance element Ra-2 in the second sub-pixel area P2. Moreover, the resistance value of the second resistance element Rb-1 in the first sub-pixel area P1 is different from the resistance value of the second resistance element Rb-2 in the second sub-pixel area P2. Therefore, when the voltage Vg-1 delivered by the second conductive layer 106 passes through the second resistance element Rb-1 of the first sub-pixel region P1, the current given to the electron emission element 110-1 will be the same as that delivered by the second conductive layer 106. The voltage Vg-2 provides substantially the same current to the electron emission element 110-2 via the second resistance element Rb-2 of the second sub-pixel region P2.

In other words, in this embodiment, by arranging the first resistance element and the second resistance element in each sub-pixel area of the field emission display panel, the current of the electron emission elements in all sub-pixel areas of the field emission display panel can be made The difference becomes smaller, thereby improving the uniformity of the luminous brightness of the field emission display panel.

It must be noted that, in the above embodiment, the numbers and shapes of the first opening Oa-1, the second opening Ob-1, and the third opening Oc-1 are not limited to those described in the embodiment, for example: the first opening The respective numbers of Oa-1/Oa-2, second openings Ob-1/Ob-2, and third openings Oc-1/Oc-2 may be at least one or more. The respective shapes of the first opening Oa-1/Oa-2, the second opening Ob-1/Ob-2, and the third opening Oc-1/Oc-2 include circle, rectangle, triangle, rhombus, and pentagon , hexagonal, star-shaped, flower-shaped, arc-shaped, polygonal, zig-zag, gear-shaped, or other suitable shapes, or a combination of any two of the above. In addition, the dimensions of the first opening Oa- 1 /Oa- 2 , the second opening Ob- 1 /Ob- 2 , and the third opening Oc- 1 /Oc- 2 are not limiting conditions.

An example and a comparative example are listed below to illustrate that arranging the first resistor element and the second resistor element in each sub-pixel region of the field emission display panel can indeed improve the uniformity of the luminous brightness of the field emission display panel.

example

In the field emission display panel of this example, a first resistance element and a second resistance element are arranged in each sub-pixel area, wherein the structure of the sub-pixel area of the field emission display panel of this example is as shown in Fig. 2A-Fig. 2C Or as shown in Figure 3A-Figure 3C. In addition, in this example, the voltage given by the external circuit to each sub-pixel area is about 35V, the resistance value of the external circuit is about 3KΩ, and the first conductive layer 102 (the first electrode and the first electrode line) is given about 0V . When the electrical properties of the three sub-pixel regions (sub-pixel regions 1, 2, and 3) of the field emission display panel of this example are measured, the results shown in Table 1 can be obtained.

Table 1

comparative example

In the field emission display panel of this comparative example, only the first resistance element is disposed in each sub-pixel region, and the second resistance element is not disposed. In addition, in this comparative example, the voltage supplied by the external circuit to each sub-pixel region is about 30V, the resistance of the external circuit is about 3KΩ, and the cathode is given about 0V. When the electrical properties of the three sub-pixel regions (sub-pixel regions 1, 2, and 3) of the field emission display panel of this example are measured, the results shown in Table 2 can be obtained.

Table 2

As can be seen from the above example, when the first resistance element and the second resistance element are arranged in each sub-pixel region in the field emission display panel, the uniformity of the current (IRa) of the electron emission element of the field emission display panel can be made Up to about 72.8%. If only the first resistor element is disposed in each sub-pixel region of the field emission display panel, the uniformity of the current (IRa) of the electron emission element of the field emission display panel is only about 66.7%. Therefore, in the present invention, disposing the first resistance element and the second resistance element in each sub-pixel area of the field emission display panel can indeed improve the brightness uniformity of the field emission display panel.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention, so the protection of the present invention The scope should be determined by the claims.

Claims (15)

1. a field emission type display panel, comprising:

One substrate, at least has a viewing area and a non-display area, and this viewing area at least comprises one first sub-pixel area and one second sub-pixel area;

One first resistive element, is arranged in this first sub-pixel area and this second sub-pixel area, and wherein the resistance value of this first resistive element in this first sub-pixel area is different from the resistance value of this first resistive element in this second sub-pixel area;

One first conductive pattern, connects the one end of this first resistive element in one end and this second sub-pixel area of this first resistive element in this first sub-pixel area;

One electronic emission element, is arranged in this first sub-pixel area and this second sub-pixel area, and connects the other end of this first resistive element in the other end and this second sub-pixel area of this first resistive element in this first sub-pixel area;

One second resistive element, is arranged in this first sub-pixel area and this second sub-pixel area, and wherein the resistance value of this second resistive element in this first sub-pixel area is different from the resistance value of this second resistive element in this second sub-pixel area;

One second conductive pattern, connects the one end of this second resistive element in one end and this second sub-pixel area of this second resistive element in this first sub-pixel area; And

One conductive layer, connects the other end of this second resistive element in the other end and this second sub-pixel area of this second resistive element in this first sub-pixel area, wherein this conductive layer around and suspension joint in this electronic emission element;

Wherein the first resistive element in different pixels district equates with the ratio of the resistance value of the second resistive element.

2. as claimed in claim 1 emission type display panel, is characterized in that, this first resistive element and this second resistive element comprise resistance elements.

3. as claimed in claim 1 emission type display panel, is characterized in that, this first conductive pattern and this second conductive pattern are made up of same rete.

4. as claimed in claim 1 emission type display panel, is characterized in that, this conductive layer is positioned at the upper of this first resistive element, this second resistive element, this first conductive pattern and this second conductive pattern.

5. as claimed in claim 1 emission type display panel, is characterized in that, further comprises an insulating barrier, is positioned at the lower of this conductive layer and does not cover this electronic emission element.

6. as claimed in claim 1 emission type display panel, is characterized in that, when this first resistive element and this second resistive element are projected on this substrate, this first resistive element does not overlap with this second resistive element.

7. as claimed in claim 1 emission type display panel, it is characterized in that, the voltage that this conductive layer transmits gives voltage that the electric current of this electronic emission element transmits with this conductive layer gives this electronic emission element electric current via the second resistive element of this second sub-pixel area via this second resistive element of this first sub-pixel area identical in fact.

8. a field emission type display panel, comprising:

One substrate, it at least comprises a viewing area and a non-display area;

One first conductive layer, is arranged in this viewing area, and this first conductive layer comprises the first electrode wires and one first electrode with this first electrode wires electric connection;

One resistance elements, is arranged on this first conductive layer of this viewing area;

One insulating barrier, be covered on this resistance elements in this viewing area, and this insulating barrier has one first opening and one second opening, this first opening exposes position this resistance elements of part above this first electrode, and this second opening exposes position this resistance elements of part above this first electrode wires;

One electronic emission element, is arranged on this resistance elements being come out by this first opening;

One second conductive layer, be arranged on this insulating barrier and in this second opening, one second electrode that wherein this second conductive layer comprises one second electrode wires and is electrically connected with this second electrode wires, and this second electrode has one the 3rd opening to expose this electronic emission element, and this second electrode wires and this first electrode wires at least define one first sub-pixel area and one second sub-pixel area;

The ratio of the resistance value of this resistance elements of part that this resistance elements of part that wherein the first opening comes out comes out with the second opening equates.

9. as claimed in claim 8 emission type display panel, is characterized in that, the area that this second opening in this first sub-pixel area is projected to this substrate is different in essence and is projected to the area of this substrate in the second opening in this second sub-pixel area.

10. as claimed in claim 8 emission type display panel, is characterized in that, this second conductive layer contact is arranged in the surface of this resistance elements of this second opening.

11. as claimed in claim 8 emission type display panels, is characterized in that, this second opening in this first sub-pixel area is to be positioned at this first electrode wires and this second electrode wires staggered place.

12. as claimed in claim 8 emission type display panels, is characterized in that, this second opening in this second sub-pixel area is to be positioned at this first electrode wires and this second electrode wires staggered place.

13. as claimed in claim 8 emission type display panels, is characterized in that, the junction of this first electrode wires and this first electrode has a gap, to make this first electrode wires and this first electrode separation.

14. as claimed in claim 8 emission type display panels, is characterized in that, the area that this first opening in this first sub-pixel area is projected to this substrate is different in essence and is projected to the area of this substrate in this first opening in this second sub-pixel area.

15. as claimed in claim 8 emission type display panels, is characterized in that, this electronic emission element area in this first sub-pixel area is different in essence in this electronic emission element area in this second sub-pixel area.

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