CN102446761B - Method for manufacturing semiconductor structure - Google Patents

Abstract

The invention discloses a manufacturing method of a semiconductor structure, which comprises the following steps: providing a p-type field effect transistor comprising a gate on a substrate; forming a tensile stress layer on the transistor; patterning the tensile stress layer so as to generate compressive stress in a transistor channel; and annealing to memorize the compressive stress in the transistor channel and achieve the purpose of enhancing the transistor performance. The method of the invention utilizes the stress memory technology to memorize the compressive stress in the transistor channel, thereby improving the mobility of the hole and improving the overall performance of the semiconductor structure.

Description

Fabrication method of semiconductor structure

technical field

The present invention generally relates to a method for manufacturing a semiconductor structure, and more specifically, relates to a method for manufacturing a high-performance semiconductor structure using stress memory technology.

Background technique

It is known that applying stress to field effect transistors (FET: field effect transistor) can improve their performance. When stress is applied to a FET, tensile stress can increase electron mobility (or nFET drive current), while compressive stress can increase hole mobility (or pFET drive current).

One way to provide this stress is called stress memory technique (SMT: stressmemorization technique), which includes forming an inherently stressed material (eg, silicon nitride) and annealing various parts of the semiconductor structure, such as above the channel region Stress is memorized in corresponding parts (such as gate region or extension region), and then the stress material is removed. In this way, stress is preserved and hole mobility can be improved, thereby improving the overall performance of the semiconductor structure.

One problem with SMT is that it can only be used with n-type field effect transistors. Specifically, in order to memorize the stress in the semiconductor structure, an annealing operation must be performed, and the annealing operation often needs to be performed at high temperature. However, materials commonly used to apply stress to field effect transistors, such as nitride materials, can only provide tensile stress at high temperatures, which limits the application of SMT technology to n-type field effect transistors.

In view of the above problems, it is necessary to provide an SMT technology that can be used for pFETs.

Contents of the invention

The purpose of the present invention is to provide a kind of SMT technology that can be used for pFET, this method can utilize commonly used stress material to apply compressive stress in the channel of pFET, and after undergoing high temperature annealing operation, can put the stress from above p-type transistor The compressive stress of the layer is memorized into the channel, thereby improving the mobility of holes and improving the overall performance of the semiconductor structure.

In addition, the method of the invention is simple to operate and has strong industrial applicability.

The invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

a) providing a p-type field effect transistor,

b) forming a tensile stress layer on the p-type field effect transistor,

c) removing a part of the tensile stress layer, so that the retained tensile stress layer generates compressive stress in the channel, and

d) Perform annealing.

Preferably, the tensile stress layer includes at least one material selected from Si ₃ N ₄ , SiO ₂ , SiOF, SiCOH, SiCO, SiCON, SiON, PSG and BPSG.

Preferably, in step b), the tensile stress layer is formed by a deposition process.

Preferably, in step c), a part of the tensile stress layer is removed by selective etching.

Preferably, wherein, after step a) and before step b), the etch stop layer is formed by a deposition process. Further preferably, the material of the etching stop layer is different from that of the tensile stress layer. Still further preferably, the etch stop layer includes SiO ₂ .

Preferably, step c) includes: photolithography to form a predetermined pattern of photoresist; and etching the tensile stress layer using the patterned photoresist as a mask. Further preferably, after step c), in the direction of the gate, the distance between the edge of the remaining tensile stress layer and the outer side of the gate is 0.02-0.2 μm.

Preferably, the p-type field effect transistor includes a dummy gate, and the dummy gate includes a dummy gate conductor and a gate dielectric. Further preferably, after step d), step e) is further included: removing the dummy gate conductor to form an opening, and forming a gate in the opening. Still further preferably, in step e), the dummy gate conductor is removed by an etching process, so as to expose the gate dielectric under the dummy gate conductor. Optionally, in step e), the dummy gate conductor and the gate dielectric are removed by an etching process, so as to expose the substrate under the gate dielectric.

In the manufacturing method of the semiconductor structure of the present invention, by combining the photolithography and etching process with the stress memory technology, the compressive stress in the channel of the transistor can be memorized, thereby improving the mobility of holes and improving the overall performance of the semiconductor structure; and , the method of the present invention is simple to operate and has strong industrial applicability.

These and other features, aspects and advantages of the present invention will be more readily understood with reference to the following specification and claims.

Description of drawings

Fig. 1 shows the preliminary structure for one embodiment of the method of the present invention.

2-7 show the intermediate structure of the manufacturing method flow according to an embodiment of the present invention.

Figure 8 shows a semiconductor structure fabricated according to one embodiment of the method of the present invention.

Detailed ways

Hereinafter, the present invention is described by means of specific embodiments shown in the drawings. It should be understood, however, that these descriptions are exemplary only and are not intended to limit the scope of the present invention. Also, in the following description, descriptions of well-known structures and techniques are omitted to avoid unnecessarily obscuring the concept of the present invention.

Top, cross-sectional, and perspective views of various structures of semiconductor structures according to embodiments of the invention are shown in the accompanying drawings. The figures are not drawn to scale, with certain details exaggerated and possibly omitted for clarity. The shapes of the various regions and layers shown in the figure, as well as their relative sizes and positional relationships are only exemplary, and may deviate due to manufacturing tolerances or technical limitations in practice, and those skilled in the art will Regions/layers with different shapes, sizes, and relative positions can be additionally designed as needed.

According to an embodiment of the present invention, a method for manufacturing a high-performance semiconductor structure using stress memory technology is provided, which can memorize the compressive stress in the transistor channel, thereby improving the mobility of holes and improving the overall performance of the semiconductor structure.

Fig. 1 shows the preliminary structure for one embodiment of the method of the present invention.

The preliminary structure is a p-type field effect transistor (pFET) 100 . The pFET 100 shown in FIG. 1 has completed initial processing of the substrate 10, such as conventional shallow trench isolation (STI) 12 formation, well implantation, gate dielectric 14 formation, gate conductor 16 formation, and first spacer Formation of 18.

2-7 show the intermediate structure of the manufacturing method flow according to an embodiment of the present invention.

Referring to FIG. 2, in one embodiment of the method according to the invention, an extension implantation is preferably performed on the initial structure pFET 100. Optionally, halo implantation can also be performed.

Using the gate conductor 16 and the first spacer 18 as a mask, the implantation is extended along the direction indicated by the arrow 202, and is formed on the exposed part of the substrate 10 on both sides of the gate conductor 16 and the first sidewall 18. Extension 20. For pFETs according to embodiments of the present invention, extension implants may be performed with p-type dopants such as boron (B or _BF2 ), indium (In), or combinations thereof. The extension region 20 is used to reduce the electric field peak value and control the short channel effect.

Optionally, using the gate conductor 16 and the first spacer 18 as a mask again, the halo implantation can be performed at a certain inclination along the direction shown by the arrow 204, so that the corresponding The location forms a halo area 21 . For pFETs according to embodiments of the present invention, halo implants may be performed with n-type dopants such as arsenic (As), phosphorus (P), or combinations thereof. Here, the halo region 21 is mainly used to prevent the later formed source/drain region 24 (as shown in FIG. 3 ) from diffusing into the channel region, thereby controlling the short channel effect.

Referring to FIG. 3 , second spacers 22 are formed on both sides of the gate conductor 16 and the first spacers 18 , and source/drain regions 24 are formed.

For example, the second spacer material is formed on the entire semiconductor structure by a conventional deposition process, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering, Then perform anisotropic etching, preferably reactive ion etching (RIE), to form the second sidewall 22 as shown in FIG. 3 . The material of the second side wall 22 and the material of the first side wall 18 may be the same or different. Preferably, the second sidewall 22 may include Si ₃ N ₄ . In subsequent steps, the second sidewall 22 may function as a mask and/or an etching protection layer.

Using the gate conductor 16 and the second spacer 22 as a mask, ion implantation is performed along the direction indicated by the arrow 206. On both sides of the gate region formed by the gate conductor 16 and the second spacer 22, the substrate 10 Source/drain regions 24 are formed in the exposed portions. For pFETs according to embodiments of the present invention, p-type dopants such as boron (B or BF ₂ ), indium (In) or combinations thereof may be used for source/drain implantation. Typically, the polarity of the dopant used in the source/drain region 24 and the extension region 20 is the same, but the type and doping concentration of the selected specific dopant may be the same or different.

Referring to FIG. 4 , an etching stop layer 26 and a tensile stress layer 28 are sequentially formed on the semiconductor structure shown in FIG. 3 . Here, for example, the respective layers may be formed by the aforementioned deposition process. Here, the material of the etch stop layer 26 is different from the material of the tensile stress layer 28 . Typically, the etch stop layer 26 may include SiO ₂ , and the tensile stress layer 28 may include at least one material selected from Si ₃ N ₄ , SiO ₂ , SiOF, SiCOH, SiCO, SiCON, SiON, PSG, and BPSG . Optionally, the etch stop layer 26 may also be formed by thermal oxidation.

Referring to FIGS. 5 and 6 , the tensile stress layer 28 is selectively etched.

Referring to FIG. 5, photolithography is performed to form a predetermined pattern of photoresist. For example, a photoresist 30 is coated on the semiconductor structure shown in FIG. 4 (for example, by a method of spin coating), and the photoresist 30 covers the entire surface of the semiconductor structure. The photoresist 30 is patterned. Typically, the patterning of the photoresist 30 can be achieved through a series of steps such as exposure, development, hard film baking, etc., to obtain a photoresist with a predetermined pattern.

With reference to Fig. 6, take patterned photoresist as a mask, remove a part of tensile stress layer 28, make the remaining tensile stress layer generate compressive stress in the trench, for example, carry out selective etching (such as RIE), and stop at etching. On the etch stop layer 26, the photoresist is removed. Here, compressive stress is concentrated in the channel region after the etching operation. Specifically, in the semiconductor structure shown in FIG. 5 , the tensile stress layer 28 generates tensile stress (T) along the arrow direction to the channel. In the semiconductor structure shown in FIG. 6 , after the etching operation, compressive stress (C) along the direction of the arrow is generated in the tensile stress layer. In this way, the resultant force of the inherent tensile stress (T) and the newly generated compressive stress (C) acts on the channel. Those skilled in the art can understand that when the newly generated compressive stress (C) is greater than the inherent compressive stress (T), compressive stress will be exerted on the channel. If too little stress layer is etched away, the stress generated at the channel position is still an undesirable tensile stress. However, if too many stress layers are etched away, it is difficult for the remaining stress material to generate a large enough compressive stress.

In order to ensure that the stress effect of the etched tensile stress layer 28 on the channel is a compressive stress effect, preferably, in the direction of the gate, the distance L between the edge of the retained tensile stress layer and the outside of the gate is 0.02 -0.2 μm.

7, annealing is performed so that the semiconductor structure can memorize the stress from the tensile stress layer 28, and activate the impurities in the extension region 20 and the source/drain region 24 (and the halo region 21, if any), while repairing the semiconductor Defects in the body and surface of a material. In one embodiment of the present invention, rapid thermal annealing (RTA) may be performed at, for example, about 1000° C., and the thermal annealing process lasts from 0 to about 1 second.

According to the semiconductor manufacturing method of the present invention, by depositing the tensile stress layer, etching, and then annealing, the compressive stress in the channel can be memorized, and a good stress memory effect can be realized.

It can be seen from FIG. 7 that after annealing, the extension region 20 diffuses to the channel region below the gate dielectric 14 .

Referring to FIG. 8 , the tensile stress layer 28 and the etch stop layer 26 are removed (eg, by wet etching or RIE); and a conventional silicide formation process is performed on the semiconductor structure.

Optionally, after removing the tensile stress layer 28 and the etch stop layer 26 , a replacement gate process operation may be performed. Specifically, after removing the tensile stress layer 28 and the etch stop layer 26 , further etching may be performed to remove the dummy gate conductor 16 to expose the gate dielectric 14 . Furthermore, a replacement gate process may be used to form a new gate conductor (not shown). For example, a new gate conductor layer can be formed on the entire surface of the semiconductor structure through a deposition process, and then etched (eg, RIE) to remove the new gate conductor material covering the surface of the substrate and sidewalls.

Optionally, when removing the gate conductor 16 , further etching can be performed to remove the gate dielectric 14 to expose the substrate under the gate dielectric 14 . Furthermore, a replacement gate process can be used to form a new gate dielectric and a new gate conductor. For example, a new gate dielectric and a new gate conductor layer covering the entire surface of the semiconductor structure are formed by a deposition process, and etching (such as RIE) is performed to remove the new gate dielectric and a new gate conductor layer covering the surface of the substrate and sidewalls. polar conductor layer.

Here, the new gate dielectric material may include a high-K material. Non-limiting examples of high-K materials include hafnium-based materials (such as HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, or HfZrO), zirconia, lanthanum oxide, titanium oxide, BST (barium strontium titanate) or PZT (zirconium titanium lead acid).

New gate conductor materials may include, but are not limited to, metals, metal alloys, metal nitrides and metal suicides, and stacks and combinations thereof. Here, the gate conductor layer 36 preferably includes a laminate of a work function metal layer and a gate metal layer; non-limiting examples of the work function metal layer include one or a combination of TiN, TiAlN, TaN, or TaAlN.

As shown in FIG. 8, a conventional silicide formation process is performed on the semiconductor structure. A metal layer (not shown in the figure) is formed on the semiconductor structure by a deposition process, the metal layer covers the entire semiconductor device, and the metal preferably includes NiPt. An annealing process is performed, for example, at about 250° C. to about 500° C., so that the deposited metal reacts with the underlying silicon to form the silicide layer 32 . Here, the silicide layer 32 preferably includes NiPtSi.

In an embodiment of the present invention, silicon is included on the surface of the source/drain region 24 and the gate conductor 16 (gate-first process, of course, if a replacement gate process is used, silicon may or may not be included on the surface of the gate conductor. Including silicon), the silicide layer 32 can reduce the ohmic contact between the metal plug in the contact hole and the source/drain region 24 and the gate conductor 16 in the interconnect structure formed later. Unreacted metal is then selectively removed, for example by wet etching, for example with a solution containing sulfuric acid.

In the manufacturing method of the semiconductor structure of the present invention, by combining the photolithography and etching process with the stress memory technology, the compressive stress in the channel of the transistor can be memorized, thereby improving the mobility of holes and improving the overall performance of the semiconductor structure; and , the method of the present invention is simple to operate and has strong industrial applicability.

Although the semiconductor structure shown in FIG. 8 is taken as an example in the above embodiments, those skilled in the art should recognize that various conventional operations can be performed on the semiconductor structure of the present invention, and the applicant intends to include any existing structure and structures that may be developed to achieve the same functionality in the future.

In the above description, the technical details of some routine operations are not described in detail. However, those skilled in the art should understand that various means in the prior art can be used to form layers, regions, etc. of desired shapes. In addition, in order to form the same structure, those skilled in the art can also design a method that is not exactly the same as the method described above.

The above description is only for illustration and description of the present invention, not intended to be exhaustive and limitative of the present invention. Accordingly, the invention is not limited to the described embodiments. The scope of the invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims (13)

1. a manufacture method for semiconductor structure, comprises the following steps:

A) p-type field-effect transistor is provided, comprises the source-drain area forming described transistor,

B) on described p-type field-effect transistor, tension stress layer is formed,

C) remove a part of tension stress layer, the edge of the tension stress layer of reservation, between described p-type field-effect transistor and shallow trench isolation, makes the tension stress layer retained produce compression in channels,

D) anneal, make described semiconductor structure can remember stress from tension stress layer, and activate source/drain region; And

E) remaining tension stress layer is removed.

2. the method for claim 1, wherein described tension stress layer comprises and is selected from Si ₃n ₄, SiO ₂, at least one material in SiOF, SiCOH, SiCO, SiCON, SiON, PSG and BPSG.

3. the method for claim 1, wherein in step b) in, form described tension stress layer by depositing technics.

4. the method for claim 1, wherein in step c) in, remove a part of tension stress layer by selective etch.

5. the method for claim 1, wherein after step a) and step b) before, form etching stop layer by depositing technics.

6. method as claimed in claim 5, wherein, the material of described etching stop layer is different from the material of described tension stress layer.

7. method as claimed in claim 6, wherein, described etching stop layer comprises SiO ₂.

8. method as claimed in claim 4, wherein, step c) comprising:

Photoetching, to form the photoresist of predetermined pattern; And

With the photoresist of patterning for mask etches described tension stress layer.

9. method as claimed in claim 8, wherein, carrying out step c) after, on grid direction, the distance between outside the edge of the tension stress layer of reservation and grid is 0.02-0.2 μm.

10. the method for claim 1, wherein described p-type field-effect transistor comprises dummy grid, and described dummy grid comprises dummy grid conductor and gate medium.

11. methods as claimed in claim 10, wherein, in steps d) after, also comprise step e):

Remove described dummy grid conductor to form opening, and form grid in said opening.

12. methods as claimed in claim 11, wherein, in step e) in, remove described dummy grid conductor by etching technics, to expose the gate medium below described dummy grid conductor.

13. methods as claimed in claim 11, wherein, in step e) in, remove described dummy grid conductor and gate medium by etching technics, to expose the substrate below described gate medium.