CN102456404A - Non-volatile memory storage device, memory controller and data storage method - Google Patents

Abstract

A nonvolatile memory storage device, a memory controller and a data storage method are provided. The nonvolatile memory storage device comprises a connector, an energy storage circuit, a power supply conversion and supply circuit, a nonvolatile memory module, a memory controller and a buffer memory. The power conversion and supply circuit is used for converting the output voltage from the energy storage circuit into a first voltage for the nonvolatile memory module and a second voltage for the memory controller and the buffer memory. The memory controller is used for writing the data temporarily stored in the buffer memory into the nonvolatile memory module in a special writing mode when receiving a detection signal indicating that the input voltage is continuously less than the preset voltage within a preset time period or a detection signal indicating the non-activated state of the connector or a pause mode signal, a warm reset signal or a warm reset signal received from the host system.

Description

Non-volatile memory storage device, memory controller and data storage method

technical field

The present invention relates to a nonvolatile memory storage device, a memory controller and a data storage method, and in particular to a method capable of writing data in a buffer memory to a nonvolatile memory when the nonvolatile memory storage device is powered off. A non-volatile memory storage device, a memory controller and a data storage method of a non-volatile memory module.

Background technique

The rapid growth of digital cameras, mobile phones, and MP3 players has led to a rapid increase in consumer demand for storage media. Since non-volatile memory has the characteristics of non-volatile data, power saving, small size and no mechanical structure, it is suitable for portable applications and is most suitable for such portable battery-powered products. A flash drive is a storage device that uses NAND flash memory (FlashMemory) as a storage medium. For example, through the Universal Serial Bus (USB), the user can easily plug and unplug the flash drive to the host to transmit digital data.

Because the speed of writing data to the flash memory is much lower than the transmission speed of the USB connected to the host, generally speaking, the buffer memory will be configured in a non-volatile memory storage device to temporarily store data from the host. data. In particular, when the host sends the write command and the data to be written to the non-volatile memory storage device, the memory control circuit (also known as the memory controller) will indicate that it has been completed after temporarily storing the data in the buffer memory. The message of the write command is returned to the host, so that the host can continue to execute the next operation, thereby improving the operating efficiency.

However, since the flash drive operates on the power provided by the host through the USB, if the user pulls the flash drive from the host while data still exists in the buffer memory, the data temporarily stored in the buffer memory will be lost. will be lost. Based on this, how to write the data temporarily stored in the buffer memory into the flash memory when the non-volatile memory storage device is powered off is a subject that those skilled in the art are working on.

Contents of the invention

The invention provides a memory storage system, a memory controller and a data storage method, which can write the data temporarily stored in the buffer memory into the non-volatile memory module when the power is cut off.

An exemplary embodiment of the present invention provides a nonvolatile memory storage device, which includes a connector, an energy storage circuit, a power conversion and supply circuit, a nonvolatile memory module, a memory controller, and a buffer memory. The connector is used to electrically connect to the host system. The energy storage circuit is used for receiving an input voltage and providing an output voltage. The power conversion and supply circuit is electrically connected to the energy storage circuit and used for converting the output voltage into a first voltage and a second voltage. The non-volatile memory module is electrically connected to the power conversion and supply circuit and operates at the first voltage. The memory controller is electrically connected to the connector, the energy storage circuit and the power conversion and supply circuit and operates at the second voltage. Buffer memory is used to temporarily store data. The memory controller is used to write the data temporarily stored in the buffer memory to the non-volatile memory module when receiving a signal, wherein the signal is a detection indicating that the input voltage is continuously lower than a preset voltage for a preset period of time The signal is either a detection signal indicating an inactive state of the connector or a suspend mode signal, a warm reset signal or a warm reset signal received from the host system.

An exemplary embodiment of the present invention provides a memory controller, which includes a host interface, a memory interface, a memory management circuit, and a buffer memory. The host interface is used to electrically connect to the host system. The memory interface is used to electrically connect to the non-volatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. The buffer memory is electrically connected to the memory management circuit and used for temporarily storing data from the host system. The memory management circuit is used for writing the data temporarily stored in the buffer memory into the non-volatile memory module when receiving the signal. In addition, the memory management circuit is also used to turn on a switch included in the energy storage circuit.

An exemplary embodiment of the present invention provides a data storage method used in a non-volatile memory module. This data storage method includes judging whether the input voltage from the host system is continuously lower than the preset voltage within the preset time; and when the input voltage from the host system is continuously lower than the preset voltage within the preset time, temporarily storing The data in the memory is written to the non-volatile memory module.

An exemplary embodiment of the present invention provides a data storage method used in a non-volatile memory module. The data storage method includes: judging whether the inactive state of the connector is detected; and writing the data temporarily stored in the buffer memory to the non-volatile memory module when the inactive state of the connector is detected.

An exemplary embodiment of the present invention provides a data storage method used in a non-volatile memory module. The data storage method includes: determining whether a suspend mode signal, a warm reset signal or a warm reset signal is received from the host system; and when a suspend mode signal, a warm reset signal or a warm reset signal is received from the host system , write the data temporarily stored in the buffer memory to the non-volatile memory module.

Based on the above, the memory storage system, memory controller and data storage method of the exemplary embodiments of the present invention can write the data temporarily stored in the buffer memory into the flash memory when the non-volatile memory storage device is powered off.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1A illustrates a host system and a non-volatile memory storage device according to an exemplary embodiment of the present invention.

FIG. 1B is a schematic diagram of a computer, an input/output device and a non-volatile memory storage device according to an exemplary embodiment of the present invention.

FIG. 1C is a schematic diagram of a host system and a non-volatile memory storage device according to another exemplary embodiment of the present invention.

FIG. 2 is a schematic block diagram illustrating the nonvolatile memory storage device shown in FIG. 1A .

FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment of the invention.

FIG. 4 and FIG. 5 are exemplary schematic diagrams of a management memory module according to an exemplary embodiment of the present invention.

6-8 are examples of writing data to a non-volatile memory module according to an exemplary embodiment of the present invention.

FIG. 9 is a schematic diagram of an energy storage circuit according to an exemplary embodiment of the present invention.

FIG. 10 is a flowchart of a data storage method according to an exemplary embodiment of the present invention.

FIG. 11 is a flowchart of a data storage method according to another exemplary embodiment of the present invention.

FIG. 12 is a flowchart of a data storage method according to another exemplary embodiment of the present invention.

[Description of main component symbols]

1000: host system

1100: computer

1102: Microprocessor

1104: random access memory

1106: Input/Output Device

1108: System bus

1110: data transmission interface

1202: Mouse

1204: keyboard

1206: display

1208: Printer

1212: Pen drive

1214: memory card

1216: SSD

1310: Digital camera

1312: SD card

1314: MMC card

1316: memory stick

1318: CF card

1320: Embedded storage device

100: Non-volatile memory storage device

102: Connector

104: memory controller

106: Non-volatile memory module

108: Energy storage circuit

110: Power conversion and supply circuit

202: memory management circuit

204: host interface

206: memory interface

208: buffer memory

210: Error checking and correction circuit

304(0)～304(R): physical block

402: data area

404: Spare area

406: System area

408: Substitution Area

510(0)～510(H): logic block

Vin: input voltage

Vout: output voltage

D: diode

R1: first resistor

R2: second resistor

S: switch

C: capacitor bank

GND: ground terminal

Detailed ways

Generally speaking, a nonvolatile memory storage device (also called a nonvolatile memory storage system) includes a nonvolatile memory module and a memory controller (also called a memory control circuit). Typically, a non-volatile memory storage device is used with a host system such that the host system can write data to or read data from the non-volatile memory storage device.

FIG. 1A is a diagram illustrating a host system and a non-volatile memory storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 1A , the host system 1000 generally includes a computer 1100 and an input/output (I/O) device 1106 . The computer 1100 includes a microprocessor 1102 , a random access memory (random access memory, RAM) 1104 , a system bus 1108 and a data transmission interface 1110 . The input/output device 1106 includes a mouse 1202, a keyboard 1204, a monitor 1206 and a printer 1208 as shown in FIG. 1B. It must be understood that the device shown in FIG. 1B is not limited to the I/O device 1106, and the I/O device 1106 may also include other devices.

In the embodiment of the present invention, the non-volatile memory storage device 100 is electrically connected with other components of the host system 1000 through the data transmission interface 1110 . Data can be written into the non-volatile memory storage device 100 or read from the non-volatile memory storage device 100 through the operation of the microprocessor 1102 , the random access memory 1104 and the input/output device 1106 . For example, the non-volatile memory storage device 100 may be a non-volatile memory storage device such as a flash drive 1212, a memory card 1214, or a solid state drive (Solid State Drive, SSD) 1216 as shown in FIG. 1B.

In general, host system 1000 can be virtually any system that can store data. Although in this exemplary embodiment, the host system 1000 is illustrated as a computer system, however, in another exemplary embodiment of the present invention, the host system 1000 may be a digital camera, video camera, communication device, audio player or video player and other systems. For example, when the host system is a digital camera (video camera) 1310, the nonvolatile memory storage device 100 is an SD card 1312, an MMC card 1314, a memory stick (memory stick) 1316, a CF card 1318 or an embedded The storage device 1320 (as shown in FIG. 1C ). The embedded storage device 1320 includes an embedded multimedia card (EmbeddedMMC, eMMC). It is worth mentioning that the embedded multimedia card is directly electrically connected to the substrate of the host system.

FIG. 2 is a schematic block diagram illustrating the nonvolatile memory storage device shown in FIG. 1A .

Referring to FIG. 2 , the nonvolatile memory storage device 100 includes a connector 102 , a memory controller 104 , a nonvolatile memory module 106 , an energy storage circuit 108 and a power conversion and supply circuit 110 .

The connector 102 is electrically connected to the memory controller 104 and used for electrically connecting to the host system 1000 . That is to say, the non-volatile memory storage device 100 is connected to the corresponding connection port on the host system 1000 through the connector 102 .

In this exemplary embodiment, the connector 102 is a Universal Serial Bus (USB) connector. However, it must be understood that the present invention is not limited thereto, and in another exemplary embodiment of the present invention, the connector 102 may also be an Institute of Electrical and Electronic Engineers (Institute of Electrical and Electronic Engineers, IEEE) 1394 connector, a high-speed peripheral component Connection interface (Peripheral Component Interconnect Express, PCI Express) connector, Serial Advanced Technology Attachment (Serial Advanced Technology Attachment, SATA) connector, secure digital (Secure Digital, SD) interface connector, memory stick (Memory Stick, MS) interface Connector, Multi Media Card (Multi Media Card, MMC) interface connector, Compact Flash (Compact Flash, CF) interface connector, Integrated Device Electronics (Integrated Device Electronics, IDE) connector or other suitable connectors.

The memory controller 104 is used to execute a plurality of logic gates or control instructions implemented in the form of hardware or firmware, and write, read and erase data in the non-volatile memory module 106 according to the instructions of the host system 1000 operation. In particular, the memory controller 104 executes the data storage method and the memory management method of the exemplary embodiment to perform data writing, reading, erasing and block management operations on the non-volatile memory module 106 . The data storage method and memory management method according to exemplary embodiments of the present invention will be described in detail below with the accompanying drawings.

The non-volatile memory module 106 is electrically connected to the memory controller 104 and used for storing data written by the host system 1000 . Non-volatile memory module 106 includes a plurality of physical blocks. Each physical block has a plurality of pages, wherein the physical pages belonging to the same physical block can be written independently and erased simultaneously. In more detail, a physical block is the smallest unit of erasing. That is, each physical block contains a minimum number of memory cells that are erased. A physical page is the smallest unit of programming. That is, a physical page is the minimum unit for writing data. Each physical page generally includes a data bit field and a redundant bit field. The data bit area is used to store user data, and the redundant bit area is used to store system data (eg, error checking and correction code). The configuration of the data bit area and the redundant bit area is common knowledge known to those skilled in the art, and will not be described in detail here. In this exemplary implementation, the non-volatile memory module 106 is a multi-level memory cell (Multi Level Cell, MLC) NAND flash memory module. However, the present invention is not limited thereto, and the non-volatile memory module 106 can also be a single-level memory cell (Single Level Cell, SLC) NAND flash memory module, other flash memory modules, or other memory modules with the same characteristics.

The energy storage circuit 108 is electrically connected to the memory controller 104 . In this exemplary embodiment, the power required for the operation of the non-volatile memory storage device 100 is provided by the host system 1000 through the connector 102 . Here, the energy storage circuit 108 is used to receive an input voltage from the host system 1000 through the connector 102 and provide an output voltage to be supplied to the memory controller 104 and the nonvolatile memory module 106 of the nonvolatile memory storage device 100 . Especially, in this exemplary embodiment, the energy storage circuit 108 is also used to store a backup electric energy, and when the host system 1000 interrupts the power supply, the energy storage circuit 108 will provide the backup electric energy as an output voltage to supply to the memory controller 104 and non-volatile memory module 106 are used for short-term operation.

The power conversion and supply circuit 110 is electrically connected to the energy storage circuit 108 and used to control the power of the non-volatile memory storage device 100 . Specifically, the power conversion and supply circuit 110 converts the received voltage (that is, the output voltage provided by the energy storage circuit 108 ) into a first voltage and a second voltage, and provides the first voltage to the nonvolatile The memory module 106 and provides the second voltage to the memory controller 104 .

FIG. 3 is a schematic block diagram of a memory controller according to an exemplary embodiment of the invention.

Referring to FIG. 3 , the memory controller 104 includes a memory management circuit 202 , a host interface 204 , a memory interface 206 and a buffer memory 208 .

The memory management circuit 202 is used to control the overall operation of the memory controller 104 to perform operations such as writing, reading, and erasing data. For example, the memory management circuit 202 has a plurality of control commands, and when the portable non-volatile memory storage device 100 is operating, these control commands will be executed to implement the data storage method and the memory management method according to the exemplary embodiment.

For example, in this exemplary embodiment, the control instructions of the memory management circuit 202 are implemented in the form of firmware. For example, the memory management circuit 202 has a microprocessor unit (not shown) and a ROM (not shown), and these control instructions are burned into the ROM. When the portable non-volatile memory storage device 100 is operating, these control instructions will be executed by the microprocessor unit to implement the data storage method and the memory management method according to the embodiment of the present invention.

In another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 may also be stored in a specific area of the non-volatile memory module 106 (for example, a system area dedicated to storing system data in the memory module) in the form of program codes. . In addition, the memory management circuit 202 has a microprocessor unit (not shown), a read only memory (not shown) and a random access memory (not shown). In particular, the ROM has a driver code segment, and when the memory controller 104 is enabled, the microprocessor unit will first execute the driver code segment to load the control instructions stored in the non-volatile memory module 106. into the random access memory of the memory management circuit 202. Afterwards, the microprocessor unit executes these control instructions to execute the data storage method and the memory management method of the exemplary embodiments of the present invention. In addition, in another exemplary embodiment of the present invention, the control instructions of the memory management circuit 202 may also be implemented in a hardware form.

The host interface 204 is electrically connected to the memory management circuit 202 and used for receiving and identifying commands and data transmitted by the host system 1000 . That is to say, the commands and data transmitted by the host system 1000 are transmitted to the memory management circuit 202 through the host interface 204 . In this exemplary embodiment, the host interface 204 is a USB interface corresponding to the connector 102 . However, it must be understood that the present invention is not limited thereto, and the host interface 204 can also be a PATA interface, IEEE 1394 interface, PCI Express interface, SD interface, MS interface, MMC interface, CF interface, SATA interface, IDE interface or other suitable Data transfer interface.

The memory interface 206 is electrically connected to the memory management circuit 202 and used for accessing the non-volatile memory module 106 . That is to say, the data to be written into the non-volatile memory module 106 is converted into a format acceptable to the non-volatile memory module 106 via the memory interface 206 .

The buffer memory 208 is electrically connected to the memory management circuit 202 and used for temporarily storing data and instructions from the host system 1000 or data from the non-volatile memory module 106 . Here, the buffer memory 208 is a static random access memory (Static Random-Access Memory, SRAM). However, it must be understood that the present invention is not limited thereto. In another exemplary embodiment, the buffer memory 208 may also be a Dynamic Random Access Memory (DRAM) or other suitable memory. In addition, in another embodiment of this example, the buffer memory 208 can also be configured independently of the memory controller 104 . That is to say, the buffer memory 208 can be configured outside the memory controller 104 and electrically connected to the memory controller 104 through a bus.

In an exemplary embodiment of the invention, the memory controller 104 further includes an error checking and correction circuit 210 . The error checking and correcting circuit 210 is electrically connected to the memory management circuit 202 and used for executing error checking and correcting procedures to ensure the correctness of data. For example, when the memory management circuit 202 receives a write command from the host system 1000, the error checking and correction circuit 210 will generate a corresponding error checking and correcting code (Error Checking and Correcting Code, ECC Code) for the data corresponding to the write command ), and the memory management circuit 202 writes the data corresponding to the write command and the corresponding ECC code into the non-volatile memory module 106 . Afterwards, when the memory management circuit 202 reads data from the non-volatile memory module 106, it will simultaneously read the error checking and correction code corresponding to the data, and the error checking and correction circuit 210 will use the error checking and correction code pair The read data is subjected to error checking and correction procedures.

FIG. 4 and FIG. 5 are exemplary schematic diagrams of a management memory module according to an exemplary embodiment of the present invention.

It must be understood that when describing the operation of the physical blocks of the non-volatile memory module 106 herein, terms such as "extract", "swap", "group", "rotate" to manipulate the physical blocks are logical the concept of. That is to say, the actual location of the physical block of the memory module 106 is not changed, but the physical block of the non-volatile memory module 106 is logically operated.

Referring to FIG. 4, the memory management circuit 202 logically groups the physical blocks 304(0)-304(R) of the non-volatile memory module 106 into a data area 402, a spare area 404, a system area 406, and a replacement area 408. .

The physical blocks of the data area 402 and the spare area 404 are used to store data from the host system 1000 . Specifically, the data area 402 is a physical block of stored data, and the physical block of the spare area 404 is used to replace the physical block of the data area 402 . Therefore, the physical blocks of the spare area 404 are empty or usable physical blocks, that is, no recorded data or invalid data marked as useless. That is, the physical blocks in the spare area have been erased, or the physical blocks extracted before the physical blocks in the spare area are extracted for storing data will be erased. Therefore, the physical blocks in the spare area are usable physical blocks.

The physical blocks logically belonging to the system area 406 are used to record system data, wherein the system data includes the manufacturer and model of the memory chip, the number of physical blocks of the memory chip, the number of physical pages of each physical block, and the like.

Physical blocks that logically belong to the replacement area 408 are replacement physical blocks. For example, when the non-volatile memory module 106 leaves the factory, 4% of the physical blocks are reserved for replacement. That is to say, when the physical blocks in the data area 402, the spare area 404, and the system area 406 are damaged, the physical blocks reserved in the replacement area 408 are used to replace the damaged physical blocks (that is, bad physical blocks) block (badblock)). Therefore, if a normal physical block still exists in the replacement area 408 and the physical block is damaged, the memory management circuit 202 will extract a normal physical block from the replacement area 408 to replace the damaged physical block. If there is no normal physical block in the replacement area 408 and the physical block is damaged, the memory management circuit 202 will declare the entire nonvolatile memory storage device 100 as a write-protected (write protect) state, and can no longer write input data.

In particular, the number of physical blocks in the data area 402 , the spare area 404 , the system area 406 and the replacement area 408 varies according to different memory specifications. In addition, it must be understood that during the operation of the nonvolatile memory storage device 100 , the grouping relationship of the physical blocks associated with the data area 402 , the spare area 404 , the system area 406 and the replacement area 408 will change dynamically. For example, when a physical block in the spare area is damaged and replaced by a physical block in the replacement area, the original physical block in the replacement area will be associated with the spare area.

Referring to FIG. 5 , as mentioned above, the physical blocks of the data area 402 and the spare area 404 store data written by the host system 1000 in an alternate manner. In this exemplary embodiment, the memory management circuit 202 allocates logical addresses to the host system 1000 to facilitate data access in the physical blocks that store data in the aforementioned alternate manner. In particular, the memory management circuit 202 will group the provided logical addresses into logical blocks 510(0)-510(H), and map the logical blocks 510(0)-510(H) to the physical addresses of the data area 402 blocks. For example, when the non-volatile memory storage device 100 is formatted with a file system (for example, FAT 32) by the operating system of the host system 1000, the logical blocks 510(0)˜510(H) are respectively mapped to the data area 402 The physical blocks 304(0)-304(D) of . That is to say, one logical block maps one physical block in the data area 402 . Here, the memory management circuit 202 will establish a logical block-physical block mapping table (logical block-physical block mapping table) to record the mapping relationship between the logical block and the physical block.

6-8 are examples of writing data to a non-volatile memory module according to an exemplary embodiment of the present invention.

Please refer to FIGS. 6-8 at the same time. For example, in the mapping state where the logical block 510(0) is mapped to the physical block 304(0), when the memory controller 104 receives a write command from the host system 1000 and When writing data to the logical address belonging to the logical block 510(0), the memory management circuit 202 will identify that the logical block 510(0) is currently mapped to the physical block 304( 0) and extract the physical block 304(D+1) from the spare area 404 as a replacement physical block to replace the physical block 304(0). However, when the memory management circuit 202 writes new data into the physical block 304(D+1), the memory management circuit 202 will not immediately move all valid data in the physical block 304(0) to the physical block 304(D+1) and erase physical block 304(0). Specifically, the memory management circuit 202 will write the valid data before the physical page in the physical block 304(0) (that is, the data in the 0th physical page and the 1st physical page of the physical block 304(0) ) to the 0th physical page and the 1st physical page of the physical block 304 (D+1) (as shown in FIG. 6 ), and write new data to the 2nd physical page of the physical block 304 (D+1). The physical page and the third physical page (as shown in FIG. 7 ). At this point, the memory management circuit 202 completes the writing operation. Because the valid data in the physical block 304(0) may become invalid in the next operation (for example, a write command), the valid data in the physical block 304(0) is immediately moved to the physical block 304( D+1) may cause unnecessary movement. In addition, data must be sequentially written to the physical pages in the physical block. Therefore, the memory management circuit 202 will only move the valid data before the physical pages to be written.

In this exemplary embodiment, the operation of temporarily maintaining the parent-child transient relationship (ie, physical block 304(0) and physical block 304(D+1)) is called opening (open) the parent-child block, and The original physical block is called a parent physical block and the replacement physical block is called a child physical block.

Afterwards, when the contents of the physical block 304(0) and the physical block 304(D+1) need to be actually merged, the memory management circuit 202 will combine the physical block 304(0) with the physical block 304(D+1). 1) The data is integrated into one physical block, thereby improving the efficiency of the physical block. Here, the operation of merging the parent and child blocks is called closing the parent and child blocks. For example, as shown in FIG. 8 , when closing the parent and child blocks, the memory management circuit 202 will save the remaining valid data in the physical block 304 (0) (that is, the fourth physical page ~ 4th physical page of the physical block 304 (0) The data in the (K)th physical page) is copied to the 4th physical page to the (K)th physical page of the replacement physical block 304 (D+1), and then the physical block 304 (0) is erased and associated to The spare area 404 , meanwhile, associates the physical block 304 (D+1) with the data area 402 . That is to say, the memory management circuit 202 remaps the logical block 510(0) to 304(D+1) in the logical block-physical block mapping table. In addition, in this exemplary embodiment, the memory management circuit 202 creates a physical block table (not shown) in the spare area to record the physical blocks currently associated with the spare area. It is worth mentioning that the memory management circuit 202 needs to use more storage space of the buffer memory 252 to store management variables when the mother-child block is enabled, so as to record more detailed storage status. For example, these management variables will record which physical pages of the physical block 304(0) and the physical block 304(D+1) the valid data belonging to the logical block 510(0) are distributed into (as shown in FIG. 7 Show). Based on this, during the operation of the portable non-volatile memory storage device 100, the number of sets of parent and child blocks is limited. Therefore, when the portable non-volatile memory storage device 100 receives a write command from the host system 1000, if the number of groups of the mother and child blocks that have been opened reaches the upper limit, the memory management circuit 202 needs to close at least one group that is currently open. parent-child block (i.e., execute the operation of closing the parent-child block) to execute the write command. Here, the writing operations shown in FIGS. 6 to 8 are called normal writing modes.

FIG. 9 is a schematic diagram of an energy storage circuit according to an exemplary embodiment of the present invention.

Referring to FIG. 9 , the energy storage circuit 1110 includes a diode D, a first resistor R1 , a second resistor R2 , a switch S and a capacitor group C. Referring to FIG. The anode of the diode D is used to receive the input voltage Vin from the host system 1000 , and the cathode of the diode D is used to provide the output voltage Vout. The first terminal of the first resistor R1 and the first terminal of the second resistor R2 are electrically connected to the cathode of the diode D. The first end of the switch S is electrically connected to the second end of the second resistor R2 , and the control end of the switch S is electrically connected to the memory controller 104 . The first end of the capacitor set C is electrically connected to the second end of the switch S and to the second end of the first resistor R1 , and the second end of the capacitor set C is electrically connected to the ground. In this exemplary embodiment, the capacitor group C may include a plurality of capacitors connected in parallel.

In this exemplary embodiment, when the nonvolatile memory storage device 100 is electrically connected to the host system 1000 , the capacitor bank C stores backup electric energy. The backup power stored in the capacitor group C is used to maintain the short-term operation of the memory controller 104 and the non-volatile memory module 106 when the input voltage provided by the host system 1000 is insufficient. In this exemplary embodiment, for example, the capacity of the capacitor bank is 470˜2200 microfarads (uF). It is worth mentioning that, in this exemplary embodiment, the first resistor R1 is to avoid a large amount of inrush current (inrush current) caused by the capacitor group C when the nonvolatile memory storage device 100 is electrically connected to the host system 1000 . For example, the resistance value of the first resistor R1 is 200 ohms. In particular, the first resistor R1 will cause the output voltage Vout to be low, so that the memory controller 104 and the non-volatile memory module 106 cannot work normally. Based on this, in this exemplary embodiment, when receiving a small computer standard interface (Small Computer Standard Interface, SCSI) from the host system 1000 for the first time, the memory controller 104 (or the memory management circuit of the memory controller 104 202) will turn on the switch S, so that the switch S is closed to connect the second resistor R2 in parallel, thereby increasing the output voltage Vout. For example, the resistance value of the second resistor R2 is 1 ohm. Based on this, when the switch S is turned on, the memory controller 104 and the non-volatile memory module 106 can operate under the normal operating voltage according to the command of the host system 1000 .

It must be understood that, in the exemplary embodiment of the present invention, when the memory controller 104 (or the memory management circuit 202 of the memory controller 104 ) receives the SCSI command from the host system 1000 for the first time after being enabled, Turn on switch S. However, the present invention is not limited thereto. In another exemplary embodiment of the present invention, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104 ) may also receive a message from the host for the first time after being enabled. When the system 1000 writes a command, the switch S is turned on. Or, in another exemplary embodiment of the present invention, the memory controller 104 (or the memory management circuit 202 of the memory controller 104 ) is enabled and waits for a delay time before turning on the switch S. For example, this delay time is 3 seconds.

In an exemplary embodiment of the present invention, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104 ) detects a detection signal corresponding to the input voltage Vin. And, when the detection signal indicates that the input voltage Vin is continuously lower than a preset voltage (for example, 4 volts (V)) within a preset time (for example, 10 seconds), the memory controller 104 (for example, the memory controller 104 The memory management circuit 202) will start the special write mode to write the data temporarily stored in the buffer memory 208 into the non-volatile memory module 106.

In particular, in the special write mode, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) extracts a physical block from the spare area 404, and stores the data temporarily stored in the buffer memory 208 Write sequentially in the physical pages of the extracted physical blocks. Specifically, the data temporarily stored in the buffer memory 208 will be sequentially written starting from the 0th physical page of the extracted physical block. That is to say, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) will not write data according to the corresponding relationship of the logical access addresses (that is, the general writing shown in FIGS. 6-8 ). model). Based on this, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104 ) can write the data temporarily stored in the buffer memory 208 into the non-volatile memory module 106 in less time.

In the special write mode, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) will record a special mark in the redundant bit area of the physical page of the extracted physical block, so as to write Physical blocks that operate in entry mode are distinguished from other physical blocks. In addition, the logical address (i.e., mapping information) corresponding to the data temporarily stored in the buffer memory 208 will also be recorded in the redundant bit area of the physical page of the extracted physical block, so as to facilitate non-volatile memory storage When the device 100 is restarted, the memory controller 104 (e.g., the memory management circuit 202 of the memory controller 104) can correctly move (i.e., rewrite) the data written in the special write mode to the mapped physical in the block.

It must be understood that, in this exemplary embodiment, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) records the special mark and Mapping information corresponding to data temporarily stored in the buffer memory 208 . However, the present invention is not limited thereto. In another exemplary embodiment of the present invention, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) may also extract another physical block from the spare area 404 as a special The physical blocks are used to record which physical pages of which physical blocks are used to write the data temporarily stored in the buffer memory 208 and the mapping information corresponding to the data temporarily stored in the buffer memory 208 in a special writing mode. Afterwards, when the non-volatile memory storage device 100 is restarted, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) will read the relevant mapping information from this special physical block, thereby converting Data written in the special write mode is correctly moved to the mapped physical block. It is worth mentioning that the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104 ) presets certain physical blocks to be used as special physical blocks. For example, in an exemplary embodiment, physical block 304(D+1)˜physical block 304(D+10) are used as special physical blocks. Based on this, when the non-volatile memory storage device 100 is restarted, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) only needs to confirm the physical block 304(D+1)～physical block 304 (D+10), it can be known whether the data temporarily stored in the buffer memory 208 was written into the non-volatile memory module 106 in a special write mode when the power was turned off last time, thus Determine whether to perform the operation of moving data.

In addition, in another exemplary embodiment of the present invention, in the special write mode, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) can also only use one of the physical pages of the extracted physical block The data temporarily stored in the buffer memory 208 is written to the physical page belonging to the lower page.

Specifically, NAND flash memory can be divided into SLC NAND flash memory and MLC NAND flash memory according to the number of bits that can be stored in each memory cell. When writing into memory cells of the SLC NAND flash memory (also known as a program), only single-level programming can be performed, so each memory cell can only store one bit of data. The programming of the physical block of the MLCNAND flash memory can be divided into multiple stages. For example, taking a 4-layer memory cell as an example, the programming of the physical block can be divided into two stages. The first stage is the writing part of the lower page, whose physical characteristics are similar to single-level memory cell (Single Level Cell, SLC) NAND flash memory. The second stage is the programmable upper page, in which the writing speed of the lower page will be faster than that of the upper page. Therefore, the pages of each physical block can be divided into slow pages (ie, upper pages) and fast pages (ie, lower pages). Similarly, in the case of 8-layer memory cells or 16-layer memory cells, the memory cells will include more pages and will be written in more stages. Here, the page with the fastest writing speed is called the lower page, and the other pages with the slower writing speed are collectively called the upper page. For example, the upper page includes multiple pages with different write speeds. In addition, in other embodiments, the upper page may also be the page with the slowest writing speed, or the page with the slowest writing speed and part of which is faster than the slowest writing speed page. For example, in a 4-layer memory cell, the lower page is the page with the fastest writing speed and the second fastest writing speed, and the upper page is the page with the slowest writing speed and the second slowest writing speed. In this exemplary embodiment, the physical pages of the physical block can be classified as belonging to the upper page or the lower page according to their write characteristics.

Based on this, by writing the data temporarily stored in the buffer memory 208 using only the physical page belonging to the lower page among the physical pages of the extracted physical block, the data temporarily stored in the buffer memory 208 can be shortened further. the time required.

In addition, in an exemplary embodiment of the present invention, the non-volatile memory storage device 100 is configured with an access indicator light (not shown) to indicate that the non-volatile memory storage device 100 is in an access operation. For example, the access indicator is an LED light.

In particular, in another exemplary embodiment of the present invention, in the special writing mode, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104 ) may further turn off the access LED to reduce power consumption.

It is worth mentioning that, in this exemplary embodiment, when the detection signal indicates that the input voltage Vin is continuously lower than the preset voltage within the preset time, the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104 ) will Start special write mode. However, the present invention is not limited thereto. For example, in another exemplary embodiment of the present invention, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104 ) may also detect signal to initiate a special write mode. Specifically, in an example where the connector 102 is USB 3.0, when the superspeed (superspeed) connection between the nonvolatile memory storage device 100 and the host system 1000 fails, the memory controller 104 (for example, the memory controller 104 The memory management circuit 202) of the connector 102 will detect the inactive (SS.Inactive) state of the connector 102, thereby determining that the non-volatile memory storage device 100 may be unplugged from the host system 1000 abnormally. In addition, in another exemplary embodiment of the present invention, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104 ) may also respond to a suspend mode (suspend mode) signal from the host system 1000, a warm reset ( warm reset) signal or hot reset (hotreset) signal to start the special write mode, where the warm reset signal is used to re-drive the system without voltage drop, and the hot reset signal is to reorganize the system Data and a signal that causes the system to start at the starting point of the system.

FIG. 10 is a flowchart of a data storage method according to an exemplary embodiment of the present invention.

Referring to FIG. 10 , during the operation of the nonvolatile memory storage device 100 , in step S1001 , it is determined whether the input voltage from the host system 1000 is continuously lower than the preset voltage within a preset time. Specifically, in step S1001, the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104) will continuously detect the input voltage from the host system 1000 to determine whether the input voltage is continuously less than preset voltage.

If the input voltage from the host system continues to be lower than the preset voltage within the preset time, it is determined in step S1003 whether the buffer memory 208 temporarily stores data that has not been written into the non-volatile memory 106 .

If there is data temporarily stored in the buffer memory 208 that has not yet been written into the non-volatile memory 106, the data temporarily stored in the buffer memory 208 in step S1005 will be written into the non-volatile memory in a special write mode. in sex memory 106. If the input voltage from the host system is not continuously lower than the preset voltage within the preset time or there is no data temporarily stored in the buffer memory 208 that has not yet been written into the non-volatile memory 106, step S1001 will be executed to Continue to detect the input voltage from the host system. In this exemplary embodiment, the process shown in FIG. 10 will continue to operate after the non-volatile memory storage device 100 is enabled until the non-volatile memory storage device 100 stops operating.

FIG. 11 is a flowchart of a data storage method according to another exemplary embodiment of the present invention.

Referring to FIG. 11 , during the operation of the nonvolatile memory storage device 100 , in step S1101 it is determined whether the inactive state of the connector 102 is detected. Specifically, in step S1101 , the memory controller 104 (for example, the memory management circuit 202 of the memory controller 104 ) determines whether an inactive state of the connector 102 is detected.

If the inactive state of the connector 102 is detected, in step S1103 it is determined whether there is data not yet written into the non-volatile memory 106 temporarily stored in the buffer memory 208 .

If there is temporarily stored data in the buffer memory 208 that has not yet been written into the non-volatile memory 106, the data temporarily stored in the buffer memory 208 will be written into the non-volatile memory in a special write mode in step S1105. in memory 106.

If the inactive state of the connector 102 is not detected or there is no data temporarily stored in the buffer memory 208 that has not been written into the non-volatile memory 106, then step S1101 will be executed to continue to detect the input from the host system Voltage. Similarly, in this exemplary embodiment, the process shown in FIG. 11 will continue to operate after the non-volatile memory storage device 100 is enabled until the non-volatile memory storage device 100 stops operating.

FIG. 12 is a flowchart of a data storage method according to another exemplary embodiment of the present invention.

Referring to FIG. 12 , during the operation of the nonvolatile memory storage device 100 , it is determined whether a suspend mode signal, a warm reset signal or a warm reset signal from the host system 1000 is received in step S1201 . Specifically, in step S1201 , the memory controller 104 (eg, the memory management circuit 202 of the memory controller 104 ) determines whether a suspend mode signal, a warm reset signal or a warm reset signal is received from the host system 1000 .

If a suspend mode signal, a warm reset signal or a warm reset signal from the host system 1000 is received, it will be judged in step S1203 whether there is any temporary storage in the buffer memory 208 that has not yet been written into the non-volatile memory 106. data.

If there is temporarily stored data in the buffer memory 208 that has not yet been written into the non-volatile memory 106, the data temporarily stored in the buffer memory 208 will be written into the non-volatile memory in a special write mode in step S1205. in memory 106.

If no suspend mode signal, warm reset signal or warm reset signal from the host system 1000 is received or there is no data temporarily stored in the buffer memory 208 that has not yet been written into the non-volatile memory 106, then step S1201 It will be executed to continue to determine whether a suspend mode signal, a warm reset signal or a warm reset signal from the host system 1000 is received. Similarly, in this exemplary embodiment, the process shown in FIG. 11 will continue to operate after the non-volatile memory storage device 100 is enabled until the non-volatile memory storage device 100 stops operating.

To sum up, the nonvolatile memory storage device, memory controller and data storage method of the exemplary embodiments of the present invention can avoid loss of data in the buffer memory caused by abnormal power failure.

Although the present invention has been disclosed as above with the embodiments, it is not intended to limit the present invention. Those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention When depending on what is defined in the appended claims shall prevail.

Claims (18)

1. nonvolatile memory stores device comprises:

A connector is in order to be electrically connected to a host computer system;

One tank circuit is in order to receive an input voltage and an output voltage is provided;

One power source conversion and supply circuit electrically connect this tank circuit and in order to this output voltage is converted to one first voltage and one second voltage;

One non-volatile memory module electrically connects this power source conversion and supply circuit and operates in this first voltage;

One Memory Controller electrically connects this connector, this tank circuit and this power source conversion and supply circuit and operates in this second voltage; And

One memory buffer electrically connects this Memory Controller, in order to temporary data,

Wherein this Memory Controller writes to this non-volatile memory module in order to these data that when receiving a signal, will be temporarily stored in this memory buffer, and wherein this signal is in order to indicate this input voltage in a Preset Time, to continue less than a detection signal of a predeterminated voltage or in order to a detection signal or a park mode signal, a warm reset signal or a warm reset signal for from this host computer system, being received of the unactivated state of indicating this connector.

2. nonvolatile memory stores device as claimed in claim 1, wherein this tank circuit comprises:

One diode has an anode and a negative electrode, and this anode is in order to receive this input voltage, and this negative electrode is in order to provide this output voltage;

One first end that one first resistance and one second resistance, one first end of this first resistance are electrically connected to this negative electrode and this second resistance of this diode is electrically connected to this negative electrode of this diode;

One switch, one first end of this switch is electrically connected to one second end of this second resistance and a control end of this switch is electrically connected to this Memory Controller; And

One capacitance group, one first end of this capacitance group are electrically connected to one second end of this first resistance and one second end of this switch and one second end of this capacitance group and are electrically connected to an earth terminal,

Wherein this Memory Controller also in order to when receive the small computer standard interface SCSI instruction that comes from this host computer system the back first time that is enabled, is opened this switch.

3. nonvolatile memory stores device as claimed in claim 1, wherein this tank circuit comprises:

One diode has an anode and a negative electrode, and this anode is in order to receive this input voltage, and this negative electrode is in order to provide this output voltage;

One first end that one first resistance and one second resistance, one first end of this first resistance are electrically connected to this negative electrode and this second resistance of this diode is electrically connected to this negative electrode of this diode;

One switch, one first end of this switch is electrically connected to one second end of this second resistance and a control end of this switch is electrically connected to this Memory Controller; And

One capacitance group, one first end of this capacitance group are electrically connected to one second end of this first resistance and one second end of this switch and one second end of this capacitance group and are electrically connected to an earth terminal,

Wherein this Memory Controller also in order to receive for the first time in the back that is enabled when coming from one of this host computer system and writing instruction, is opened this switch.

4. nonvolatile memory stores device as claimed in claim 1, wherein this tank circuit comprises:

One diode has an anode and a negative electrode, and this anode is in order to receive this input voltage, and this negative electrode is in order to provide this output voltage;

One first end that one first resistance and one second resistance, one first end of this first resistance are electrically connected to this negative electrode and this second resistance of this diode is electrically connected to this negative electrode of this diode;

One switch, one first end of this switch is electrically connected to one second end of this second resistance and a control end of this switch is electrically connected to this Memory Controller; And

One capacitance group, one first end of this capacitance group are electrically connected to one second end of this first resistance and one second end of this switch and one second end of this capacitance group and are electrically connected to an earth terminal,

Wherein this Memory Controller is opened this switch also in order to after being enabled and waiting for a time delay.

5. nonvolatile memory stores device as claimed in claim 1, wherein this non-volatile memory module comprises that a plurality of physical blocks and these physical blocks are grouped into a data field and a spare area at least,

Wherein this Memory Controller extracts a physical blocks and this data that will be temporary in this memory buffer write in this physical blocks from this spare area when receiving this signal.

6. nonvolatile memory stores device as claimed in claim 5, wherein this Memory Controller only uses the physical page that belongs to a lower page among a plurality of physical pages of this physical blocks of from this spare area, being extracted to write these data that are temporary in this memory buffer when receiving this signal.

7. nonvolatile memory stores device as claimed in claim 5, wherein this Memory Controller also in order to when receiving this signal in a redundant digit district of this physical blocks record to a map information that should data.

8. nonvolatile memory stores device as claimed in claim 5, wherein this Memory Controller also in order to when receiving this signal, from this spare area, extract another physical blocks and in this another physical blocks of being extracted record to a map information that should data.

9. nonvolatile memory stores device as claimed in claim 5 also comprises an access pilot lamp,

Wherein this Memory Controller is also in order to close this access pilot lamp when receiving this signal.

10. Memory Controller comprises:

One HPI is in order to be electrically connected to a host computer system;

One memory interface is in order to be electrically connected to a non-volatile memory module;

One memory management circuitry electrically connects this HPI and this memory interface; And

One memory buffer electrically connects this memory management circuitry and in order to temporary data that come from this host computer system,

Wherein this memory management circuitry writes to this non-volatile memory module in order to these data that when receiving a signal, will be temporarily stored in this memory buffer; Wherein this signal is in order to indicate this input voltage in a Preset Time, to continue less than a detection signal of a predeterminated voltage or in order to a detection signal or a park mode signal, a warm reset signal or a warm reset signal for from this host computer system, being received of the unactivated state of indicating this connector

Wherein this memory management circuitry also is included in the switch in the tank circuit in order to unlatching.

11. a date storage method is used for a non-volatile memory module, this date storage method comprises:

Judge whether an input voltage that comes from this host computer system continues less than a predeterminated voltage in a Preset Time; And

When this input voltage that comes from this host computer system continues less than this predeterminated voltage, data that are temporarily stored in the memory buffer are write to this non-volatile memory module in this Preset Time.

12. date storage method as claimed in claim 11, wherein this non-volatile memory module has a plurality of physical blocks and these physical blocks are grouped into a data field and a spare area at least,

Wherein will be temporarily stored in the step that these data in this memory buffer write to this non-volatile memory module comprises:

From this spare area, extract a physical blocks; And

These data that are temporary in this memory buffer are write in this physical blocks.

13. date storage method as claimed in claim 12; Wherein each these physical blocks comprises that speed that a plurality of physical pages and these physical pages belong to the page on a lower page and respectively and write data to the physical page that belongs to this lower page is faster than writing data to the speed that belongs to the physical page of the page on this

Wherein will be temporary in the step that these data in this memory buffer write in this physical blocks comprises: only use the physical page that belongs to this lower page among these physical pages of this physical blocks of from this spare area, being extracted to write these data that are temporary in this memory buffer.

14. date storage method as claimed in claim 12 wherein will be temporarily stored in the step that these data in this memory buffer write to this non-volatile memory module and also comprise:

Record is to a map information that should data in a redundant digit district of this physical blocks.

15. date storage method as claimed in claim 12 wherein will be temporarily stored in the step that these data in this memory buffer write to this non-volatile memory module and also comprise:

From this spare area, extract another physical blocks and in this another physical blocks of being extracted record to a map information that should data.

16. date storage method as claimed in claim 12 wherein will be temporarily stored in the step that these data in this memory buffer write to this non-volatile memory module and also comprise:

Close an access pilot lamp.

17. a date storage method is used for a non-volatile memory module, this date storage method comprises:

Judge whether to detect a unactivated state of a connector; And

When detecting this unactivated state of this connector, data that are temporarily stored in the memory buffer are write to this non-volatile memory module.

18. a date storage method is used for a non-volatile memory module, this date storage method comprises:

Judge whether from this host computer system, to receive a park mode signal, a warm reset signal or a warm reset signal; And

When from this host computer system, receiving this park mode signal, this warm reset signal or this warm reset signal, data that are temporarily stored in the memory buffer are write to this non-volatile memory module.

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