CN102468170A - Forming method of stress layer for improving NFET performance - Google Patents
Forming method of stress layer for improving NFET performance Download PDFInfo
- Publication number
- CN102468170A CN102468170A CN2010105341606A CN201010534160A CN102468170A CN 102468170 A CN102468170 A CN 102468170A CN 2010105341606 A CN2010105341606 A CN 2010105341606A CN 201010534160 A CN201010534160 A CN 201010534160A CN 102468170 A CN102468170 A CN 102468170A
- Authority
- CN
- China
- Prior art keywords
- nfet
- stressor layers
- improving
- formation method
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 61
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 34
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 34
- 238000002955 isolation Methods 0.000 claims abstract description 25
- 238000011282 treatment Methods 0.000 claims abstract description 18
- 230000008569 process Effects 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 33
- 230000015572 biosynthetic process Effects 0.000 claims description 32
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 28
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 28
- 238000000137 annealing Methods 0.000 claims description 17
- 238000005229 chemical vapour deposition Methods 0.000 claims description 17
- 229910052757 nitrogen Inorganic materials 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 7
- 238000005224 laser annealing Methods 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 abstract description 17
- 229910052739 hydrogen Inorganic materials 0.000 abstract description 17
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 abstract description 11
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 abstract description 11
- 229910052796 boron Inorganic materials 0.000 abstract description 11
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 238000002161 passivation Methods 0.000 abstract description 5
- 230000035882 stress Effects 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 6
- 230000005669 field effect Effects 0.000 description 5
- 239000002800 charge carrier Substances 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000006353 environmental stress Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000004151 rapid thermal annealing Methods 0.000 description 2
- 238000004062 sedimentation Methods 0.000 description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 125000001475 halogen functional group Chemical group 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000011221 initial treatment Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A method of forming a stress layer for improving NFET performance, comprising the steps of: providing a substrate comprising an NFET; forming a silicon oxide layer on the surface of the NFET; performing nitridation treatment on the silicon oxide layer to form an isolation layer; and forming a stress layer on the surface of the isolation layer. In summary, the present invention forms a silicon oxide layer on a substrate comprising an NFET and then performs a nitridation process on the silicon oxide layer to form an isolation layer. The isolation layer can prevent hydrogen in a stress layer formed subsequently from entering the active region, so that the hydrogen and boron are prevented from reacting, loss of boron passivation and diffusion is reduced, threshold voltage of the NFET is effectively improved, and performance of the NFET is improved.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, relate in particular to a kind of formation method of stressor layers of the NFET of improvement performance.
Background technology
Along with the continuous development of semiconductor technology, the integrated degree of integrated circuit is increasingly high, and size of devices also constantly reduces.Device size constantly reduces to cause the performance of device to receive very big influence.For example, when the length of raceway groove narrows down to 50nm when following, device begins to show short-channel effect, comprises problems such as carrier mobility decline, threshold voltage increase.
In order to reduce the problem that causes owing to dimension shrinks, can improve the stress of device channel region through stress technique, thereby improve the mobility of charge carrier rate, improve the performance of device.Specifically be to introduce biaxial strain or uniaxial strain,, improve the response device speed of MOSFET, improve the performance of MOSFET device to increase channel region mobility of charge carrier speed through channel region at Metal-oxide-semicondutor FET (MOSFET).Provide the mode of this stress to be called as stress memory technique (SMT, Stress Memorization Technique).Concrete stress memory technique is the inherent strain material layer of NFET (N-type Field-Effect Transistor, n type field effect transistor) or PFET (P-type Field-Effect Transistor, the p type field effect transistor) top at semiconductor device; Be stressor layers, (said stressor layers can be silicon nitride layer etc.), and carry out high-temperature annealing process so that stress is remembered on semiconductor device; For example remember in grid polycrystalline silicon or diffusion region or silicon substrate,, reduce the current suffered obstruction of charge carrier through the spacing of stress changes at the silicon atom at the grid lower channel place of FET; Just be equivalent to reduce resistance; Thereby semiconductor device heating amount and energy consumption all can reduce, for example, and for n type MOSFET; Increase the spacing of the silicon atom at grid lower channel place, thereby the speed of service can get a promotion then.Remove strain gauge material then, make stress be able to keep and improve the mobility in electronics or hole, thereby improve the whole performance of semiconductor.
In the prior art, the main flow material of stressor layers is a silicon nitride, and silicon nitride layer adopts chemical vapour deposition technique (CVD, Chemical Vapor Deposition) method deposit to form usually.Yet the silicon nitride layer that adopts chemical vapour deposition technique to form contains a large amount of hydrogen bond (for example Si-H key, N-H key), in follow-up high-temperature annealing process; Si-H key and N-H key can break to form a part of hydrogen, and hydrogen is to external environment with to inner silicon oxide layer diffusion, and silicon oxide layer does not have blocking effect for hydrogen; So hydrogen can pass through the silicon oxide layer diffusion and arrive active area (S/D district), in active area, replaces with dopant ion boron, quickens the passivation and the diffusion of boron; Cause the loss of boron in the active area; Influence the threshold voltage (Vt, Threshold Voltage) of NFET, and then reduce the performance of NFET.
The patent No. is that the United States Patent (USP) of US2009/0289284 discloses a kind of heavily stressed silicon nitride layer that is used to improve the NFET performance.Above-mentioned patent discloses; After deposit forms silicon nitride layer; Silicon nitride layer is carried out nitrogen treatment (Nitrogen gas treatment) or UV treatment (Ultra-violet treatment), removing a large amount of Si-H key in the silicon nitride layer, thereby improve the pressure of answering of stressor layers.Yet above-mentioned patent reckons without and in silicon nitride layer, also contains a large amount of N-H keys; The N-H key is more stable than the Si-H key; The temperature of destroying the N-H key is more than 1000 ℃, and the disclosed UV treatment temperature of above-mentioned patent is at 250 ℃ to 500 ℃, so nitrogen treatment and UV treatment all can't be removed the N-H key; Silicon nitride layer still has a large amount of hydrogen bonds, in the subsequent anneal technical process, still has a large amount of hydrogen to diffuse to the performance that active area influences device.
Summary of the invention
The technical problem that the present invention will solve is; Provide a kind of and can intercept effectively that hydrogen diffuses to active area (S/D district) in the stressor layers that on the NFET device, forms; Reduce in annealing process hydrogen to the passivation and the diffusion influence of dopant ion boron in the active area, the method for the NFET performance of improvement.
For addressing the above problem, the present invention provides a kind of formation method of stressor layers of the NFET of improvement performance, may further comprise the steps:
Provide one comprise NFET substrate;
Form silicon oxide layer on said NFET surface;
Said silicon oxide layer is carried out nitrogen treatment, to form isolation layer;
Form stressor layers on said isolation layer surface.
Further, the formation method of said silicon oxide layer is a chemical vapour deposition technique.Preferable, the thickness of said silicon oxide layer is
Preferably, said nitrogen treatment step comprises, utilizes the said silicon oxide layer of plasma bombardment that contains nitrogen.
Preferable, the said plasma bombardment time is 10 seconds～120 seconds.
Preferable, the power of said plasma bombardment is 50W～200W.
Optional, said plasma is N
2, N
2O, NH
3Or N
2H
2Further, the material of said isolation layer is a silicon oxynitride.
Further, the thickness of said isolation layer is
Further, the material of said stressor layers is a silicon nitride.
Preferably, the formation step of said stressor layers comprises, utilizes chemical vapour deposition technique to form silicon nitride layer; Said silicon nitride layer is carried out annealing process.
Preferable, the thickness of said stressor layers is
Preferable, the method for said silicon nitride layer being carried out annealing process comprises high annealing and laser annealing.
Preferable, the temperature of said silicon oxide layer being carried out annealing process is 900～1100 ℃.
In sum; The present invention carries out nitrogen treatment on said silicon oxide layer surface; To form one deck isolation layer on said silicon oxide layer surface; Said isolation layer can effectively stop hydrogen in annealing process, to get in the active area of NFET, thereby avoids hydrogen and boron to react and cause boron passivation and diffusion, has effectively improved the performance of NFET device.
Description of drawings
Fig. 1 is the schematic flow diagram of the formation method of the stressor layers of improving the NFET performance in one embodiment of the invention.
Fig. 2 is for forming the structural representation after the said stressor layers of improving the NFET performance among the embodiment among the present invention.
Embodiment
For making content of the present invention clear more understandable,, content of the present invention is described further below in conjunction with Figure of description.Certainly the present invention is not limited to this specific embodiment, and the general replacement that those skilled in the art knew also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes sketch map to carry out detailed statement, and when instance of the present invention was detailed, for the ease of explanation, sketch map did not amplify according to general ratio is local, should be with this as to qualification of the present invention.
Core concept of the present invention is: contain on the substrate of NFET form silicon oxide layer after, silicon oxide layer is carried out nitrogen treatment, to form isolation layer, on said isolation layer, form stressor layers.Said stressor layers is a silicon nitride layer, forms through chemical vapour deposition (CVD), contains a large amount of hydrogen bonds.The hydrogen bond that said isolation layer can intercept in the silicon nitride layer gets into active area, avoid with active area in the boron reaction, thereby effective improvement threshold voltage.
Fig. 1 is the schematic flow diagram of method one embodiment described in the present invention.Fig. 2 is for forming the structural representation after the said stressor layers of improving the NFET performance among the embodiment among the present invention.Please refer to Fig. 1 and combine structural representation shown in Figure 2, the said formation method of improving the stressor layers of NFET performance may further comprise the steps:
S01: provide one comprise NFET substrate 100; Said substrate 100 can be selected from N type substrate, P type substrate also can be silicon (SOI) on the insulating barrier etc.Be formed with n type field effect transistor (NFET) on the said substrate 100; Accomplished initial treatment at substrate 100 this moment; For example, conventional shallow trench isolation is from formation, trap injection, the formation of gate-dielectric 102 and the expansion/haloing (Halo) that is used to spread of (STI) 104, the injection of active area (source electrode, drain electrode) 101 etc.
S02: form silicon oxide layer 103 on said NFET surface; Further, the formation method of said silicon oxide layer 103 is a chemical vapour deposition technique.In the present embodiment; The thickness of said silicon oxide layer 103 is that the formation of
said silicon oxide layer 103 can be through the thickness of parameter controlled oxidation silicon layers 103 such as sedimentation time, gas flow and environmental stress in the control chemical vapor deposition method; By those skilled in the art are known, so do not give unnecessary details at this.Said silicon oxide layer 103 is as resilient coating, in subsequent etch is removed the technology of stressor layers, plays the effect that stops layer.
S03: said silicon oxide layer 103 is carried out nitrogen treatment, to form isolation layer 105; In the present embodiment, the material of the isolation layer 105 of formation is a silicon oxynitride.The thickness of said isolation layer 105 is
Preferably, said nitrogen treatment step comprises, utilizes the said silicon oxide layer 103 of plasma bombardment that contains nitrogen.The said plasma bombardment time is 10 seconds～120 seconds, and the power of said plasma bombardment is 50W～200W, with the isolation layer 105 that forms above-mentioned thickness.Said plasma is N
2, N
2O, NH
3Or N
2H
2, or above-mentioned any several kinds combination, the effect of said nitrogen treatment is to form silicon oxynitride layer on silicon oxide layer 103 surfaces.So other nitrogenous gases all can be used as thought range of the present invention.
S04: form stressor layers 106 on said isolation layer 105 surfaces.The material of said stressor layers 106 is a silicon nitride, and said stressor layers 106 thickness are
Preferably, the formation step of said stressor layers 106 comprises, utilizes chemical vapour deposition technique to form silicon nitride layer; Said silicon nitride layer is carried out annealing process.
Further; Form silicon nitride layer and can be plasma activated chemical vapour deposition (Plasma Enhanced CVD) or low-pressure chemical vapor deposition (LPCVD) or thermalization chemical vapour deposition (CVD) (RTCVD) formation fast, the reacting gas of said silicon nitride layer comprises SiH4, SiH
2Cl
2, SiH
2F
2Or above-mentioned several kinds combination, other form the method for stressor layers in addition, and for example high density plasma deposition (HDP) etc. is all within thought range of the present invention.The formation of said silicon nitride layer can be through the thickness of parameter control silicon nitride layers such as sedimentation time, gas flow and environmental stress in the control chemical vapor deposition method, by those skilled in the art are known, so do not give unnecessary details at this.
Further, the method for said silicon nitride layer being carried out annealing process comprises high annealing and laser annealing, and the temperature that said silicon oxide layer carries out annealing process is 900～1100 ℃.In the present embodiment; Said high temperature rapid thermal annealing temperature is 1000～1200 ℃, and said laser annealing temperature is 1000～1300 ℃, and said annealing process not only makes the stress of stressor layers fully remember on the NFET; Said high temperature rapid thermal annealing helps the diffusion of dopant ion in the active area 101 simultaneously; And laser annealing gets in the lattice of substrate silicon atom dopant ion, thereby produces charge carrier, improves device performance.
In sum, the present invention contain on the substrate of NFET form silicon oxide layer after, silicon oxide layer is carried out nitrogen treatment, to form isolation layer.The hydrogen that said isolation layer can intercept in the stressor layers of follow-up formation gets into active area, thereby avoids hydrogen and boron to react, and has reduced the loss of boron passivation and diffusion, thereby has effectively improved the NFET threshold voltage, improves the performance of NFET.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (14)
1. a formation method of improving the stressor layers of NFET performance is characterized in that, may further comprise the steps:
The substrate that comprises NFET is provided;
Form silicon oxide layer on said NFET surface;
Said silicon oxide layer is carried out nitrogen treatment, to form isolation layer;
Form stressor layers on said isolation layer surface.
2. the formation method of improving the stressor layers of NFET performance as claimed in claim 1 is characterized in that the formation method of said silicon oxide layer is a chemical vapour deposition technique.
3. the formation method of improving the stressor layers of NFET performance as claimed in claim 1; It is characterized in that the thickness of said silicon oxide layer is
4. the formation method of improving the stressor layers of NFET performance as claimed in claim 1 is characterized in that, said nitrogen treatment step comprises, utilizes the said silicon oxide layer of plasma bombardment that contains nitrogen.
5. the formation method of improving the stressor layers of NFET performance as claimed in claim 4 is characterized in that, the said plasma bombardment time is 10 seconds～120 seconds.
6. the formation method of improving the stressor layers of NFET performance as claimed in claim 4 is characterized in that the power of said plasma bombardment is 50W～200W.
7. the formation method of improving the stressor layers of NFET performance as claimed in claim 4 is characterized in that, the said plasma that contains nitrogen is N
2, N
2O, NH
3Or N
2H
2
8. the formation method of improving the stressor layers of NFET performance as claimed in claim 1 is characterized in that the material of said isolation layer is a silicon oxynitride.
9. the formation method of improving the stressor layers of NFET performance as claimed in claim 1; It is characterized in that the thickness of said isolation layer is
10. the formation method of improving the stressor layers of NFET performance as claimed in claim 1 is characterized in that the material of said stressor layers is a silicon nitride.
11. the formation method of improving the stressor layers of NFET performance as claimed in claim 1; It is characterized in that the thickness of said stressor layers is
12. the formation method of improving the stressor layers of NFET performance as claimed in claim 1 is characterized in that, the formation step of said stressor layers comprises, utilizes chemical vapour deposition technique to form silicon nitride layer; Said silicon nitride layer is carried out annealing process.
13. the formation method of improving the stressor layers of NFET performance as claimed in claim 12 is characterized in that the method for said silicon nitride layer being carried out annealing process comprises high annealing and laser annealing.
14. the formation method of improving the stressor layers of NFET performance as claimed in claim 12 is characterized in that, the temperature of said silicon oxide layer being carried out annealing process is 900～1100 ℃.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105341606A CN102468170A (en) | 2010-11-05 | 2010-11-05 | Forming method of stress layer for improving NFET performance |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105341606A CN102468170A (en) | 2010-11-05 | 2010-11-05 | Forming method of stress layer for improving NFET performance |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102468170A true CN102468170A (en) | 2012-05-23 |
Family
ID=46071645
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010105341606A Pending CN102468170A (en) | 2010-11-05 | 2010-11-05 | Forming method of stress layer for improving NFET performance |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102468170A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839815A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming NMOS transistor |
| CN106952810A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | Fabrication method of semiconductor structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1757101A (en) * | 2003-02-28 | 2006-04-05 | 东京毅力科创株式会社 | Substrate processing method |
| CN101167177A (en) * | 2005-05-26 | 2008-04-23 | 应用材料股份有限公司 | Integrated Process for Fabricating Stressed Transistor Structures |
| US20080296631A1 (en) * | 2007-05-28 | 2008-12-04 | Neng-Kuo Chen | Metal-oxide-semiconductor transistor and method of forming the same |
| CN101320693A (en) * | 2007-06-06 | 2008-12-10 | 台湾积体电路制造股份有限公司 | Manufacturing method of semiconductor element |
| CN101847661A (en) * | 2009-03-26 | 2010-09-29 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing the same |
-
2010
- 2010-11-05 CN CN2010105341606A patent/CN102468170A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1757101A (en) * | 2003-02-28 | 2006-04-05 | 东京毅力科创株式会社 | Substrate processing method |
| CN101167177A (en) * | 2005-05-26 | 2008-04-23 | 应用材料股份有限公司 | Integrated Process for Fabricating Stressed Transistor Structures |
| US20080296631A1 (en) * | 2007-05-28 | 2008-12-04 | Neng-Kuo Chen | Metal-oxide-semiconductor transistor and method of forming the same |
| CN101320693A (en) * | 2007-06-06 | 2008-12-10 | 台湾积体电路制造股份有限公司 | Manufacturing method of semiconductor element |
| CN101847661A (en) * | 2009-03-26 | 2010-09-29 | 株式会社半导体能源研究所 | Semiconductor device and method for manufacturing the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103839815A (en) * | 2012-11-21 | 2014-06-04 | 中芯国际集成电路制造(上海)有限公司 | Method for forming NMOS transistor |
| CN103839815B (en) * | 2012-11-21 | 2017-09-26 | 中芯国际集成电路制造(上海)有限公司 | The forming method of nmos pass transistor |
| CN106952810A (en) * | 2016-01-06 | 2017-07-14 | 中芯国际集成电路制造(上海)有限公司 | Fabrication method of semiconductor structure |
| CN106952810B (en) * | 2016-01-06 | 2020-07-10 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor structure |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8294224B2 (en) | Devices and methods to improve carrier mobility | |
| US8809141B2 (en) | High performance CMOS transistors using PMD liner stress | |
| US20060154411A1 (en) | CMOS transistors and methods of forming same | |
| CN102105977A (en) | Performance enhancement in PMOS and NMOS transistors on the basis of silicon/carbon material | |
| US9349823B2 (en) | Methods of scaling thickness of a gate dielectric structure, methods of forming an integrated circuit, and integrated circuits | |
| CN101071774A (en) | Metal oxide semiconductor field effect transistor and its manufacturing method | |
| CN102468171A (en) | Method for improving stress effect of stress layer | |
| CN102569082B (en) | Method for manufacturing embedded germanium-silicon strain PMOS (P-channel Metal Oxide Semiconductor) structure | |
| CN102468170A (en) | Forming method of stress layer for improving NFET performance | |
| CN102915968A (en) | Manufacturing method of CMOS (Complementary Metal oxide Semiconductor) transistor | |
| CN102280379B (en) | A kind of manufacture method of strained silicon nmos device | |
| CN102024706B (en) | Method for manufacturing semiconductor device | |
| KR100508867B1 (en) | Method for fabricating the p-channel MOS transistor and CMOS transistor | |
| CN116936363A (en) | NMOSFET manufacturing method and NMOSFET using stress memory technology | |
| KR100850138B1 (en) | Gate dielectric layer of semiconductor device and method for forming the same | |
| US20070004114A1 (en) | Sacrificial capping layer for transistor performance enhancement | |
| US9064888B2 (en) | Forming tunneling field-effect transistor with stacking fault and resulting device | |
| CN101232019A (en) | Semiconductor device and manufacturing method thereof | |
| CN103377933A (en) | Manufacturing method of MOS transistors | |
| CN103377935B (en) | The manufacture method of MOS transistor | |
| US20100025742A1 (en) | Transistor having a strained channel region caused by hydrogen-induced lattice deformation | |
| US7102183B2 (en) | MOS transistor | |
| CN103367155B (en) | The formation method of nmos pass transistor and MOS transistor | |
| CN105529267A (en) | MOSFET device and manufacturing method thereof and electronic device | |
| JP6110686B2 (en) | Manufacturing method of semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHA Effective date: 20130619 Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Free format text: FORMER OWNER: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION Effective date: 20130619 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: 201203 PUDONG NEW AREA, SHANGHAI TO: 100176 DAXING, BEIJING |
|
| TA01 | Transfer of patent application right |
Effective date of registration: 20130619 Address after: 100176 No. 18 Wenchang Avenue, Beijing economic and Technological Development Zone Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 No. 18 Zhangjiang Road, Shanghai Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20120523 |